JPS5852575A - Power-factor transducer - Google Patents

Power-factor transducer

Info

Publication number
JPS5852575A
JPS5852575A JP15181181A JP15181181A JPS5852575A JP S5852575 A JPS5852575 A JP S5852575A JP 15181181 A JP15181181 A JP 15181181A JP 15181181 A JP15181181 A JP 15181181A JP S5852575 A JPS5852575 A JP S5852575A
Authority
JP
Japan
Prior art keywords
voltage
circuit
proportional
output
filter circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15181181A
Other languages
Japanese (ja)
Inventor
Kenzo Akamatsu
赤松 建三
Tadashi Hashimoto
正 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15181181A priority Critical patent/JPS5852575A/en
Publication of JPS5852575A publication Critical patent/JPS5852575A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00Arrangements for measuring electric power or power factor
    • G01R21/006Measuring power factor

Abstract

PURPOSE:To realize a transducer having high accuracy without being influenced by a temperature of a circuit to be measured, by executing addition and subtraction of each DC voltage being proportional to a power of a phase difference of 2 AC inputs, and reference voltage, in a prescribed ratio. CONSTITUTION:An AC input of a phase diffenence (phi) is applied to a terminal 1 and 2, respectively, is waveform-shaped by a comparator 11 and 12, its exclusive OR is taken by a gate 13, and square wave voltage 53 of a duty ratio being proportional to the phase difference (phi) is obtained. The voltage 53 passes through a switch S1 and a filter A1, is converted to DC voltage E21, and is supplied to S2. In the same way, voltage E22 being proportional to phi<2> is obtained and is supplied to S3. Moreover, voltage E23 being proportional to phi<3> is obtained. Subsequently, the voltage E22 and E23 are subjected to addition and subtraction in the prescribed ratio, respectively, with reference voltage Ez by an adding and subtracting circuit AD, and DC voltage being proportional to a power-factor of a circuit to be measured is obtained.

Description

【発明の詳細な説明】 この発明は、被測定回路の力率に比例し、た直流電圧を
出力するようにした力率トランスデユーサに関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power factor transducer that outputs a DC voltage proportional to the power factor of a circuit under test.

従来、力率トランスデユーサは二つの交流入力の位相差
φに比例した直流電圧を出力する位相弁別回路と、ダイ
オード等を使用した折線近似のφcrs d ’9;!
換回路で構成されていた。
Conventionally, a power factor transducer has a phase discrimination circuit that outputs a DC voltage proportional to the phase difference φ between two AC inputs, and a polygonal line approximation using a diode, etc. φcrs d '9;!
It consisted of a switching circuit.

しかしながら、ダイオ−ド等を使用した折線近似のφ−
ctf1$ F m回路は変換精度が悪く、また周囲温
度変化や時間的なドリフト等に影響されるため高精度の
力率計測(τは適していなかった。
However, the φ-
The ctf1$F m circuit has poor conversion accuracy and is affected by ambient temperature changes and temporal drift, so it was not suitable for high-precision power factor measurement (τ).

この発明け、」二連のよう乃実情に着目してなされたも
ので、スイッチm’f e+′・とフィルタ回路を使用
した位相差φのベキ乗回路を使用することによって、−
一可φ変換を行ない高精度の力率トランスデユーサを提
供しようとするものである。
This invention was made by paying attention to the actual situation of two series, and by using a power circuit of the phase difference φ using a switch m'fe+' and a filter circuit, -
The present invention attempts to provide a highly accurate power factor transducer that performs one-possible φ conversion.

ここで、力率前φを位相差φのベキ乗に関して表わす。Here, the power factor before φ is expressed in terms of the power of the phase difference φ.

邸φを≠についてテーラ−展開すると次の(1)式のよ
うに表わせる。
When the residence φ is subjected to Taylor expansion with respect to ≠, it can be expressed as the following equation (1).

一般的に力率トランスデユーサは、実用上刃率0.5〜
1の範囲が測定できればよいので、力率の範囲をα5〜
1として可φをφに関して次の(2)式のように表わす
ことも可能である。
In general, power factor transducers have blade factors of 0.5 to 0.5 in practice.
Since it is sufficient to be able to measure the range of 1, the power factor range is α5~
It is also possible to express φ as shown in the following equation (2) with respect to φ.

邸φ中1−α522φ+0.068φ  ・・・(2)
(2)式に具体的な数値を代入してφ−煎φ変換精度に
ついて求め、(2)式による囲φ値と可φの真値の比較
を表1に示す。
Residenceφ middle 1-α522φ+0.068φ...(2)
By substituting specific numerical values into equation (2), the φ-determined φ conversion accuracy is determined, and Table 1 shows a comparison between the enclosed φ value and the true value of possible φ based on equation (2).

表1 表1の通り(2)式による部φ値は真の邸φ値に対し誤
差僅少である。
Table 1 As shown in Table 1, the part φ value obtained by equation (2) has a small error with respect to the true residence φ value.

従って、この発明の回路は(2)式を算出するように構
成されたものである。
Therefore, the circuit of the present invention is configured to calculate equation (2).

以下、この発明の一実施例を図によって説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第1図はこの発明の力率トランスデユーサの一実施例を
示す図で、図中、(1)および(2)はそれぞれ被測定
回路の交流人力41および42を印加する入力端子、(
111およびθりはそれぞれ入力端子(1)および(2
)に印加される交流入力を波形整形するコンパレータ、
i+31は前記コンパレータ(111および(121の
出力の排他的論理和を出力するゲート、S+、82およ
びS3はそれぞれの制御端子G+、GzおよびG3の電
圧がハイのときのみONするスイッチ、AT。
FIG. 1 is a diagram showing an embodiment of the power factor transducer of the present invention, in which (1) and (2) are input terminals to which AC human power 41 and 42 of the circuit under test are applied, respectively;
111 and θ are input terminals (1) and (2), respectively.
), a comparator that shapes the waveform of the AC input applied to the
i+31 is a gate that outputs the exclusive OR of the outputs of the comparators (111 and (121); S+, 82, and S3 are switches that are turned on only when the voltages of the respective control terminals G+, Gz, and G3 are high; AT;

A2およびA3は入力信号を平滑するフィルタ、EZは
基準直流電圧、Q])、(イ)および(至)は位相差φ
に関して、それぞれφ、−一およびφ8に比例した直流
電圧が得られる端子、ADは基準電圧EZと端子(ホ)
および−にそれぞれ出力される直流電圧を前記(2)式
に基づく比率で加減算する加減算回路、(2)は力率に
比例した直流電圧をとり出す出力端子である。
A2 and A3 are filters that smooth the input signal, EZ is the reference DC voltage, Q]), (a) and (to) are the phase difference φ
, AD is the terminal where the DC voltage proportional to φ, -1 and φ8 is obtained, respectively, and AD is the reference voltage EZ and the terminal (H).
An adding/subtracting circuit adds and subtracts the DC voltages outputted to and - respectively at a ratio based on equation (2) above, and (2) is an output terminal that takes out a DC voltage proportional to the power factor.

このように構成された力率トランスデユーサ回路におい
て、入力端子(1)および(2)にはそれぞれ第2図(
1)および(2)に示すような位相差φの交流入力41
および42が印加される。これらの入力はコンパレータ
(11)およびG21によって、それぞれ第2図(3)
および(4)に示す矩形波電圧51および52に波形整
形される。これらの矩形波電圧51と52はゲー)Hで
排他的論理和がとられ、第2図(5)に示す位相差φに
比例したデユーティ比の矩形波電圧53が得られる。該
矩形波電圧53はスイッチS+、S2およびS3の制御
端子Gj、G2およびG3に印加式れる。
In the power factor transducer circuit configured in this way, the input terminals (1) and (2) are connected to each other as shown in FIG.
AC input 41 with phase difference φ as shown in 1) and (2)
and 42 are applied. These inputs are input by comparators (11) and G21, respectively, as shown in Fig. 2 (3).
And the waveforms are shaped into rectangular wave voltages 51 and 52 shown in (4). These rectangular wave voltages 51 and 52 are exclusive-ORed with a gate (G)H, and a rectangular wave voltage 53 having a duty ratio proportional to the phase difference φ shown in FIG. 2 (5) is obtained. The square wave voltage 53 is applied to control terminals Gj, G2 and G3 of switches S+, S2 and S3.

まずスイッチS1は前記矩形波電圧53がハイのと@O
Nして基準電圧KZi通過でせ、第2図(6)に示すよ
うな波高値Kzの出力61が得られる。
First, switch S1 is activated when the rectangular wave voltage 53 is high.
N and the reference voltage KZi is passed through, and an output 61 having a peak value Kz as shown in FIG. 2 (6) is obtained.

この出力61はフィルタA1で平滑され、次の+3)式
で示すような入力の位相差φに比例した直流電圧E2+
に変換される。
This output 61 is smoothed by the filter A1, and the DC voltage E2+ is proportional to the input phase difference φ as shown in the following +3) formula.
is converted to

E21=  1’  −Ez   ・・・+3)π この電圧Fi2+はスイッチS2に供給され、スイッチ
S1と同様にして第2図(7)に示すような波高値E2
1の出力62が得られる。この出力62はフィルタA2
で平滑され、次の(4)式で示すような入力の位相差φ
に関しφ☆ に比例した直流電圧Fi22に変換される
E21= 1' -Ez...+3)π This voltage Fi2+ is supplied to the switch S2, and in the same way as the switch S1, the peak value E2 is set as shown in FIG. 2 (7).
1 output 62 is obtained. This output 62 is filter A2
The input phase difference φ is smoothed by the following equation (4).
is converted into a DC voltage Fi22 proportional to φ☆.

=<−j!−5・Ez   ・・・(4)π この電圧Fj22けスイッチS5に供給され、同様にし
て第2図(8)に示すような波高値B22の出力68が
得られる。この出力63はフィルタA3で平滑され、次
の(5)式で示すような入力の位相差φに関しφ8國比
例した直流電圧]l123に変換される。
=<-j! -5·Ez (4)π This voltage Fj22 is supplied to the switch S5, and in the same way, an output 68 having a peak value B22 as shown in FIG. 2 (8) is obtained. This output 63 is smoothed by a filter A3 and converted into a DC voltage 1123 proportional to φ8 with respect to the input phase difference φ as shown in the following equation (5).

=(11げ・E・   ・・・(5) π 以上のようにして得られた直流電圧E22とB2Mおよ
び基準電圧ILzは加減算回路ADによってそねそれ加
減算比率Kl、に2および1で加減算され、次の(6)
式で示す出力Fi2sが得られる。
=(11ge·E····(5) π The DC voltages E22 and B2M and the reference voltage ILz obtained in the above manner are added and subtracted by 2 and 1 to the addition/subtraction ratio Kl by the addition/subtraction circuit AD. , the next (6)
An output Fi2s shown by the formula is obtained.

F225=Ez−K 1E22 +に2 B2 sK、
+            B2 (01式において□= (1,522,−−=0.06
8に選べF9             F8 ば、(6)式に示す出力E25は前記(2)式と同比率
で加減算き才することになυ、入力の力率に比例する。
F225=Ez-K 1E22 +2 B2 sK,
+ B2 (In formula 01, □= (1,522,--=0.06
If F9 F8 is selected as 8, the output E25 shown in equation (6) will be added and subtracted at the same ratio as in equation (2), and will be proportional to the power factor of the input.

ここで、第1図の回路では第2図(5)〜(8)に示す
ように負仰1の出力は考慮されていないが、スイッチS
、、SzおよびB3をそれぞれ制御端子a1.a2およ
びG3がローのときに入力を反転した電圧をそれぞれフ
ィルタAl、A2およびA3に出力するように構成した
場合、そrしぞれフィルタAl、A2およびA3の出力
E2+、E22およびB25は次の1311i目)およ
び00式のようになる。
Here, in the circuit of FIG. 1, as shown in FIG. 2 (5) to (8), the output of the load 1 is not considered, but the switch S
, , Sz and B3 are respectively connected to control terminals a1. If a2 and G3 are configured to output inverted voltages to filters Al, A2 and A3, respectively, when a2 and G3 are low, the outputs E2+, E22 and B25 of filters Al, A2 and A3, respectively, are as follows. 1311i) and 00 formula.

φ−(π−φ) E 2  + =  −−−Fiz π = (”−1) Ez−031 π m−(π−の B22= −・Ft21 π ==(2$  1)s 、Ez π −−(4代−4$  +1)EZ  −04)F9  
   π B25=φ−(π−φ)、B22 π 次に、加減算回路ADでB21.B22.に23および
基準電圧Ezをそれぞれ加減算比率M+、 M2. M
5およびM4で加減算すると、次の(16)式で示す出
力E25が得られる。
φ−(π−φ) E 2 + = −−−Fiz π = (”−1) Ez−031 π m−(π− B22= −・Ft21 π ==(2$ 1)s , Ez π − -(4 generations -4$ +1)EZ -04)F9
π B25=φ−(π−φ), B22 π Next, B21. B22. 23 and the reference voltage Ez at the addition/subtraction ratio M+, M2. M
5 and M4, an output E25 shown by the following equation (16) is obtained.

E2s=M+Ez++M2E22+M3に23+λ4t
Kz=((rt)M1+(ア、−71) M2 + <
’?”、pr−十實−3)Ms4−M4)Bz2φ  
 4φ24φ +j藺φJFiz   ・・・(+6)(+6)式にお
いて、−Mi +M2−M5十M4=11−M + −
−−M2 十−Ms =6’、  ’ M2 +−MS
 =0.522π     π      π    
    F9     π98[3=α068に選べば
、前記(2)式と同比率で加減πB 算されることになり、(6]式と同様に力率に比例した
出力が得られる。
E2s=M+Ez++M2E22+23+λ4t for M3
Kz=((rt)M1+(a, -71) M2+<
'? ”, pr-Juji-3) Ms4-M4) Bz2φ
4φ24φ +j藺φJFiz ... (+6) In the (+6) formula, -Mi +M2-M50M4=11-M + -
--M2 10-Ms = 6', 'M2 +-MS
=0.522π π π
If F9 π98[3=α068 is selected, addition/subtraction πB will be calculated at the same ratio as in equation (2), and an output proportional to the power factor will be obtained as in equation (6).

また、第1図において、ゲー)1BとスイッチS1で構
成される位相弁別回路は位相の遅れと進みに関係なく、
位相差φの大きさにのみ比例したデユーティ比の矩形波
電圧を出力するようになっているが、一般によく使用さ
れているように入力の一方全π/2だけ移相して位相弁
別することにより、位相の遅れと進みに対応して増減す
るデユーティ比の矩形波電圧を出力するように構成した
場合にも同様にして位相差−に関してA2およびA8を
算出することによりφ−囲φ変換が可能であり、これも
この発明に含まれるものである。
In addition, in FIG. 1, the phase discrimination circuit composed of gate 1B and switch S1 is
It is designed to output a rectangular wave voltage with a duty ratio proportional only to the magnitude of the phase difference φ, but as is commonly used, one of the inputs can be phase-shifted by a total of π/2 to discriminate the phase. Therefore, even when configured to output a rectangular wave voltage with a duty ratio that increases or decreases in response to phase lag and advance, the φ-circle φ conversion can be performed by similarly calculating A2 and A8 with respect to the phase difference -. This is possible and is also included in this invention.

このよう々場合には第1図におけるフィルタA3の出力
電圧75:位相舵零を中心に正負反転するので、加減算
回路ADの入力部分03)に絶対値回路等を挿入するこ
とによっても実現できるものである。
In such a case, the output voltage 75 of the filter A3 in FIG. 1 is reversed around the zero phase rudder, so it can also be realized by inserting an absolute value circuit or the like into the input section 03) of the adder/subtractor circuit AD. It is.

U上のようにこの発明によれば、簡単な回1δ檜成で、
被測定回路の力率に比例した直流電圧が得られるもので
、ダイオード等ドリフトの原因になる素子を使用してい
ないため、周囲温度変化等に安定な高精度の力率トラン
スデユーサを提供することができるものである。
According to this invention as above, with a simple cycle 1δ hinoki,
It provides a DC voltage proportional to the power factor of the circuit under test, and because it does not use elements that cause drift such as diodes, it provides a highly accurate power factor transducer that is stable against changes in ambient temperature, etc. It is something that can be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明における力率トランスデユーサの一笑
軸側を示す回路図、第2図は第1図における各部の波形
図である。 図において、(1) (2)は入力端子、(11Q21
はコンパレータ、031はゲート、(ハ)は出力端子、
81〜S5はスイッチ、A1〜ASはフィルタ、ADは
加減算回路、Fizは基準電圧である。 代理人 葛野信− 手続補正書(自発) 特許庁長官殿 ■、小事件表示    特願昭56−151811号2
、発明の名称 力率トランスデユーサ 3、補正をする者 5、 補正の対象 明細書の発明の詳細な説明の欄 66  補正の内容 (1)明細書をつぎのとおり訂正する。 (2)
FIG. 1 is a circuit diagram showing a power factor transducer according to the present invention on the positive axis side, and FIG. 2 is a waveform diagram of each part in FIG. 1. In the figure, (1) and (2) are input terminals, (11Q21
is a comparator, 031 is a gate, (c) is an output terminal,
81 to S5 are switches, A1 to AS are filters, AD is an addition/subtraction circuit, and Fiz is a reference voltage. Agent Makoto Kuzuno - Procedural amendment (spontaneous) Mr. Commissioner of the Japan Patent Office■, Small case indication Patent application No. 151811/1982 2
, Name of the invention Power factor transducer 3, Person making the amendment 5, Detailed explanation of the invention column 66 of the specification to be amended Contents of the amendment (1) The specification is corrected as follows. (2)

Claims (2)

【特許請求の範囲】[Claims] (1)被測定回路の二つの交流入力の位相差−に比例し
たデユーティ比の矩形波電圧を出力する位相弁別回路、
この位相弁別回路の出力を平滑して位相差φに比例した
直流電圧を出力するフィルタ回路、このフィルタ回路の
出力端に接続された第1のスイッチ回路、この第1のス
イッチ回路の出力端に接続された第1のフィルタ回路、
この第1のフィルタ回路の出力端に接続された第2のス
イッチ回路、この第2のスイッチ回路の出力端に接続さ
れた第2のフィルタ回路、及び基準電圧と前記第1のフ
ィルタ回路の出力電圧と前記第2のフィルタ回路の出力
電圧を所定比率で加減算する加減算回路を備え、前記第
1のスイッチ回路及び第2のスイッチ回路を前記位相弁
別回路の出力で断続するようにしたことを特徴とする力
率トランスデユーサ。
(1) A phase discrimination circuit that outputs a rectangular wave voltage with a duty ratio proportional to the phase difference between two AC inputs of the circuit under test;
A filter circuit that smoothes the output of this phase discrimination circuit and outputs a DC voltage proportional to the phase difference φ, a first switch circuit connected to the output end of this filter circuit, and a first switch circuit connected to the output end of this first switch circuit. a first filter circuit connected;
a second switch circuit connected to the output end of the first filter circuit; a second filter circuit connected to the output end of the second switch circuit; and a reference voltage and the output of the first filter circuit. It is characterized by comprising an adding/subtracting circuit that adds and subtracts the voltage and the output voltage of the second filter circuit at a predetermined ratio, and the first switch circuit and the second switch circuit are switched on and off based on the output of the phase discrimination circuit. power factor transducer.
(2)前記加減算回路は前記基準電圧と前記フィルタ回
路の出力電圧と、前記第1のフィルタ回路の出力電圧と
前記第2のフィルタ回路の出力電圧を所定比率で加減算
するようにしたことを特徴とする特許請求の範囲第(1
)項記載の力率トランスデユーサ。
(2) The addition/subtraction circuit adds or subtracts the reference voltage, the output voltage of the filter circuit, the output voltage of the first filter circuit, and the output voltage of the second filter circuit at a predetermined ratio. Claim No. 1 (1)
) Power factor transducer described in section 2.
JP15181181A 1981-09-24 1981-09-24 Power-factor transducer Pending JPS5852575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15181181A JPS5852575A (en) 1981-09-24 1981-09-24 Power-factor transducer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15181181A JPS5852575A (en) 1981-09-24 1981-09-24 Power-factor transducer

Publications (1)

Publication Number Publication Date
JPS5852575A true JPS5852575A (en) 1983-03-28

Family

ID=15526819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15181181A Pending JPS5852575A (en) 1981-09-24 1981-09-24 Power-factor transducer

Country Status (1)

Country Link
JP (1) JPS5852575A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5348576A (en) * 1976-09-30 1978-05-02 Siemens Ag Analogue arithmetic unit for powerrfactor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5348576A (en) * 1976-09-30 1978-05-02 Siemens Ag Analogue arithmetic unit for powerrfactor

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