JPS5850764A - Semiconductor device for power supply - Google Patents
Semiconductor device for power supplyInfo
- Publication number
- JPS5850764A JPS5850764A JP56148218A JP14821881A JPS5850764A JP S5850764 A JPS5850764 A JP S5850764A JP 56148218 A JP56148218 A JP 56148218A JP 14821881 A JP14821881 A JP 14821881A JP S5850764 A JPS5850764 A JP S5850764A
- Authority
- JP
- Japan
- Prior art keywords
- varistor
- semiconductor device
- voltage
- ceramic base
- thyristor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thermistors And Varistors (AREA)
- Protection Of Static Devices (AREA)
- Die Bonding (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はセラミックバリスター系材料で構成された容器
中に半導体エレメントを収納して成る電力用半導体装置
に関する０
従来、電力用半導体装置としてダイオード、サイリスタ
、パワートランジスター、ゲートターンオフサイリスタ
（ＧＴＯ）などが実用されている。これらの素子は高電
圧から大電流をスイッチングする機能を有し、かつ、高
信頼度を維持するため第１図にしめすごとく、半導体エ
レメント（１）（シリ；ン基板）はセラミック等の絶縁
物円筒（！）の中に上下から銅電極１３１１４１で圧接
保持され、かつ、不活性ガス中に密封設置されている０
第１図はサイリスタ、トランジスタ、ＧＴＯ等の３端子
形半導体装置の構成例であり、ゲート端子等の制御電極
（Ｉｌが絶縁容器（りを密封貫通し半導体エレメント（
１）の中心に導かれている。なお、電極＋３３１４１
社それぞれ７ノード電極囚とカソード電極（Ｋ）で知ら
れている０さて、電力用半導体装置は有限の耐電圧値を
有しておシ、現状最大の耐電圧はサイリスタで６ＫＶま
で、ＧＴＯでは亀５００Ｖ、 ）ランジスタでは４００
〜５ｏｏｖ程度である。これ以上の電圧が半導体装置に
印加されると、半導体ニレメン） （’１１は絶縁破壊
して本来の機能を消失し単なる金属導体と化し価値はな
くなる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power semiconductor device comprising a semiconductor element housed in a container made of a ceramic varistor material. Turn-off thyristors (GTOs) and the like are in practical use. These elements have the function of switching large currents from high voltages, and in order to maintain high reliability, the semiconductor element (1) (silicon substrate) is made of an insulating material such as ceramic, as shown in Figure 1. A cylinder (!) is held under pressure by copper electrodes 131141 from above and below, and is sealed in an inert gas atmosphere.
Figure 1 shows an example of the configuration of a three-terminal semiconductor device such as a thyristor, transistor, or GTO, in which a control electrode (Il, such as a gate terminal) sealingly passes through an insulating container (
1) is guided by the center. In addition, electrode +33141
0 Now, power semiconductor devices have a finite withstand voltage value, and the current maximum withstand voltage is up to 6KV for thyristors, and for GTOs. Tortoise 500V, ) 400V for transistor
It is about ~5oov. If a voltage higher than this is applied to a semiconductor device, the semiconductor device ('11) will undergo dielectric breakdown and lose its original function, becoming a mere metal conductor and having no value.
それゆえ、半導体装置を過電圧から保護することは実用
上非常に重要な技術であシ、種々の方式が存在するが、
代表的な回路構成は第８図に示すものである。半導体装
置（６）のアノード端子（３）とカソード端子（４）に
は抵抗（７）とコンデンサ（８）の直列回路から成るサ
ージ抑制回路が並列接続されるのが普通である。最近で
は、セラミック系バリスターに電圧−電流の非線形特性
のすぐれた材料が・現われ、バリスター（３）が半導体
装置（６）と並列に接続され、バリスター（３）が有す
る電圧−電流特性にしたがい半導体装置（６）を効果的
に保護する。特にセラミック系バリスターには酸化亜鉛
形バリスターが適している。。Therefore, protecting semiconductor devices from overvoltage is a very important technology in practice, and there are various methods.
A typical circuit configuration is shown in FIG. A surge suppression circuit consisting of a series circuit of a resistor (7) and a capacitor (8) is usually connected in parallel to the anode terminal (3) and cathode terminal (4) of the semiconductor device (6). Recently, materials with excellent nonlinear voltage-current characteristics have appeared in ceramic varistors, and the varistor (3) is connected in parallel with the semiconductor device (6), and the voltage-current characteristics that the varistor (3) has Accordingly, the semiconductor device (6) is effectively protected. Zinc oxide type varistors are particularly suitable for ceramic varistors. .
セラミック系バリスター（９）の電圧電流特性の代表例
を第３図に示゛【７ている。すなわち、横軸は電流で縦
軸゛は電圧である。この特性では電流１１に）のときの
制限電圧ｔｊ： ｖＩＣｖ）であり、電□流夏２（Ａ）
の時の制限電圧はＶ２ （Ｖ）と電流が大巾に増加【７
ても電圧の変化はわずかである。数値的な一例を示すと
、１１＝１ｍＡで、ｖｔ ＝ ３ＫＶ、 １２ ＝１０
，０ＯＯＡで、Ｖ２＝４ＫＶ等である。A typical example of the voltage-current characteristics of the ceramic varistor (9) is shown in FIG. That is, the horizontal axis is current and the vertical axis is voltage. In this characteristic, the limiting voltage tj: vICv) when the current is 11), and the current □ current summer 2 (A)
The limiting voltage at the time is V2 (V) and the current increases significantly [7
However, the change in voltage is slight. To give a numerical example, 11 = 1mA, vt = 3KV, 12 = 10
, 0OOA, V2=4KV, etc.
本発明は上記に鑑みてなさ′れたもので、セラミック系
バリスターで容器を構成することによって、サージ抑制
回路を内蔵した電力用半導体装置を提供する。The present invention has been made in view of the above, and provides a power semiconductor device having a built-in surge suppression circuit by constructing a container using a ceramic varistor.
第４図は本発明にもとすぐ電力用半導体装置の構成例を
示すものである。す表わち、セラミック系絶縁物の円筒
状容器（＋０１を第３図に示すよりなマー１特性を有す
るセラミック系バリスター材料で構成し、容器回内に半
導体エレメント（１）を銅電極Ｔｅｌ １４１で圧接保
持する。ゲート電極（５）は従来のものと同様に、容器
（１０！を密封貫通し、半導体エレメントに導かれる。FIG. 4 shows an example of the configuration of a power semiconductor device according to the present invention. That is, a cylindrical container made of a ceramic insulator (+01 is made of a ceramic varistor material having a mer-1 characteristic as shown in FIG. 3, and a semiconductor element (1) is connected to a copper electrode Tel The gate electrode (5) is held under pressure at 141. The gate electrode (5) passes through the container (10!) in a sealed manner and is led to the semiconductor element, as in the conventional case.
本発明にもとづく電力用半導体装置の電気的等価回路は
、従来のものが第２図の破線内に示す構成であったのに
対し、第５図に示すようにセラミック系バリスター（１
０）による過電圧保護機能付の電気回路構成となってい
る。The electrical equivalent circuit of the power semiconductor device according to the present invention has a ceramic varistor (1
0) has an electric circuit configuration with an overvoltage protection function.
通常、電力用半導体装置の代表例であるサイリスタの場
合、第６図に示す電圧（ｖ）−電流（１）特性、すなわ
ち、正電圧に対して０−Ａ−Ｂ−Ｃ特性を有し、逆電圧
に対してＦｉｏ−Ｄ特性をもっている。Usually, in the case of a thyristor, which is a typical example of a power semiconductor device, it has a voltage (v)-current (1) characteristic shown in FIG. 6, that is, a 0-A-B-C characteristic for positive voltage, It has FIO-D characteristics against reverse voltage.
しかるに１セラオツク系バリスターのｖ−１０性０−Ｘ
、Ｏ−Ｙが加わるため常にセラミック系バリスターの電
圧−電流特性がサイリスターの電圧以下とな９、サイリ
スタは確実に正、逆方向電圧とも過電圧から保護される
ことになる。−さらに、電力用半導体装置は正常な機１
４＠ 全果すために適当な温厩以下に保つ必要があシ、
このため通常何らかの冷却が実施される。したがって、
従来の構成では冷却されるものは電力用半導体装置のみ
であったが、本発明の場合、セラミック系バリスター（
１ｏ）も同時に冷却されるためより過電圧保護特性の優
れたバリスターを実現できる。However, the v-10 characteristics of the 1-cell barista 0-X
, O-Y are added, so the voltage-current characteristic of the ceramic varistor is always below the voltage of the thyristor9, and the thyristor is reliably protected from overvoltage in both forward and reverse directions. -Furthermore, power semiconductor devices are normal devices.
4＠ It is necessary to keep the temperature below an appropriate temperature for full fruiting,
For this reason, some cooling is usually performed. therefore,
In the conventional configuration, only the power semiconductor device was cooled, but in the case of the present invention, a ceramic varistor (
Since 1o) is also cooled at the same time, a varistor with better overvoltage protection characteristics can be realized.
さらに、従来電力用半導体装置とバリスターが別々に設
置されていたので、空間的によシ大きいスペースを必要
としたが、本発明では両者が一体化されたため、小形、
軽量化が図れる。Furthermore, in the past, the power semiconductor device and the varistor were installed separately, which required a large amount of space, but in the present invention, the two are integrated, making it compact and compact.
Lighter weight can be achieved.
第１図は従来の電力用半導体装置の断面図、第２区は第
１図を使用した電力用半導体装着の使用回路を示す構成
図、第３図はセラミック系バリスターの電圧−電流特性
を示す説明図、第４図は本発明の一実施例を示す断面図
、第５図は巣４図の等価回路を示す構成図、第６図は第
４図の電圧−電流特性を示す説明図である、
図において、＋１１１１を半導体ニレメン）、＋３１＋
４１は電極、＋Ｓｏｌは化ラミック系バリスターである
。
なお各図中同一符号は同−又は相轟部分を示す。
代理人 葛野信−Figure 1 is a cross-sectional view of a conventional power semiconductor device, Section 2 is a configuration diagram showing the circuit used for mounting a power semiconductor using Figure 1, and Figure 3 shows the voltage-current characteristics of a ceramic varistor. 4 is a sectional view showing an embodiment of the present invention, FIG. 5 is a configuration diagram showing an equivalent circuit of Figure 4, and FIG. 6 is an explanatory diagram showing the voltage-current characteristics of FIG. 4. In the figure, +1111 is a semiconductor element), +31+
41 is an electrode, and +Sol is a lamic varistor. Note that the same reference numerals in each figure indicate the same or similar parts. Agent Makoto Kuzuno
Claims (2)
、上記各電極に固着されたセラミック系バリスターで上
記半導体エレメントを密封したことを特徴とする電力用
半導体装置。(1) A power semiconductor device characterized in that a pair of electrodes are arranged at both ends of a semiconductor element, and the semiconductor element is sealed with a ceramic varistor fixed to each electrode.
特許請求の範囲第１項記載の電力用半導体装置。(2) The power semiconductor device according to claim 1, wherein the varistor is of a zinc oxide type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56148218A JPS5850764A (en) | 1981-09-19 | 1981-09-19 | Semiconductor device for power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56148218A JPS5850764A (en) | 1981-09-19 | 1981-09-19 | Semiconductor device for power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5850764A true JPS5850764A (en) | 1983-03-25 |
| JPS6224949B2 JPS6224949B2 (en) | 1987-05-30 |
Family
ID=15447912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56148218A Granted JPS5850764A (en) | 1981-09-19 | 1981-09-19 | Semiconductor device for power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850764A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02189960A (en) * | 1989-01-18 | 1990-07-25 | Nippon Soken Inc | Mounting structure of integrated circuit device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0593560U (en) * | 1992-05-13 | 1993-12-21 | 富士ロビン株式会社 | Sorting machine for empty cans |
| JPH0593561U (en) * | 1992-05-13 | 1993-12-21 | 富士ロビン株式会社 | Empty can sorter |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4861762U (en) * | 1971-11-15 | 1973-08-06 | ||
| JPS56131951A (en) * | 1980-03-19 | 1981-10-15 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1981
- 1981-09-19 JP JP56148218A patent/JPS5850764A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4861762U (en) * | 1971-11-15 | 1973-08-06 | ||
| JPS56131951A (en) * | 1980-03-19 | 1981-10-15 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02189960A (en) * | 1989-01-18 | 1990-07-25 | Nippon Soken Inc | Mounting structure of integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6224949B2 (en) | 1987-05-30 |
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