JPS584974A - Insulating gate-enhancement type metal insulator semiconduction field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain the small-sized E type IG-FET having high gains by forming a gate electrode by two poly Si layers, introducing an impurity and giving enhancement (E) type characteristics to one layer and depletion (D) type ones to the other layer. CONSTITUTION:The E type FET is formed onto an insulating substrate 1 according to a predetermined method, the impurities are introduced to the gate electrode 6 of poly Si, and 6E for the E type and 6D for the D type are shaped. When the materials, concentration, etc. of the impurities of the sections 6E, 6D are properly selcted at that time, gm is remarkably higher than conventional E type FETs when VG is close to thershold value Vth while displaying the E type characteristics and gm can be incerased in the same manner as conventional D type FETs even when gm is larger than Vth when viewed from the characteristics of the gate electrode VG-mutual conductance, and high gains are obtained. Accordingly, a channel length modulation effect is not generated unnecessarily even when the length of a channel 4 is decreased, and the transistor can be miniaturized more than conventional devices.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in insulated gate enforcement MI8 field effect transistors.

Insulated gate enforcement type MI8 field effect transistor (hereinafter simply referred to as enforcement type for simplicity) IIF
In principle, a semiconductor region 2 for a source is formed on an insulating or semi-insulating substrate 1 as shown in FIGS. 1 to 4.
and a drain semiconductor 11 [, a channel forming region 4 between inner regions 2 and 3, and a gate electrode 6 disposed on the region 4 with a gate insulating layer 5 interposed therebetween. In such a structure, the source semiconductor region 2, the drain semiconductor region 5, and the channel forming region 4 have the same conductivity IN (1°) as shown in FIGS.
In the case of the figure, N111, #! In the case of Figure 2, it has PIII),
And if the latter has a lower impurity concentration than the former,
Enhancement #1 IFITtJS is called a buried channel type (N type buried channel type in the case of Fig. 1, P type buried channel type in the case of w42 figure), and the semiconductor region 2 for the source and the semiconductor region for the drain. When the conductivity S and the channel forming region 4 are different from each other as shown in FIGS. 5 and 4, the source semiconductor region 2 and the drain semiconductor region S are NWII, and the channel forming region 4 is P In the case of the #14 diagram, the source semiconductor region 2 and drain semiconductor region 3 have PJI, and the channel formation region 4 has NM), and the latter has a lower impurity concentration than the former, it is an enhancement type FET. is said to be a surface channel type (the N-type surface channel type in the case of FIG. 3, and the P-type all channel type in the case of FIG. 4).

The enhancement having the above-described configuration in FIGS. 1 to TS4 [FBT has a gate voltage V applied between the source semiconductor region 2 and the drain conductor region ''3.

The gate voltage V in terms of the relationship with the drain current lD flowing through the source semiconductor region 2 and drain semiconductor region 3. When is large, the gate voltage ■. When becomes the expected threshold voltage ■th, the drain current ID
begins to flow, and the gate voltage V. When becomes larger than the negative value voltage vth, the drain voltage RID increases accordingly, but the gate voltage V. When is zero, the drain current lD is zero, which is an enhancement type characteristic, so the apparent #! 1-~1-~ have the same basic configuration as the above-mentioned basic configuration, but the gate voltage V. In terms of the relationship between the drain current ID and the gate voltage V.

When , the gate voltage V. is the planned threshold voltage Vt
The drain current ID begins to flow when the voltage V becomes h, and when the gate voltage V becomes larger than the threshold voltage th, the drain current ID increases accordingly, but the gate voltage V
. When is zero, the drain current! Compared to the insulated gate delusion type MI8 field effect transistor (hereinafter simply referred to as depletion type FIT for simplicity), which exhibits depletion type characteristics in which the current is not zero, it has the characteristic that it is easy to use as a switching element. It is widely used as an element.

However, the enhancement having the principle configuration described above in FIGS. 111 to 4! ! ! The FET has its trn-I
Generally, the mutual conductance expressed by D/Vo is the mutual conductance of a depletion type FB'l' which apparently has the same basic configuration as that described above in FIGS. V. Looking at the characteristics of a mutual conductance of 1 m for 1 m, it is obtained as shown by the line ID in Fig. s. Similarly, when the gate voltage V
. Looking at the characteristics of the mutual conductance with respect to the gate voltage ■, as shown by the line IE in FIG.

is a voltage V that is equal to the threshold voltage vth of the enhancement 1 FBT. , of course, if the gate voltage v0 is V. Even when the value is 1 or more, the mutual conductance value is smaller than that of depletion type PET, and therefore a high gain cannot be obtained in general.

In addition, the enhancement fiFBT having the above-mentioned principle structure in FIGS. If you try to miniaturize the whole, an undesirable channel length modulation effect will occur, and therefore a constant @
It had the disadvantage of having a high degree of

Accordingly, the present invention proposes a novel enhanced membrane (11FIT) free from the above-mentioned drawbacks, which will become clear from the detailed description below.

The present invention is based on an enhancer (FllFIT) having the configuration described above in Figure 1wJ-4.

The reason why it exhibits the enhancement wave characteristics described above is that the gate electrode 6 is composed of one of the semiconductor layers such as polycrystalline silicon, and the one semiconductor layer is given the enhancement wave property. impurities for imparting 1141 properties (for example, pH impurities such as boron in the case of the NIl takikomi channel device shown in Figure 1; @N impurities such as phosphorus in the case of the P-type implanted channel device shown in Figure 2) In the case of the surface channel of NIl with a diameter of 3 m, for example, phosphorus impurities are introduced, and in the case of the surface channel of PIl of Fig. 1114, pH impurities such as boron) are introduced. In the depletion carbon fiFIT, which has the same principle structure as the one described above, but exhibits a depreciation characteristic of 11%, the reason why it exhibits the depreciation M7Mk characteristic described above is that it has a gate in the gate. The electrode 6 is made of, for example, one of the semiconductors, and an impurity for imparting depletion shoulder 1141 imparting the depletion characteristic to the one semiconductor layer (apparently a buried channel type of N@ in FIG. 1) is added. In the case of , N@ impurity,
In the case of implanted channel deafness with an apparent pH of 211, P@
Impurities, %Pfi in case of surface channel type with apparently N vessels
In the case of an impurity, an apparent PII surface channel image, N[
This is because the gate electrode 6 is made of a semiconductor such as polycrystalline silicon. , and one of the two semiconductor layers is doped with an impurity for imparting enhancement characteristics to form an electrode portion for a semiconductor gate for imparting enhancement characteristics (this is referred to as 6B). ), and the other part is made into a semiconductor dirt electrode part (6D) by introducing an impurity for imparting depletion characteristic ffi% to this, and the gate electrode 6 becomes part 6PS. Fig. 6 shows the mutual conductance gm with respect to the gate voltage V0 when the portions 6B and 6D of the gate electrode 6 consist only of the semiconductor gate electrode for imparting ffl characteristics. If the enhancement 11411 shown by the dotted line IB is obtained in II (conventional enhancement) WI
(In the case of FET, it is mutually exclusive) -P'l II ノ Vo
Against gn'l "1" Mite, 11m' 6 II K
Enhancement characteristics shown by the dotted line II' are obtained.

When the gate electrode 6 is made up of only the portions 6D, the impurities in the portions 6E and 6D are determined to obtain the depletion property shown by the dotted line ID in FIG. If you choose the material and concentration force appropriately, similar v
(As shown in Figure 6 by I'HI in terms of i vs. ) The gate voltage V is significantly higher than that of 11FI.

When is larger than the vicinity of the threshold voltage vth, it can be obtained as high as the conventional depletion HFIT, and therefore a higher gain can be obtained compared to the conventional enhancement type FIT. Depending on the length, even if the channel length is made small, unnecessary channel length modulation effects will not occur.
This led us to recall that it is possible to reduce the amount compared to M〒.

Therefore, I have come to propose 41 birds here, and the m1it examples are [Figure 7, Figure 8, Figure 9 and 111]
As shown in FIG. 10, FIGS. 1 and 2.

The gate electrode 6 has the above-mentioned structure as shown in FIGS. It has a configuration that it is equipped with.

In fact, the gauge electrode parts 6D and 4M mentioned above are arranged, for example, in a manner such that they are connected to each other so that the same potential is applied to them.

The above is the enhancement according to the present invention) It F IT
The am-like structure of
Since it is clear from the above, a detailed explanation will be omitted, but since a high gain can be obtained, a higher gain can be obtained compared to the conventional Enhancement 1-@PET, and the overall gain can be reduced by reducing the channel length. It has the great feature that it can be made into a small part.

In the above description, the case where there is only one gate electrode section 6E and 6D has been described, but it is clear that the same effect can be obtained if there is a plurality of gate electrode sections 6E and 6D. .

[Brief explanation of the drawing]

Figures 1 to 4 are schematic cross-sectional views showing the basic structure of a conventional enhancement-type FIT, and Figure 5 and Figure 116 show the relationship between the mutual conductance g and the gate voltage v0 applied to the m-channel of the present invention. Figure shown, No. 7 m11-111
1t1 diagram is in book l! 1 is a cross-sectional view illustrating the basic structure of an enhancement type FIT according to Akira.・(゛)V Figure 7 Figure 8 Figure 9 Figure 10 Display of the case 1982 Patent Application No. 102522/
Title of invention Insulated gate enhancement type MIS
Relationship with field-effect transistor patent applicant case Patent applicant address 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo 100 Name (422) Representative of Nippon Telegraph and Telephone Public Corporation Osamu Tsuneyo Makoto Address 102 Tokyo 5-7 Kojimachi, Chiyoda-ku, Miyako Hidekazu Kioicho TBR 820 Phone: 03-230-4644 Subject of amendment Full text of the specification Contents of amendment As attached Specification (corrected full text) 1. Title of the invention Insulated gate enhancement type M
IS Field Effect Transistor 2, Claims A gate electrode includes an electrode portion for a semiconductor gate for enhancement-type characteristics into which an impurity for imparting enhancement-type characteristics is introduced, and a depletion type semiconductor gate electrode portion into which an impurity for imparting depression-type characteristics is introduced. An insulated gate enhancement type MIS field effect transistor comprising: a semiconductor gate electrode portion for imparting type characteristics; 3. DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in insulated gate enhancement type MIS field effect transistors. Insulated gate enhancement type M, IS field effect transistor (hereinafter simply referred to as enhancement type FE for simplicity)
(referred to as T)- has the following structure in principle. That is, as shown in FIGS. 1 to 4, on an insulating or insulating substrate 1, a semiconductor region 2 for a source, a semiconductor region 3 for a drain, and a semiconductor region 2 for a source and a semiconductor region for a drain are formed. 3, and a gate electrode 6 disposed on the region 4 with a gate insulating layer 5 interposed therebetween. In an enhancement type FET having such a configuration, a source semiconductor region 2 and a drain semiconductor region 3
and the channel forming region 4, as shown in FIGS. 1 and 2, have the same conductivity type (N type in the case of FIG. 1, P type in the case of FIG. 2), When the channel forming region 4 has a lower impurity concentration than the source semiconductor region 2 and the drain semiconductor region 3, the enhancement type FET is a buried channel type (in the case of FIG. 1, an N type buried It is called a buried channel type (in the case of FIG. 2, a P-type buried channel type). Further, as shown in FIGS. 3 and 4, the source semiconductor region 2, the drain semiconductor region 3, and the channel formation region 4 are of different conductivity types (in the case of FIG. The region 2 and the drain semiconductor region 3 are N type,
In the case where the channel forming region 4 is of P type, as shown in FIG. 4, the source semiconductor region 2 and the drain semiconductor region 3 are of P type, and the channel forming region 4 is of N type. has a lower impurity concentration than the source semiconductor region 2 and the drain semiconductor region 3, the enhancement type FET is a surface channel type (in the case of FIG. 3, an N-type surface channel type, and in the case of FIG. case,
It is said to be a P-type surface channel type). The enhancement type FET having the configuration described above in FIGS. 1 to 4 has a structure in which the gate voltage V applied between the source semiconductor region 2 and the drain semiconductor region 3 is 3. In relation to the drain current l flowing through the gate voltage v
When increasing 4, the gate voltage vG becomes the expected threshold voltage v
From the time it reaches 4h, the drain current If) starts to flow,
If the gate voltage V becomes larger than the threshold voltage V4h, the drain current ■ increases accordingly, but if the gate voltage V becomes zero, the drain current ■ becomes larger. It exhibits an enhancement type characteristic in which the value is zero. The enhancement type FET described above in FIGS. 1 to 4 has the same basic structure as that described above in FIGS. 1 to 4, but the drain current with respect to the gate voltage VG Considering the relationship, when the gate voltage vGt is increased, the drain current 1. began to flow,
If the Goot voltage v6 becomes larger than the threshold voltage W, the drain current 1. However, when the gate voltage va is zero, the drain current I. It has the characteristic that it is easier to use as a switching element than an insulated gate depression type MIs field effect transistor (hereinafter simply referred to as a depletion type FET for simplicity), which exhibits a depression type characteristic in which the FET is not zero. For this reason, the enhancement type FET described above in FIGS. 1 to 4 is widely used as a switching element. However, the enhancement type FET having the above-mentioned principle configuration in FIGS. 1 to 4 has the following characteristics. 1ll=1
．． , /V(,) In general, the mutual conductance throw of a depletion type FET which apparently has the same principle configuration as that described above in FIGS. 1 to 4 is given by the gate voltage VG. Looking at the characteristics of the transconductance gs with respect to the gate voltage Ve, as shown by the line ID in FIG. Not only when the voltage V6 is a voltage VGI which is equal to the threshold voltage vxi of the enhancement type FET, but also when the gate voltage V is equal to or higher than V61, the mutual conductance 9- of the depletion type FET For this reason, the enhancement type FETs described above in FIGS. 1 to 4 generally have the disadvantage of not being able to obtain high gains. The enhancement type FET having the principle configuration described above in the figure has a mutual conductance of 0.
As mentioned above, since the characteristics are generally small, the length of the channel forming region 4, and therefore the channel length, is made small,
Attempts to downsize the entire enhancement FET result in undesirable channel length modulation effects. For this reason, the enhancement type FET described above in FIGS. 1 to 4 has a certain limit in miniaturizing it.
It had the following drawback. Therefore, the present invention aims to propose a novel enhancement type FET that does not have the above-mentioned drawbacks, which will become clear from the detailed description below. The present inventors have discovered that the enhancement type FET having the configuration described above in FIGS. 1 to 4 exhibits the enhancement type characteristics described above because the gate electrode 6
is composed of one semiconductor layer, such as polycrystalline silicon, and an impurity for imparting enhancement type characteristics (an N-type impurity in FIG. 1) imparts enhancement type characteristics to that one semiconductor layer. For embedded channel type,
In the case of the P type buried channel type shown in Figure 2, an N type impurity such as phosphorus, in the case of the N type surface channel type shown in Figure 3, e.g. It was recalled that this is because an N-type impurity (for example, a P-type impurity such as boron in the case of the P-type surface channel type shown in FIG. 4) is introduced. In addition, the present inventors have developed a depression type FET which apparently has the same principle structure as that described above in FIGS. 1 to 4, but which exhibits depressin type characteristics. Similarly, the reason why the gate electrode 6 exhibits the depletion type characteristics is that the gate electrode 6 is composed of, for example, one of the semiconductor layers, and that one semiconductor layer is provided with a depletion type characteristic imparting impurity (depression type characteristic) that imparts the depletion type characteristic. In the case of the N-type buried channel type shown in Figure 1, there is apparently an N-type impurity, and in the case of the P-type buried channel type shown in Figure 2, there is a P-type impurity, an apparent, and an N-type impurity. It was also recalled that this is because a P-type impurity is introduced in the case of the surface channel type, and an N-type impurity is introduced in the case of the surface channel type, which is apparently P type. Furthermore, based on the above-mentioned recollection, the present inventors apparently
It has the same principle structure as described above in FIGS. 1 to 4, but the gate electrode 6 is made of, for example, polycrystalline silicon.
An electrode part for a semiconductor gate for imparting enhancement type characteristics is formed by introducing an impurity for imparting enhancement type characteristics into one of the two semiconductor layers (this is referred to as 6E). ), and the other is made into a semiconductor gate electrode part (6) by introducing an impurity for imparting depression type characteristics into this.
D), and in this case, if the gate electrode 6 is made up of only the part 6E, then the parts 6F and 6D of the gate electrode 6 are both made up of only the semiconductor gate electrode for imparting enhancement-type characteristics. When looking at the mutual conductance Ql with respect to the gate voltage VG, the dotted line 1. Enhancement type 2, denoted by E. When the characteristics can be obtained <conventional enhancement type FET
Corresponding to the case of 1), when looking at the same V and O-, the enhancement type characteristics shown by the dotted line IE in FIG. , looking at the same V& vs. Ql, if the material, concentration, etc. of the impurity in parts 6F and 6D are appropriately selected so that the depletion type characteristic shown by the dotted line ID in Fig. 6 can be obtained, the same V & vs. g■ can be obtained. Look at the solid line T E in Figure 6.
”, while exhibiting enhancement type characteristics, the mutual fundance Q- can be obtained as being significantly higher than that of the conventional enhancement type FET when the gate voltage V6 is near the threshold voltage Vth. , and when the gate voltage V6. is larger than the vicinity of the threshold voltage vth, it can be obtained as high as a conventional depletion type FET, and therefore a higher gain can be obtained compared to a conventional enhancement type FET. Moreover, for this reason, even if the channel length is made small depending on the length of the channel forming region 4, an unnecessary channel length modulation effect does not occur. Therefore, the present inventors proposed the present invention as described in the claims, and the principle embodiment thereof is the seventh embodiment. As shown in Figures 8, 9 and 10,
In the structure described above in FIG. 1, FIG. 2, FIG. 3, and FIG. It has a configuration including a gate electrode section 6D. In fact, the gate electrode parts 6D and 6F described above are connected to each other by, for example, wiring so that the same potential is applied to them. The basic structure of the enhancement type FET according to the present invention has been clarified above. According to the enhancement type FET of the present invention having such a configuration, as is clear from the above, a detailed explanation will be omitted, but since a high g- can be obtained, compared to the conventional enhancement type FET, It has the great feature that an old gain can be obtained, and the entire enhancement type FET can be downsized by making the channel length small. In addition, in the above description, the case where there is only one gate electrode section 6F and 6D has been described, but it is also possible to obtain the same effect as described above by using a plurality of gate electrode sections 6F and 6D. It should be obvious. 4. Brief Description of the Drawings FIGS. 1, 2, 3, and 4 are sectional views showing the basic structure of a conventional enhancement type FET, respectively. FIGS. 5 and 6 are diagrams showing the relationship between mutual conductance Q- and gate voltage VcT for explaining the present invention. FIG. 7, FIG. 8, FIG. 9, and FIG. 10 are line sectional views showing the basic structure of an enhancement type FET according to the present invention, respectively. 1...Insulating or semi-insulating substrate 2
......Semiconductor region 3 for source...
......Drain semiconductor region 4...
......Channel formation area 5...
・・・・・・Gate insulating layer 6・・・・・・・・・・・・
Gate electrode 6F: Electrode section for semiconductor gate for imparting enhancement type characteristics. 6D・・・・・・・Electrode part for semiconductor gate for imparting depression type characteristics

Claims (1)

[Claims] A conductor gate electrode part for imparting enhancement type characteristics into which an impurity for imparting enhancement type characteristics can be introduced, and a semiconductor gate for imparting enhancement SI% characteristics into which an impurity for imparting depletion type characteristics can be introduced. An insulated gate enhancement type MI8 field effect transistor characterized by comprising an electrode portion for use in the field.