JPS5848822A - Photometric circuit provided with latch unlocking circuit - Google Patents
Photometric circuit provided with latch unlocking circuitInfo
- Publication number
- JPS5848822A JPS5848822A JP14608081A JP14608081A JPS5848822A JP S5848822 A JPS5848822 A JP S5848822A JP 14608081 A JP14608081 A JP 14608081A JP 14608081 A JP14608081 A JP 14608081A JP S5848822 A JPS5848822 A JP S5848822A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- diode
- photodiode
- operational amplifier
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B7/00—Control of exposure by setting shutters, diaphragms or filters, separately or conjointly
- G03B7/08—Control effected solely on the basis of the response, to the intensity of the light received by the camera, of a built-in light-sensitive device
- G03B7/081—Analogue circuits
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
- Exposure Control For Cameras (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、カメラ等のラッチ解除回路を有する測光回路
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a photometric circuit having a latch release circuit for a camera or the like.
従来の測)し回路では第1図の如く受光用フォトダイオ
ードを高入力インピーダンス演貢:増幅器全使用してフ
ォトダイオードの両端をイマージナリショートの状態で
フォトダイオードに発生する元邂流を対数変換ダイオー
ドに流して対数圧縮された電圧に変換して使用している
。この方式は通常の使用状態に於てはフォトダイオード
の両端に発生する光強度に応じて対数変換された開放電
圧を使用する方法に比し、光強度の変化に対しその出力
電圧の応答性が良い為に良く使用される。しかし回路の
電源投入時に発生するノイズ、演算増幅器の電源電圧の
立上りに対する安定時間等の問題の為、フォトダイオー
ドと対数変換ダイオードとの接続点の非常に高入力イン
ピーダンスになっている箇所に逆電荷の蓄積が発生して
ラッチを起し2それが長時間抜けない為に正常な測光電
圧金得るのに長時間必要としていた。In the conventional measurement circuit, as shown in Figure 1, the light-receiving photodiode is used as a high-input impedance amplifier: All amplifiers are used, and both ends of the photodiode are imaginary shorted, and the current generated in the photodiode is converted logarithmically. It is used by converting it into a logarithmically compressed voltage by passing it through a diode. Compared to the method that uses an open circuit voltage that is logarithmically converted according to the light intensity generated at both ends of the photodiode under normal usage conditions, this method has a lower responsiveness of the output voltage to changes in light intensity. It is often used because it is good. However, due to problems such as noise generated when the circuit is powered on and stabilization time for the operational amplifier's power supply voltage to rise, a reverse charge is generated at the connection point between the photodiode and the logarithmic conversion diode, which has a very high input impedance. The accumulation of the voltage caused the latch to occur, and because it did not release for a long time, it took a long time to obtain a normal photometric voltage.
このようなラッチ現象を第1図に示した従来の測光回路
で説明する。EBは電源、SWlは電源スィッチでON
すると演算増幅器A11人!、及び露出計回路1に給電
される。演算増幅器A、の入力端子間に接続されたフォ
トダイオードPDは、矢印の方向にフォトダイオード面
の照度に応じた元電流ILが発生する。演算増幅器A、
は高入力インピーダンスの演算増幅器でありi電流■L
は演算増幅器A、の負入力端子と出力端子間に接続され
た対数変換ダイオードD1により対P1.変換された電
圧として演算増幅器A1の出力に低インピーダンスで出
力され露出計回路1に伝達される。演算増幅器A2の正
入力端子と電源の負ラインに接続されている基準バイア
ス電源Eoは演算増幅器A2によりその基準電圧は同相
増幅されて演算増幅器A1出力の基準電位を設定してい
ると共に基準バイアス電源E。Such a latching phenomenon will be explained using the conventional photometric circuit shown in FIG. Turn on EB with the power supply and SWl with the power switch.
Then there were 11 operational amplifiers A! , and the exposure meter circuit 1. In the photodiode PD connected between the input terminals of the operational amplifier A, an original current IL is generated in the direction of the arrow in accordance with the illuminance on the photodiode surface. operational amplifier A,
is an operational amplifier with high input impedance, and the i current ■L
is connected to the pair P1. by the logarithmic conversion diode D1 connected between the negative input terminal and the output terminal of the operational amplifier A. The converted voltage is outputted to the output of the operational amplifier A1 with low impedance and transmitted to the exposure meter circuit 1. The reference bias power supply Eo, which is connected to the positive input terminal of the operational amplifier A2 and the negative line of the power supply, has its reference voltage amplified in phase by the operational amplifier A2 to set the reference potential of the output of the operational amplifier A1, and also serves as a reference bias power supply. E.
の電圧は露出計回路1へ必要な演算処理を行う為に基準
バイアス電圧として伝達されている。演算増幅器A2の
出力側に接続されている抵抗R6、R11’の抵抗値に
よりこの基準バイアス電圧は決定される。演算増幅器A
1の正入力側とフォトダイオードPDのアノード側の接
続点の電位が演算増幅器A2により電源EBの負のライ
ン電圧より正側に高めであるのは、露出計回路1の演算
処理の必要性の為だけでなく、仮述のある程度のラッチ
解除を対数変換用ダイオードD1に並列接続されている
ダイオ−1’ D 、にぶり行う為である。The voltage is transmitted to the exposure meter circuit 1 as a reference bias voltage in order to perform necessary arithmetic processing. This reference bias voltage is determined by the resistance values of resistors R6 and R11' connected to the output side of operational amplifier A2. Operational amplifier A
The reason why the potential at the connection point between the positive input side of the exposure meter circuit 1 and the anode side of the photodiode PD is set higher than the negative line voltage of the power supply EB by the operational amplifier A2 is due to the necessity of calculation processing of the exposure meter circuit 1. This is not only for the purpose of canceling the latch to some extent as mentioned above, but also for diode 1' D connected in parallel to the logarithmic conversion diode D1.
電源スィッチSWI 金ONすると演算増幅器A1は
時間ゼロで正常作動になるわけではなく、必ず有限時間
の過渡的な不安定期間を有する。この不安定期間内、で
はフォトダイオードPDをイマージナルショートにはで
きないので演算増幅器A、の出力は不確定であり、過渡
的に演算増幅器A、比出力本来の正常な出力エリも高く
なってしまう。それにより対数変換用ダイオードDak
介して電流が流れ込み、フォトダイオードPDの接合容
量に電荷が蓄積され、それはフォトダイオードPDのカ
ソード側に正の電荷が蓄積される。このような電荷は又
電源スイッチSW、 のチャタリングノイズにエリ回
路の浮遊容量を介して蓄積される。When the power switch SWI is turned ON, the operational amplifier A1 does not operate normally at time zero, but always has a transient unstable period of finite time. During this unstable period, the photodiode PD cannot be imaginal shorted, so the output of operational amplifier A is uncertain, and the normal output error of operational amplifier A, which is the specific output, becomes high transiently. . Therefore, the logarithmic conversion diode Dak
A current flows through the photodiode PD, and charge is accumulated in the junction capacitance of the photodiode PD, which causes positive charge to be accumulated on the cathode side of the photodiode PD. Such charges are also accumulated in the chattering noise of the power switch SW through the stray capacitance of the ERI circuit.
演算増幅器A、の不安定期間が終了すると演算増幅器A
、はフォトダイオードPDをイマージナルショートで制
御しようとするが、受光面照度が充分大なる時前述の蓄
積電荷は元電流工りによりすぐ中和されるので演算増幅
器A1出力に正常な出力が直ちに得られる。When the unstable period of operational amplifier A ends, operational amplifier A
, tries to control the photodiode PD by imaginal short circuit, but when the light-receiving surface illuminance becomes sufficiently large, the accumulated charge mentioned above is immediately neutralized by the source current, so a normal output is immediately output to the operational amplifier A1 output. can get.
受光面照糺が非常に低下してくると光電流は数10PA
〜数PI程度になりその様な状態では光電流IL自体の
中和で正常な状態に復帰するには長時間を要する。その
場合にダイオードD、はある点まで急速に復帰する事に
役立つ。即ち、フォトダイオードPDのカソード側に正
の電荷が蓄積する事により演算増幅器A1の負入力側は
正入力側よりも正の電位になり、従って演算増幅器A1
の出力は電源の負ライン側に低下してダイオードD、が
順方向に、バイアスされて前述の蓄積IHr荷の放電が
行われる。演算増幅器A2により電源の負ライン側より
正の電位を演算増幅器A1の正入力端に与えているのは
、演算増幅器A1の作動電源が第1図の如く片電源方式
の場合演算増幅器A、出力の最低電位は、電源EBの負
ラインより下る事はなく、演算増幅器A1出力の電位が
負ラインの電圧にほぼ等しくなった時には少くともダイ
オ・−ドD2 k十分に順方向にバイアスして蓄積電荷
の放電を可能とする為である。以上の如くダイオードD
。When the light receiving surface becomes very low, the photocurrent decreases to several tens of PA.
~ several PI, and in such a state, it takes a long time to return to the normal state by neutralizing the photocurrent IL itself. In that case, diode D serves to quickly return to a certain point. That is, as positive charges accumulate on the cathode side of the photodiode PD, the negative input side of the operational amplifier A1 becomes a more positive potential than the positive input side, and therefore the operational amplifier A1
The output of D falls to the negative line side of the power supply, and the diode D is forward biased to discharge the accumulated IHr load mentioned above. The reason for applying a positive potential to the positive input terminal of operational amplifier A1 from the negative line side of the power supply by operational amplifier A2 is that when the operating power supply of operational amplifier A1 is a single power supply system as shown in Fig. 1, operational amplifier A, output The lowest potential of the diode D2 does not fall below the negative line of the power supply EB, and when the potential of the operational amplifier A1 output becomes approximately equal to the voltage of the negative line, at least the diode D2 k is sufficiently forward biased and accumulated. This is to enable electric charge to be discharged. As above, diode D
.
により蓄積電荷の放電が行われるのであるが、ある程度
までダイオードDオによる電荷の中和が行われると演算
増幅器A1の出力はしだいに上昇しダイオードD、Fi
対数特性を有する為に順方電圧が減少すると共に等測的
に非常な高抵抗となる。従ってその様な状態になるとそ
れ以上の中和動作が期待できなくなりその先完全に中和
が行われて正常な状態に復帰する為に長時間を要する事
になる。それは長い場合は数100 m5ec〜数最に
及ぶ。The accumulated charge is discharged, but when the charge is neutralized to a certain extent by the diode D, the output of the operational amplifier A1 gradually rises, and the output of the diodes D and Fi increases.
Since it has logarithmic characteristics, the forward voltage decreases and the resistance is isometrically very high. Therefore, in such a state, no further neutralizing operation can be expected, and it will take a long time for complete neutralization to return to the normal state. If it is long, it ranges from several 100 m5ec to several maximum.
その様な事をさける為にフォトダイオードの両端を演算
増幅器A1の不安定期間だけトランジスタでショートす
る方法等もあるがトランジスタのスイッチング時の急速
な電位変動が浮遊容量を介してノイズとして伝達されて
再ラツチを起してしまう事があり効果がないばかりでな
く有害な事がある。又不安定期間だけLED 等により
元を与えて中和電流を発生させてラッチ解除を行う方法
もあるが、大がかりでありコスト高になり、又消費電力
の増加等の好ましくない状況が発生する。In order to avoid such a situation, there is a method of shorting both ends of the photodiode with a transistor during the unstable period of operational amplifier A1, but rapid potential fluctuations during switching of the transistor are transmitted as noise via stray capacitance. It may cause re-latching, which is not only ineffective but also harmful. There is also a method of releasing the latch by generating a neutralizing current using an LED or the like during the unstable period, but this method is large-scale and costly, and causes undesirable situations such as an increase in power consumption.
本発明の目的は、測光回路における上述のような演算増
幅器の過渡的な不安定状態に起因してフォトダイオード
に生ずる電荷蓄積の問題を簡単な回路でより有効に解決
することにある。SUMMARY OF THE INVENTION An object of the present invention is to more effectively solve the problem of charge accumulation occurring in a photodiode due to the above-mentioned transient unstable state of an operational amplifier in a photometric circuit with a simple circuit.
以下に本発明の実施例を第2〜5図を参照して説明をす
る。Embodiments of the present invention will be described below with reference to FIGS. 2 to 5.
第2図は本発明の第1の実施例ラッチ解除回路を含む測
光装置である。第1図と同一作動の回路素子には同一記
号を付しである。第1図と異なるのはダイオードD3、
抵抗R1、R1の直列回路がフォトダイオードPDに並
列に、そしてコンデンサC1が抵抗R1とR6の接続点
から負ラインへと接続されである事である。その作動は
次の如く行われる。FIG. 2 shows a photometric device including a latch release circuit according to a first embodiment of the present invention. Circuit elements having the same operation as in FIG. 1 are given the same symbols. What is different from Fig. 1 is the diode D3.
A series circuit of resistors R1 and R1 is connected in parallel to the photodiode PD, and a capacitor C1 is connected from the connection point of resistors R1 and R6 to the negative line. Its operation is as follows.
電源スィッチSW1 が開放時、コンデンサC0の電荷
は抵抗R3及び演算増幅器A2の出力と電源Esの負ラ
イン間の抵抗R6とR8′を介して放電されており、電
源スイッチSW1投入時にはコンデンサC2に電荷はな
いようにされている。When the power switch SW1 is open, the charge in the capacitor C0 is discharged through the resistor R3 and the resistors R6 and R8' between the output of the operational amplifier A2 and the negative line of the power supply Es, and when the power switch SW1 is turned on, the charge in the capacitor C2 is discharged. It is assumed that there is no such thing.
電源スィッチSW1 を閉じると演算増幅器A、 、A
、そのものの動作は一般的に数10μ(6)〜数100
μ戴の過渡的な不安定期間後に正常になる。しかし演算
増幅器A、の出力はまだ正常なものではない。それは本
実施例で付加されているコンデンサCIの充電電流とi
−でダイオ′−ドD11、抵抗R8及びダイオードD、
を介してフォトダイオードPDのカソード側の正の電荷
を引抜く方向に電流が流れており演算増幅器A1の入力
側の電圧が変化し従ってその出力電圧が変化しているか
らである。コンデンサC8には抵抗R1f”介しても充
電されているが、コンデンサC1の電圧が抵抗R2、R
1を介して充電が進み上昇するとダイオードDsk介し
て流れる電流がなめらかに減少していき、コンデンサC
Iの上昇する充twwL圧が演算増幅器A2出力亀圧よ
り0.2 V程度低い電圧迄到達するとダイオードD、
の順方向に印加される電圧は順方向バイアスとして不十
分となり等価抵抗は急に非常に高くなる工う変化するが
、それに比して抵抗R,の抵抗値は変化しないからその
抵抗値は急に高くなったダイオードD、の抵抗に比べて
相対的に小さくなるので抵抗R1に(11)
よるコンデンサC3の充電が支配的となる。When power switch SW1 is closed, operational amplifiers A, , A
, its operation is generally several tens of microns (6) to several hundred
After a period of transient instability of μDai, it becomes normal. However, the output of operational amplifier A is still not normal. It is the charging current of the capacitor CI added in this embodiment and i
- diode D11, resistor R8 and diode D,
This is because a current flows in the direction of drawing out the positive charge on the cathode side of the photodiode PD through the photodiode PD, and the voltage on the input side of the operational amplifier A1 changes, and therefore the output voltage changes. The capacitor C8 is also charged through the resistor R1f, but the voltage of the capacitor C1 is connected to the resistors R2 and R
As charging progresses and rises through diode Dsk, the current flowing through diode Dsk decreases smoothly, and capacitor C
When the rising charge twwL voltage of I reaches a voltage approximately 0.2 V lower than the operational amplifier A2 output voltage, the diode D,
The voltage applied in the forward direction of R is insufficient as a forward bias, and the equivalent resistance suddenly becomes very high.However, in comparison, the resistance value of resistor R does not change, so its resistance value suddenly changes. Since the resistance of the diode D is relatively small compared to the resistance of the diode D, which has become high, the charging of the capacitor C3 by the resistance R1 (11) becomes dominant.
そのため、演算増幅器A、の出力と同電位の所で安定す
る。Therefore, it becomes stable at the same potential as the output of operational amplifier A.
コンデンサC,の電圧が演算増幅器A!の出力電圧と同
電位になると、この時には演算増幅器A、は正常に作動
しているので正負入力間はイマージナルショートの状態
であり電位差は演算増幅器A、のオフセット電圧の数m
V以内であり、その領域に於てはダイオードD8の両端
にも同じ電圧がかがるがその時流れる電流は光電流It
に比し実質的にゼロとみなせる程度に充分小さくダイオ
ードD。The voltage of capacitor C, is operational amplifier A! When the potential becomes the same as the output voltage of the operational amplifier A, at this time, the operational amplifier A is operating normally, so there is an immanent short between the positive and negative inputs, and the potential difference is the number m of the offset voltage of the operational amplifier A.
In that region, the same voltage is applied across the diode D8, but the current flowing at that time is the photocurrent It.
The diode D is small enough to be considered as substantially zero compared to the diode D.
が接続されている事による測光の影響は光電流が数PA
程度になっても問題にならない。The influence of photometry due to the connection of the photocurrent is several PA.
Even if it gets to a certain extent, it's not a problem.
コンデンサC1、抵抗R+ 、R@ k適当に選ぶ事に
より最短の回復値が得られる。抵抗R1は過大電流を流
さない為であり、なくても同様の効果を得る。この場合
ダイオードD、はなくても良い。本実施例の回路では、
フォトダイオードPDの電荷を放電するダイオード(1
2)
D、は、コンデンサC1の光mWL圧と演算増幅器A2
の出力である基準電圧との差によりバイアスされており
、演算増幅器A、の出力電位即ちフォトダイオードPD
の放電状態に関係していないからフォトダイオードPD
の不要蓄積電荷を確実に除去することができる。The shortest recovery value can be obtained by appropriately selecting the capacitor C1, resistor R+, and R@k. The resistor R1 is provided to prevent excessive current from flowing, and the same effect can be obtained even without it. In this case, diode D may be omitted. In the circuit of this example,
A diode (1) that discharges the charge of the photodiode PD
2) D is the optical mWL pressure of capacitor C1 and operational amplifier A2
It is biased by the difference from the reference voltage which is the output of operational amplifier A, that is, the output potential of photodiode PD
Since it is not related to the discharge state of the photodiode PD
Unnecessary accumulated charges can be reliably removed.
M3図は第2の実施例を示すが、この第2の実施91は
電子シャッターカメラに適用されムー例である。第2図
と同一の回路要素は同一記号を使用(2ている。電源ス
ィッチsw;IoNするとスイッチSWrに並列接続さ
れている電源タイマー用コンデンサC2をショートする
と共に抵抗R8を介して電源の正ラインに挿入されてい
るトランジスタQ1をONして本実施例の回路に給電す
る。一方、スイッチSW、’ 1OFF l、でも
コンデンサC,の充電電流のたぬ所定時間トランジスタ
Q1はONを持続する。スイッチ8 W+ ’は一般的
にカメラのシャツタ釦に連動しており、カメラがレリー
ズされるストロークより浅い位置でONになる。FIG. M3 shows a second embodiment, and this second embodiment 91 is applied to an electronic shutter camera and is a Mu example. The same circuit elements as in FIG. The transistor Q1 inserted in the switch is turned ON to supply power to the circuit of this embodiment.On the other hand, the transistor Q1 remains ON for a predetermined time when the charging current of the capacitor C is not generated even when the switch SW is 1OFF. 8 W+' is generally linked to the camera's shutter button, and is turned on at a position shallower than the camera release stroke.
トランジスタQ1のONにより演算増幅器A、 、 A
、は数10μ就〜数100μ(6)後に正常作動状態に
なる。電源の正と負ライン間に直列接続された抵抗R,
とツェナーダイオードZD、 との接合点電圧と演算
増幅器A。By turning on transistor Q1, operational amplifiers A, , A
, will be in a normal operating state after several tens of microns to several hundred microns (6). A resistor R connected in series between the positive and negative lines of the power supply,
and Zener diode ZD, and the junction voltage of and operational amplifier A.
間の出力電圧との差に従ってコンデンサC1の電圧は抵
抗R6側が正抵抗R,側が負に充電されるようにされて
いる。この時トランジスタQ、は抵抗R1を介してのコ
ンデンサC8への充電電圧が低くまだOFF である
ようにされている。数m5ec後に抵抗R4k介しての
コンデンサC8の充tm圧がトランジスタQ。The voltage of the capacitor C1 is such that the voltage on the capacitor C1 is charged so that the resistor R6 side is positive and the resistor R side is negative. At this time, the transistor Q is set so that the voltage charged to the capacitor C8 via the resistor R1 is low and is still OFF. After several m5ec, the charging tm pressure of capacitor C8 via resistor R4k becomes transistor Q.
1ONl、てコンデンサC4の抵抗R3側の接続点を電
源負ラインの電位にクランプして落す。従ってその瞬間
にコンデンサC4の抵抗R,、R,の接続点側の電位は
電源の負ライン側電位よりさらに負側に下る。この負電
圧により前述同様抵抗R2を介してダイオードD、は順
バイアスされ、フォトダイオードPDのカソード側の演
算増幅器A、の不安定状態時に蓄積された正の電荷は確
実に全て放電される。その後前述同様コンデンサC1の
電位は滑らかに変化してコンデンサC1の抵抗R1、R
2の接続側が演算増幅器A、比出力同電位の所で停止す
る。従って演算増幅器A。1ONl, the connection point on the resistor R3 side of the capacitor C4 is clamped to the potential of the negative line of the power supply. Therefore, at that moment, the potential on the connection point side of the resistors R, , R, of the capacitor C4 falls further to the negative side than the potential on the negative line side of the power supply. This negative voltage causes the diode D to be forward-biased via the resistor R2 as described above, ensuring that all the positive charges accumulated in the operational amplifier A on the cathode side of the photodiode PD during the unstable state are discharged. Thereafter, the potential of capacitor C1 changes smoothly as described above, and the resistors R1 and R of capacitor C1
The connection side of No. 2 is operational amplifier A, and stops when the specific output is at the same potential. Therefore, operational amplifier A.
の出力は光電流ILに従った電圧にすぐなる。The output immediately becomes a voltage according to the photocurrent IL.
スイッチ8W2 はレリーズでありカメラのシャツタ
釦の最終ストロークでONになる。シャツタ釦が急速に
押されてスイッチ8 W l’、S W!がほぼ同時に
ONになってもコンデンサC5の為にトランジスタQ、
はトランジスタQ。Switch 8W2 is the release and is turned on with the final stroke of the camera's shutter button. The shirt button is pressed rapidly and switch 8 W l', SW! Even if they turn on almost simultaneously, transistors Q and
is transistor Q.
がONL、て電源電圧が回路に印加された直後はOFF
であり、抵抗R6及びコンデンサCIによる所定時
間後に即ち演算増幅器A1のラッチが解除された後にト
ランジスタQ、はONになり、スイッチ8W、のONは
露出制御回路2に伝達されてレリーズM g +に通電
されて公知のカメラの機械動作′fニーaむ露出制御の
シーケンスが起動されシャッタ制御のM g tが(1
5)
作動してシャッタの制御ヲ行う。トランジスタQ2はカ
メラがレリーズされてからシャッタが閉じて露光動作が
終了するまでの間ON状態に制御回路2により制御され
、露光中にスイッチsw、’がOFFしてもトランジス
タ。1がOFF l、てシャッタが閉じてし筐ゎない
様になっている。is ONL, and is OFF immediately after the power supply voltage is applied to the circuit.
After a predetermined time by the resistor R6 and the capacitor CI, that is, after the operational amplifier A1 is unlatched, the transistor Q is turned on, and the ON state of the switch 8W is transmitted to the exposure control circuit 2 and the release M g + is turned on. When the current is applied, a known camera mechanical operation 'f knee exposure control sequence is started, and the shutter control M g t becomes (1
5) Operate to control the shutter. The transistor Q2 is controlled by the control circuit 2 to be in an ON state from the time the camera is released until the shutter closes and the exposure operation ends, and remains a transistor even if the switches sw and ' are turned off during exposure. When 1 is OFF, the shutter closes and the housing does not open.
第3図の実施例で、この実施例が第2図と異なるのは1
g2図の場合通電初期時にダイオードD3を順バイアス
するのは演算増幅器A。In the embodiment shown in Fig. 3, the difference between this embodiment and Fig. 2 is 1.
In the case of figure g2, it is operational amplifier A that forward biases diode D3 at the initial stage of energization.
の出力電圧によって得ているので演算増幅器A2出力電
圧はダイオードD3の順電圧より高くなければいけない
が第3図の場合はコンデンサC4と抵抗■t、lの接続
点は電源の負のラインよりさらに負に下る為、演算増幅
器A。Since the output voltage of operational amplifier A2 must be higher than the forward voltage of diode D3, in the case of Figure 3, the connection point between capacitor C4 and resistors t and l is further away from the negative line of the power supply. Operational amplifier A because it goes negative.
の出力電圧はダイオードD、の順電圧より低くてもダイ
オードD3を順バイアスする事が可能であり、演算増幅
器A2出力電圧をゼロ、即ち演算増幅器A、の正入力側
と、フォトダイオードPDの7ノード及び抵抗R1の接
続(16)
点を接地してもダイオードD3Fi順バイアスする事が
でき演算増幅器A、のラッチ状態を急速に解除する事が
できる。ツェナーダイオードZD、は電源電圧の変動が
あっても通電初期時の充電電圧を一定にして常に同じ状
態を得る為である。It is possible to forward bias the diode D3 even if the output voltage of the diode D is lower than the forward voltage of the diode D, and the output voltage of the operational amplifier A2 can be set to zero, that is, the positive input side of the operational amplifier A and the 7 of the photodiode PD. Even if the connection point (16) between the node and the resistor R1 is grounded, the diode D3Fi can be forward biased and the latched state of the operational amplifier A can be rapidly released. The purpose of the Zener diode ZD is to keep the charging voltage constant at the initial stage of energization and to always maintain the same state even if the power supply voltage fluctuates.
第4図は第3の実施例である。第3図の第2の実施例と
同一回路要素は同一記号を付しである。第2の実施例で
はコンデンサC4は通電初期に一度充電され、その時に
はダイオードD、は順バイアスされず、抵抗R1とコン
デンサC3で決る所定時間後に順バイアスされる様にな
っている。第3の実M例ではトランジスタQ1がOFF
している時にダイオードD、に順方向バイアスを与
えるためのコンデンサC6は抵抗R8、R1、及び演算
増幅器A!の出力と電源の負ライン間の抵抗Ro% R
6’を介して予め充電されている。スイッチs w、’
がONされてトランジスタQ+がONすると同期し
てトランジスタQ、は抵抗R7を介してのバイアスによ
りONになりコンデンサC6の抵抗R8の端子は負ライ
ン電位となりコンデンサC0と抵抗R,,RRの接続点
は電源の負ライン側よりもさらに負側電位になり、ダイ
オードD、は順バイアスされて前述同様の動作を行う。FIG. 4 shows a third embodiment. Circuit elements that are the same as those in the second embodiment of FIG. 3 are given the same symbols. In the second embodiment, the capacitor C4 is charged once at the beginning of energization, and the diode D is not forward biased at that time, but is forward biased after a predetermined time determined by the resistor R1 and the capacitor C3. In the third real M example, transistor Q1 is OFF
Capacitor C6 is connected to resistors R8, R1, and operational amplifier A! to provide forward bias to diode D when The resistance between the output of and the negative line of the power supply Ro% R
6'. switch s w,'
is turned on and transistor Q+ is turned on, and synchronously, transistor Q is turned on by bias through resistor R7, and the terminal of resistor R8 of capacitor C6 becomes a negative line potential, which is the connection point of capacitor C0 and resistors R, RR. becomes a more negative potential than the negative line side of the power supply, and the diode D is forward biased and performs the same operation as described above.
ダイオードD4・は電源Enの電圧が変動してもダイオ
ードD。Diode D4 remains a diode D even if the voltage of the power supply En fluctuates.
の順バイアスの程度を一定にする為のものである。即ち
、トランジスタQ、がONI、てコンデンサC6の抵抗
R1とR1の接続点の電位が負ラインよりも更に負電位
になったときその負電位の大きさがダイオードD4によ
ってダイオードD、の順方向電圧である一定の値にクラ
ンプされるので電源電圧の変動にかかわりなくダイオー
ドD、へは一定の順方向バイアスが印加される。その他
の動作は第2夾施例と同様である。This is to keep the degree of forward bias constant. That is, when the transistor Q is ONI, and the potential at the connection point between the resistors R1 and R1 of the capacitor C6 becomes more negative than the negative line, the magnitude of the negative potential is increased by the diode D4 to the forward voltage of the diode D. Since it is clamped to a constant value, a constant forward bias is applied to diode D regardless of fluctuations in the power supply voltage. Other operations are the same as in the second embodiment.
第5図は第4の実施例である。この場合は光電流の対数
圧縮の方法が異なっている。第1.2.3の実施例の場
合対数変換ダイオードD、は演算増幅器A1の負入力と
出力側との間に接続されているが、第4の実施例では演
算増幅器A1の正入力側と電源の負ライン側との間に対
数変換ダイオードD11が接続されている。この場合に
はフォトダイオードPDの7ノート側に負の電荷が、前
述同様の通電初期時の演算増幅器A、の不安定な期間に
蓄積する事によりラッチが起る。スイッチsw1をON
にすると通電直後にはコンデンサc 1Gの充Km荷は
ないので抵抗R1(1s RII 、R12の接続点に
はツェナーダイオードzD2により定まる電圧が発生し
、その電圧はダイオードD Ha 、 D 、、の順方
向電圧よりも高く選ばれているのでダイオードD 1o
は順方向にバイアスされてダイオードD11の7ノード
側の負の電荷を中和する。時間経過と共にコンデンサC
IOは光電され、従って抵抗RIll 、 R11%
R12の接続点の電位は下り、ダイオードDloの順方
向電流はなめらかに減少し、コンデンサ010が充電を
完了すると抵抗R10% R11、RHの(19)
接続点の電位は電源負ライン側と同じ電位になる。この
ときダイオードD、。は完全に逆バイアスされ沖1元回
路に影41を与えない。ダイオードD、1には光電流I
Lが順方向に流れるので対数圧縮された電圧がその両端
に発生し、それはアンプA1により低インピーダンスで
他の回路に伝達される。トランジスタQ roはスイッ
チSW1がONされてから抵抗R98、コンデンサCI
Iによる所定秒時後、即ちコンデンサ010の充電かは
ぼ完了した時点でONになるようにされており、抵抗R
IO1R11及びRttの接続点を短絡し給電動作中に
例えばシャッタ制御Mgの通電制御による電源EBに対
する急な負荷変動に起因する電圧変動があっても抵抗R
1O% R11、Rttの接続点の電位変動を少くする
為である。FIG. 5 shows a fourth embodiment. In this case, the method of logarithmic compression of the photocurrent is different. In the embodiment 1.2.3, the logarithmic conversion diode D, is connected between the negative input and the output side of the operational amplifier A1, but in the fourth embodiment, the logarithmic conversion diode D, is connected between the positive input side and the output side of the operational amplifier A1. A logarithmic conversion diode D11 is connected between the power supply and the negative line side. In this case, latching occurs because negative charge accumulates on the 7th note side of the photodiode PD during the unstable period of the operational amplifier A at the initial stage of energization, as described above. Turn on switch sw1
Then, immediately after energization, there is no charge in the capacitor c 1G, so a voltage determined by the Zener diode zD2 is generated at the connection point of the resistor R1 (1s RII, R12, and the voltage is in the order of the diodes D Ha , D , , The diode D1o is chosen higher than the directional voltage.
is forward biased to neutralize the negative charge on the 7th node side of diode D11. As time passes, capacitor C
IO is photovoltaic and therefore the resistance RIll, R11%
The potential at the connection point of R12 decreases, the forward current of diode Dlo decreases smoothly, and when capacitor 010 completes charging, the potential at the connection point of resistor R10% (19) of R11 and RH becomes the same potential as the negative line side of the power supply. become. At this time, diode D. is completely reverse biased and does not cast a shadow 41 on the Oki one-element circuit. The photocurrent I in the diode D,1
Since L flows in the forward direction, a logarithmically compressed voltage is generated across it, which is transmitted to other circuits at low impedance by amplifier A1. Transistor Q ro is connected to resistor R98 and capacitor CI after switch SW1 is turned on.
It is designed to turn on after a predetermined time by I, that is, when charging of capacitor 010 is almost completed, and resistor R
Even if the connection point of IO1R11 and Rtt is short-circuited and there is a voltage change during power supply operation due to a sudden load change to the power supply EB due to the energization control of the shutter control Mg, the resistor R
10% This is to reduce potential fluctuations at the connection point between R11 and Rtt.
以上の様に本発明に従えばフォトダイオードの光電流を
高人力インピーダンス演算増幅器、対数変換ダイオード
を使用して対数変換する測光回路において通電初期時に
対数変換(20)
ダイオードとフォトダイオードとの接続点の高インピー
ダンス点に蓄積される電荷に起因するラッチを急速に中
和する事が可能となり、対数変換出力の立上り特性は低
輝#iに於ても高速応答が可能となる。又中和電流は時
間経過にエリ円滑に減少するようにすれば中和電流をス
イッチングする方式に比してノイズは発生しないので非
常な低輝度まで安定なラッチ解除動作を得ることができ
る。As described above, according to the present invention, in the photometry circuit that logarithmically converts the photocurrent of the photodiode using a high impedance operational amplifier and a logarithmic conversion diode, logarithmic conversion (20) is performed at the initial stage of energization at the connection point between the diode and the photodiode. It is possible to quickly neutralize the latch caused by the charge accumulated at the high impedance point of the latching, and the rise characteristic of the logarithmically converted output can respond quickly even at low brightness #i. Furthermore, if the neutralizing current is made to decrease smoothly over time, no noise will be generated compared to a method in which the neutralizing current is switched, so that a stable latch release operation can be obtained even at very low brightness.
第1図は、従来の′6111元装置の回路図である。
第2図は、本発明に従うラッチ解除回路を有する測光回
路の第1の実施例を含む露出装置の回路図である。
第3図は、本発明に従うラッチ解除回路を有する測光回
路の第2の実施例を含む電子シャッターカメラの回路図
である。
第4図は、本発明に従うラッチ解除回12iを有する測
光回路の第3の実施例を含む電子シャッターカメラの回
路図である。
第5図は、本発明に従うラッチ解除回路を有する測光回
路図である。
〔主要部分の符号の説明〕
演算増幅器 ・・・・・・・・・・・・・・・・・・・
・・・A1受光用フォトダイオード・・・PD
対数変換ダイオード・・・・・・・・・D1放電用一方
向性素子・・・・・・・・・D3バイアス点電位設定回
路・・・C,、R,(第2図)C6、R1,R4、QB
(第3図)
Ca s R1、R@、Q! (第4図)CIo 1i
t、、 (第5図)FIG. 1 is a circuit diagram of a conventional '6111 device. FIG. 2 is a circuit diagram of an exposure device including a first embodiment of a photometric circuit with a latch release circuit according to the present invention. FIG. 3 is a circuit diagram of an electronic shutter camera including a second embodiment of a photometric circuit with a latch release circuit according to the present invention. FIG. 4 is a circuit diagram of an electronic shutter camera including a third embodiment of a photometric circuit with a latch release circuit 12i according to the present invention. FIG. 5 is a photometric circuit diagram having a latch release circuit according to the present invention. [Explanation of symbols of main parts] Operational amplifier ・・・・・・・・・・・・・・・・・・
...A1 Photodiode for light reception...PD Logarithmic conversion diode...D1 Unidirectional element for discharge...D3 Bias point potential setting circuit...C ,,R, (Figure 2) C6, R1, R4, QB
(Figure 3) Ca s R1, R@, Q! (Figure 4) CIo 1i
t,, (Fig. 5)
Claims (1)
マージナルショート状態に接続されたフォトダイオード
、該フォトダイオードに接続された対数変換用ダイオー
ド、及び 前記演算増幅器の一方入力端子、前記フォトダイオード
の一方電極及び前記対数変換用ダイオードの一方電極の
接続点に、前記測光回路への電源からの通電開始からF
7r定のあいだ中和電流を流すラッチ解除回路を含むこ
とを特徴とする測光回路。 2、特許請求の範囲第1項に記載の測光回路において、 前記ラッチ解除回路は、前記接続点に一方電極が、また
バイアス点に他方電極がそれぞれ接続された放電用の半
導体一方向性素子及び前記通↑に開始から所定期間前記
放電用一方向性素子を時間経過とともに減少する順方向
のバイアスf:Jえるとともに前記所定期間の終了時以
後前記放電用一方向性素子が前記接続点とバイアス点と
の間を遮断するバイアスを該放電用一方向性素子に与え
るよう前記バイアス点の電位を設定するバイアス点電位
設定回路とを含むことを特徴とする測光回路。 3、特許請求の範囲第2項に記載の6111元回路にお
いて、 前記バイアス点電位設定回路は、前記電源の一方端子の
電位に対して前記演算増幅器の他方入力端子の電位f:
所定量だけ高く設定する基準電位設定回路と、前記電源
の一方端子と前記バイアス点との間に接続σれ、前記通
電開始から前記一方向性素子を介して充電されるコンデ
ンサとから成ることを特徴とする測光回路。 4、特許請求の範囲第2項に記載の測光回路においで、 前記バイアス点電位設′iIチ回路は、前記通電り開始
前に前記電源の端子間に接続されて充電されるコンデン
サと、前記通電開始すると前記コンデンサを前記放電用
一方向性水子に11直方向バイアスを与える極性で前記
バイアス点を介l−での放電路を形成するスイッチング
回路とを含むことを%徴とする測光回路。 5、%許請求の範囲第2項に記載の測光回路において、 前d已バイアス点電位設定回路は、他方電極が前記電源
の一方端子に接続された前記一方向性素子と、前記電源
の他方端子とMiJ記バイアス点との間に接続され前記
通電開始から前記所定期間のあいだ充電されて前記一方
向性水子に順方向バイアスを与え、前記所定期間経過後
に九m児了して前記一方向性素子に逆方向バイアスを与
えるコンデンサとを含むことを%徴とする測光回路。[Claims] 1. an operational amplifier, a photodiode connected in an immanent short state between the positive and negative input terminals of the operational amplifier, a logarithmic conversion diode connected to the photodiode, and a logarithmic conversion diode connected to the photodiode; From the start of energization from the power supply to the photometric circuit to the connection point of one input terminal, one electrode of the photodiode, and one electrode of the logarithmic conversion diode,
A photometric circuit comprising a latch release circuit that allows a neutralizing current to flow during a constant period of 7r. 2. In the photometric circuit according to claim 1, the latch release circuit includes a semiconductor unidirectional element for discharge, in which one electrode is connected to the connection point and the other electrode is connected to the bias point, and The unidirectional discharge element is biased in the forward direction, which decreases over time, for a predetermined period from the start of the process ↑, and after the end of the predetermined period, the unidirectional discharge element is biased to the connection point. and a bias point potential setting circuit that sets the potential of the bias point so as to apply a bias to the discharge unidirectional element to cut off the voltage between the bias point and the bias point. 3. In the 6111 element circuit according to claim 2, the bias point potential setting circuit sets the potential f of the other input terminal of the operational amplifier with respect to the potential of one terminal of the power supply:
A reference potential setting circuit that sets the reference potential high by a predetermined amount, and a capacitor that is connected between one terminal of the power source and the bias point and that is charged via the unidirectional element from the start of energization. Features a photometric circuit. 4. In the photometric circuit according to claim 2, the bias point potential setting circuit includes a capacitor connected between terminals of the power source to be charged before the start of energization; and a switching circuit that forms a discharge path through the bias point with a polarity that applies a direct bias to the unidirectional water droplet for discharging the capacitor when current is started. . 5.% Permissible In the photometric circuit according to claim 2, the front d bias point potential setting circuit includes the unidirectional element whose other electrode is connected to one terminal of the power source, and the other electrode of the power source. The terminal is connected between the terminal and the bias point MiJ, and is charged for the predetermined period from the start of the current supply to give a forward bias to the unidirectional water, and after the predetermined period has passed, the unidirectional water has completed 9m and the A photometric circuit characterized by including a capacitor that provides a reverse bias to a directional element.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14608081A JPS5848822A (en) | 1981-09-18 | 1981-09-18 | Photometric circuit provided with latch unlocking circuit |
US06/417,170 US4462670A (en) | 1981-09-18 | 1982-09-13 | Light measuring apparatus for camera |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14608081A JPS5848822A (en) | 1981-09-18 | 1981-09-18 | Photometric circuit provided with latch unlocking circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5848822A true JPS5848822A (en) | 1983-03-22 |
JPH0381090B2 JPH0381090B2 (en) | 1991-12-27 |
Family
ID=15399656
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14608081A Granted JPS5848822A (en) | 1981-09-18 | 1981-09-18 | Photometric circuit provided with latch unlocking circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5848822A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6054131U (en) * | 1983-09-20 | 1985-04-16 | 株式会社ニコン | Photography equipment |
JPS6273413A (en) * | 1985-09-25 | 1987-04-04 | Nippon Telegr & Teleph Corp <Ntt> | Method and apparatus for manufacturing magnetic recording medium |
-
1981
- 1981-09-18 JP JP14608081A patent/JPS5848822A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6054131U (en) * | 1983-09-20 | 1985-04-16 | 株式会社ニコン | Photography equipment |
JPS6273413A (en) * | 1985-09-25 | 1987-04-04 | Nippon Telegr & Teleph Corp <Ntt> | Method and apparatus for manufacturing magnetic recording medium |
Also Published As
Publication number | Publication date |
---|---|
JPH0381090B2 (en) | 1991-12-27 |
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