JPH0746481A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To pick up an object at high to low luminance with high accuracy with excellent tracking performance of an output voltage over a wide illuminance range. CONSTITUTION:A photoelectric conversion photo diode 1 is connected to a drain of a logarithmic transformation MOS transistor(TR) 2a whose gate and drain are connected and an output voltage is obtained from the gate or the drain. The drain and the gate are connected via a P-channel MOS TR 9 whose resistance is decreased attended with the increase in a photo current IP outputted from the photo diode 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for converting an optical signal into an electric signal, and more particularly to a solid-state image pickup device having a dynamic range expanded by incorporating a logarithmic conversion function.

[0002]

2. Description of the Related Art A solid-state image pickup device is small and lightweight, has low power consumption, is free from image distortion and image sticking, and is resistant to environmental conditions such as vibration and magnetic field. Further, since it can be manufactured in the same or similar process as the LSI, it has high reliability and is suitable for mass production. Therefore, the one-dimensional solid-state image pickup device is widely used in facsimiles and the like, and the two-dimensional solid-state image pickup device is widely used in video cameras and the like.

By the way, many solid-state image pickup devices have a narrow dynamic range as compared with a silver salt film. Therefore, it is necessary to precisely control the exposure amount. Has a drawback that it is likely to be crushed in black and saturated in bright areas.
A solid-state imaging device that solves these problems and has a wide dynamic range and is capable of imaging from high brightness to low brightness has been proposed. According to this, a photosensitive unit capable of generating a photocurrent according to the amount of incident light, a MOS transistor for inputting the photocurrent, and a bias for biasing the MOS transistor to a state of a threshold voltage or less and a subthreshold current can flow. Means is provided and the MOS transistor is used in the subthreshold current characteristic region, whereby the photocurrent can be logarithmically compressed and converted.

FIG. 4 shows that the applicant of the present application has previously filed Japanese Patent Application No. 1-33.
4 shows a circuit configuration of one pixel of a solid-state image pickup device filed as No. 4472. In the figure, reference numeral 1 is a photodiode that generates a photocurrent I _P according to the amount of emitted light, and its cathode has a DC voltage V via a terminal 21.
Connected to _DD1 . The anode is connected to the drain and gate of the logarithmic conversion MOS transistor 2a. The source of the MOS transistor 2a is connected to the DC voltage V _SS1 via the terminal 22.

The output of the MOS transistor 2a is taken out from the gate (drain) and input to the gate of the second MOS transistor 2b. The drain of the MOS transistor 2b is connected to the DC voltage V _DD2 via the terminal 23, and the source is connected to the capacitor 3 and the output terminal 25. The other end of the capacitor 3 is connected to the DC voltage V _SS2 via the terminal 24. The capacitor 3 plays a role of integrating the current I ₂ flowing through the transistor 2b based on the output of the MOS transistor 2a.

According to this circuit, if the output voltage V _O is set to V _O = V _OI when the time t is t = 0, the following formula can be obtained, ignoring the substrate bias effect of the MOS transistor. V _O = V _SS1 + (nkT / q) ln [(q / nkTC) ∫I _P dt + exp {(q / nkT) (V _OI −V _SS1 )}] (1) where q Electronic charge amount k; Boltzmann constant T; absolute temperature n; constant C determined by the shapes of the MOS transistors 2a and 2b C; capacitance of the capacitor 3

Equation (1) is obtained by calculating the integrated value of the photocurrent I _P and V _OI
It indicates that the sum of the constant value determined by −V _SS1 is logarithmically converted to the voltage V _O. That is, if V _O1 −V _SS1 is sufficiently small, the equation (1) becomes as follows, and the logarithmic conversion can be performed accurately.

V _O = V _SS1 + (nkT / q) ln [(q / nkTC) ∫I _P dt] (2)

As described above, the previous application (Japanese Patent Application No. 1-3)
34472), the integrated value of the photocurrent I _P is logarithmically converted. That is, during the integration period, the photodiode 1
The strength of the incident light is changed, along with this photocurrent I _P
Is changed, the integrated value is logarithmically converted (in a normal solid-state imaging device having no logarithmic conversion function, a signal proportional to the integrated value of the photocurrent I _P is obtained).
Therefore, it is possible to realize a solid-state imaging device having a wide dynamic range and capable of capturing images from high brightness to low brightness.

However, in the above-mentioned invention, when the intensity of the light incident on the photodiode 1 changes rapidly, the output voltage V _O cannot sufficiently follow the change of the intensity of the light. This is because the stray capacitance 5 exists at the connection point 4 between the N-channel first MOS transistor 2a and the second MOS transistor 2b, as shown by the dotted line in FIG. That is, (1) or (2)
In order to obtain the equation, as described in the specification of the previous application, the gate voltage V _{G of} the first and second MOS transistors 2a and 2b corresponds to the photocurrent I _P and is given by the following equation. It needs to change.

V _G = V _SS1 + V _T + {(nkT / q) ln (I _P / I _DO )} (3) where V _{T is} the threshold voltage I _DO of the first MOS transistor 2 a; A constant determined by the shape of the 1MOS transistor 2a

In the steady state, V _G is determined by the equation (3), and no current flows in the stray capacitance 5. However, when I _P changes, a current for charging or discharging the stray capacitance 5 flows in the stray capacitance 5, and when the charging or discharging is completed, the current becomes 0, and V _G becomes (3) It becomes the value given by. Therefore, the tracking of V _G is delayed with respect to the change of I _P (the time required for charging or discharging the floating capacitance 5 is delayed). Therefore, when I _P changes, the logarithmic transformation based on the equation (1) or (2) is not accurately performed.

The point at which the followability deteriorates will be described in more detail. First, the case where the light amount decreases and I _P becomes small will be described. At this time, the electric charge accumulated in the floating capacitance 5 is discharged and the potential of V _G drops, but this discharging is performed via the drain current of the first MOS transistor 2a. The drain current decreases as the gate voltage decreases. Therefore, the discharge of the charge accumulated in the stray capacitance 5 progresses, the drain current decreases as the gate voltage decreases,
The efficiency of discharge is also reduced, and the discharge time is long. Therefore, the followability of V _G to I _P change is poor.

On the other hand, when the amount of light increases and I _P increases, the electric potential of V _G rises as the floating capacitance 5 is charged. This charging current is supplied from the photodiode 1. However, the current I _P flowing through the photodiode 1 is equal to the stray capacitance 5 and the first MOS.
Since it is divided into the current flowing through the transistor 2a, the first
The more current flowing through the MOS transistor 2a, the lower the charging efficiency. However, the gate voltage of the first MOS transistor 2a rises as the stray capacitance 5 is charged, the current flowing through the first MOS transistor 2a increases, and the charging efficiency also decreases. Therefore, also in this case, the followability of V _G to the change of I _P is poor.

In order to overcome this problem, the present inventor has proposed to connect the gate and drain of the logarithmic conversion MOS transistor through a resistive impedance 8 as shown in FIG. Japanese Patent Application 4-193
I am applying for No. 37. According to this configuration, when the photocurrent I _P decreases and the drain voltage of the first MOS transistor 2a drops, the drop of the gate voltage is delayed and the drain current is kept large. On the other hand, the photocurrent I _P
, And the drain voltage rises, the rise of the gate voltage is delayed and the drain current is kept small. Therefore, the stray capacitance 6 is quickly charged or discharged, the gate voltage V _G of the first MOS transistor 2a changes quickly with respect to the change of the photocurrent I _P , and the followability thereof is dramatically improved.

[0016]

By the way, a solid-state image pickup device incorporating a logarithmic conversion circuit is required to have a wide dynamic range, and therefore it is desirable to be able to cope with a change in photocurrent over several digits. However, when it is used in a wide range in which the change in photocurrent reaches several orders of magnitude, it is not possible to obtain the application in Japanese Patent Application No.
With a resistive impedance having a constant resistance value such as No. 7, there is a problem that the above-mentioned followability cannot be sufficiently obtained. That is, when the photocurrent changes from a state of steady operation with a very large value to a very small value, the gate voltage of the MOS transistor 2a at the time of the change is high, and therefore the conductivity of the MOS transistor 2a is high. high. Therefore, if the state in which the gate voltage is high is relatively long, the photocurrent and the discharge current of the stray capacitance 7 excessively flow in the MOS transistor 2a, and the drain voltage thereof falls too much (overshoots). This means that it takes time for the drain voltage to return from the overshoot point to the desired point, and thus the above-mentioned followability is impaired.

On the other hand, when the photocurrent changes from a state of steady operation with a very small value to a very large value,
It doesn't matter much. It is because the gate voltage at the time of the change is very low and the MOS transistor 2a
This is because the drain current is suppressed due to the low conductivity of, and the drain voltage rises, but at the same time, the photocurrent easily flows to the gate side through the resistive impedance, and the gate voltage rises. .

The present invention particularly improves the followability when the photocurrent changes from a very large state to a very small state, whereby the output voltage has a good followability over a wide illuminance range, from high brightness to low brightness. It is an object of the present invention to provide a solid-state image pickup device capable of picking up images with high accuracy.

[0019]

In order to achieve the above object, according to the present invention, photoelectric conversion means is connected to the drain of a MOS transistor for logarithmic conversion in which a gate and a drain are connected, and an output is provided from the gate or the drain. In the solid-state image pickup device for obtaining a voltage, the drain and the gate are connected through a resistive impedance whose resistance value decreases with an increase in photocurrent output from the photoelectric conversion means. There is.

[0020]

According to this structure, when the photocurrent I _P decreases and the drain voltage drops, the gate voltage drop is delayed and the drain current is kept large. On the other hand, I
_{When P} increases and the drain voltage rises, the rise of the gate voltage is delayed and the drain current is kept small.
Therefore, the stray capacitance is charged or discharged quickly, the gate voltage V _G of the first MOS transistor 2a changes quickly with respect to the change of the photocurrent I _P , and its followability is improved. Moreover, since the resistance value of the resistive impedance is small in the range where the photocurrent is large, when the photocurrent changes from this state to a significantly small value, the current flowing from the gate side to the drain side through the resistive impedance. Increase, and the gate current decreases quickly,
The conductivity of the logarithmic conversion transistor also becomes low, which prevents the drain voltage from excessively decreasing.

[0021]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 shows a circuit configuration of one pixel of a solid-state image pickup device to which the present invention is applied. Here, the P-channel MOS transistor 9 is inserted between the drain and the gate of the N-channel type first MOS transistor 2a, and the DC voltage V _GG is applied to the gate of the P-channel MOS transistor 9 by the terminal 10. The gate of the second MOS transistor 2b is the first MOS
It is connected to the drain of the transistor 2a. At this time, the stray capacitances 6 and 7 are present at the gate and drain of the first MOS transistor 2a.

The operation of the P-channel MOS transistor 9 will be described here. If the P-channel MOS transistor 9 is conductive, the gate and drain voltages of the first MOS transistor 2a are the same voltage, and the voltage is obtained by the equation (3). This is P channel M
This means that the source voltage and the drain voltage of the OS transistor 9 increase logarithmically with the increase of the photocurrent I _P. On the other hand, since a constant DC voltage V _GG is applied to the gate of the P-channel MOS transistor 9, the gate-source voltage of the transistor 9 decreases logarithmically as the photocurrent I _P increases. . If the V _GG is selected so that the MOS transistor 9 operates in the sub-threshold region, the MOS transistor 9 is of the P-channel type, so that the drain-source current is equal to the gate-source voltage. It will increase exponentially with the decrease. In other words, this means that the resistance between the drain and source of the P-channel MOS transistor 9 decreases exponentially. The above can be described in terms of equations as follows.

From the equation (3), the drain voltage V _D and the gate voltage V _G of the MOS transistor 2a are: V _D = V _G = V _SS1 + V _T + {(nkT / q) ln (I _P / I _DO )} The gate-source voltage V _PGS of the P-channel MOS transistor 9 is V _PGS = V _GG −V _D = V _GG −V _SS1 −V _T − {(nkT / q) ln (I _P / I _DO )}. .. (4) Current I flowing through P-channel MOS transistor 9
_{When PD} is | V _PGS | >> kT / q, I _PD = I _PDO exp {(− q / nkT) · (V _PGS −V _PT )} ... (5) Here, I _PDO is a constant smaller than 0, and V _PT is the threshold voltage (<0) of the P-channel MOS transistor 9.

I _PD = I _PDO exp {(-q / nkT) · (V _GG −V _SS1 −V _T −V _PT )} × exp {ln (I _P / I _PO )} ... (6) Here, I _PDO exp {(-q / nkT) · (V _GG -V _SS1 -V _T-
V _PT )} is a constant, and exp {ln (I _P / I _PO )} is I _{P
Considering} / I _PO , I _PD is proportional to I _P.

As described above, the P channel MOS
It can be seen that the conductivity of the P-channel MOS transistor 9 can be made substantially proportional to the photocurrent I _P by adjusting the DC voltage V _GG applied to the gate of the transistor 9. This also means that the resistance value of the P-channel MOS transistor 9 decreases as the photocurrent increases, so that the resistance value is small in a large photocurrent range.

The operation of the circuit of this embodiment in the state where the DC voltage V _GG is adjusted as described above, especially the operation relating to the followability when the photocurrent suddenly changes will be described below.
In FIG. 1, each DC voltage is, for example, V _GG = 2V,
It is assumed that V _DD1 = V _DD2 = 10V and V _SS1 = V _SS2 = 6V are selected.

First, the case where the amount of light is reduced and the photocurrent I _P is reduced will be described. At this time, the charges accumulated in the floating capacitors 6 and 7 are discharged, and the gate voltage V _G of the first MOS transistor 2a and the first MOS transistor 2a are discharged.
Drain voltage V _D of the drain voltage decreases. This discharge is performed for the floating capacitance 7 via the drain current of the first MOS transistor 2a, while for the floating capacitance 6 is performed via the drain currents of the P-channel MOS transistor 9 and the first MOS transistor 2a.

For this reason, the discharge current i ₇ of the stray capacitance 7 flows and the voltage of the stray capacitance 7 decreases, so that the first MOS
The drain voltage V _D of the transistor 2a decreases. on the other hand,
P-channel MOS while the transistor 9 discharge current i ₆ from stray capacitance 6 is flowing in the first 1MOS transistor 2a gate - G Voltage V _G has become higher than the drain voltage V _D, its discharge current i ₆ At zero, V _G is equal to V _D. In other words, the decrease in the gate voltage V _G is delayed compared to the decrease in the drain voltage V _D. The first M
The drain current of the OS transistor 2a is the gate voltage V _G
Is higher, the drain current does not decrease much even if the discharge of the stray capacitance 7 progresses. For this reason,
The stray capacitance 6 discharged through the P-channel MOS transistor 9 is also discharged quickly.

The same operation is performed when the photocurrent I _P changes from a very large steady state to a very small value, but the P channel MOS at the time of the change occurs.
Since the resistance value of the transistor 9 is low as described above,
The discharge current of the stray capacitance 6 sufficiently flows through the P-channel MOS transistor 9, and the gate voltage is reduced more quickly, so that the conductivity of the first MOS transistor 2a is suppressed. Therefore, the problem that the drain voltage drops too much does not occur.

On the other hand, when the amount of light increases and the photocurrent I _P increases, the stray capacitances 6 and 7 are charged and the voltage of the stray capacitances 6 and 7 rises to connect them. The drain and gate voltages V _G and V _D that are present will also increase. In this case, the photocurrent I _P is the charging current to the stray capacitances 6 and 7 and the first MOS transistor 2a.
Since it is divided into the drain current flowing through the first MOS transistor 2a, the smaller the current flowing through the first MOS transistor 2a, the higher the charging efficiency. In the present embodiment, since the gate of the first MOS transistor 2a is connected to the drain via the P-channel MOS transistor 9, the rise of the gate voltage V _G of the MOS transistor 2a is delayed with respect to the rise of the drain voltage V _D. become. Therefore, the drain current does not increase so much even if the drain voltage V _D rises, and the charging efficiency of the stray capacitance 7 improves. Further, the charging of the floating capacitance 6 performed via the P-channel MOS transistor 9 is also quickly performed following the charging of the floating capacitance 7.

FIG. 2 shows a second embodiment of the present invention. In this embodiment, the second MOS transistor 2b is used.
1 is different from the embodiment of FIG. 1 in that the gate of is connected directly to the gate of the first MOS transistor 2a and is connected to the drain of the first MOS transistor 2a through a P-channel MOS transistor 9. The other parts are the same as in FIG.

Also in this second embodiment, as shown in FIG.
As described in the description of the embodiment, since the gate voltage V _G of the first MOS transistor 2a quickly follows the change in the light amount, the output voltage V _O can also quickly follow the change in the light amount.

FIG. 3 shows a third embodiment of the present invention. In the third embodiment, a switch 11 composed of a P-channel MOS transistor is connected to a connection point 12 between the anode of the photodiode 1, the drain of the first MOS transistor 2a and the gate of the second MOS transistor 2b in the embodiment of FIG. 1 is different from the embodiment of FIG. This switch 11 can select conduction or interruption by a pulse Φp given through the terminal 26, and the potential at the connection point can be set to the DC voltage V _P at the terminal 27 when conducting. Also, this switch 11 is n
It is also possible to use a channel MOS transistor or the like. Here, Φp has a peak value of 5 V and V _P has a value of 8 V, and other DC voltages are the same as those in the case of FIG.

A switch 28 is provided at both ends of the integrating capacitor 3. The switch 28 is turned off when the integration of the current I ₂ is started, and is turned on when the integrated value is cleared. Becomes The switch 28 is composed of a MOS transistor, and a control signal for ON / OFF is given to the gate. Switch 28
Are similarly provided in FIGS. 1 and 2, but are not shown.

In this embodiment, the switch 11 is turned on before the integration operation of the capacitor 3 is started, and the connection point 1
The potential of 2 is set to V _P, and the switch 11 is turned off. In the embodiment of FIGS. 1 and 2, the connection points 12 and 14
The higher the potential, the higher the gate voltage of the first MOS transistor 2a and the larger the current flowing through the transistor 2a, so that the change in the light amount can be followed in a short time. In the third embodiment, the potential of the connection point 12 can be set to an arbitrary DC voltage V _P by the switch 11, so that FIG.
As compared with the embodiment of FIG. Also in the embodiment of FIG. 2, the connection point 13 or 14 may be connected to a DC voltage via a switch. Thereby, the same effect as that of FIG. 3 is obtained.

Although the substrate of the P-channel MOS transistor 9 is connected to the DC voltage V _DD1 in the embodiments shown in FIGS. 1 to 3, it may be connected to another DC voltage. In each of the above embodiments, the first and second MOS transistors 2a and 2b may be replaced with P channel MOS transistors, and N channel MOS transistors may be used as the resistive impedance. However, in this case, the polarity of the photodiode 1 is reversed.

[0037]

As described above, according to the present invention, even when the photocurrent changes from a very large state to a very small value, the gate voltage and the output voltage of the logarithmic conversion MOS transistor can be tracked well. Since it is drastically improved, it is possible to realize a solid-state imaging device having a wide dynamic range and capable of highly accurately imaging from high brightness to low brightness.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the solid-state imaging device of the present invention.

FIG. 3 is a circuit diagram of a third embodiment of the solid-state imaging device of the present invention.

FIG. 4 is a circuit diagram of a conventional solid-state imaging device.

FIG. 5 is a circuit diagram of another conventional example.

[Explanation of symbols]

 1 Photodiode 2a First MOS transistor 2b Second MOS transistor 6 Gate stray capacitance 7 Drain stray capacitance 9 P-channel MOS transistor 11 Switch

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koichi Ishida 2-3-13 Azuchi-cho, Chuo-ku, Osaka, Osaka International Building Minolta Camera Co., Ltd. (72) Inventor Koichi Samejima 2-chome, Azuchi-cho, Chuo-ku, Osaka No. 13 Osaka International Building Minolta Camera Co., Ltd.

Claims (1)

[Claims] 1. A solid-state image pickup device in which a photoelectric conversion means is connected to the drain of a MOS transistor for logarithmic conversion in which a gate and a drain are connected to obtain an output voltage from the gate or the drain. A solid-state imaging device, wherein the drain and the gate are connected via a resistive impedance whose resistance value decreases with an increase in photocurrent output from the means.