JPS5847285A - Supplying device for voltage of electronic timepiece - Google Patents

Abstract

PURPOSE:To save the consumption of a power and prolong the lifetime of a power souce by a method wherein a voltage obtained by lowering a supply voltage is supplied to a circuit whose operation frequency is relatively high. CONSTITUTION:An oscillation signal P1 is supplied to a frequency divider 2, a frequency-division signal P3 is shaped 4, and a sampling signal P4 is supplied to a voltage level detecting circuit 5, while a signal P5 for counting is supplied to a counter 6 for control. The circuit 5 discriminates the amplitude of a voltage- division signal P6 according to the fall of the signal P4 and delivers it as a signal P7. The signal P7 controls the counter 6 to make the signal P5 perform up/ down counting, and according to the state of output of count signals S1-S3 thus obtained, an adjusting circuit 7 delivers a frequency-division signal P2 as a signal P8 having a different pulse width. The signal P8 is averaged 8 to a voltage signal P9, which changes the on-resistance of a power amplifying circuit 9 as a means for lowering a voltage which is constituted by MOSFET. As the result, an output potential VSS1 is controlled, and it is supplied to an oscillation circuit 1, a frequency-dividing circuit 2, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage supply device for an electronic watch that steps down the power supply voltage to a constant voltage and outputs a stepped down voltage that is not affected by fluctuations in the power supply voltage due to heavy loads such as when lighting a lamp. .

Recently, efforts have been made to reduce the power consumption of ICs in order to extend the lifespan of electronic watches. One of them is that lowering the voltage supplied to the IC reduces the consumption voltage, so I
A method is adopted in which the power supply voltage is stepped down to a range in which the IC can operate and is then supplied to the IC. The problem here is the step-down circuit.There is a method in which multiple resistors connected in series are connected between the power supply voltages and an arbitrary voltage is extracted from the intermediate connection of the resistors. This has the disadvantage that the oscillation circuit that receives this voltage stops oscillating due to fluctuations in the power supply voltage, resulting in a large voltage drop. In order to eliminate the above drawbacks, the present invention provides a voltage supply device for an electronic watch that can constantly monitor the step-down voltage and send a monitor signal to a circuit that controls the step-down voltage to keep the output of the step-down voltage constant. be.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an electronic timepiece according to the present invention.

1 is an oscillation circuit including a crystal resonator, and the frequency is 32768Hz.
The oscillation signal P is frequency-divided by the frequency dividing circuit 2 to become frequency-divided signals P2, P3, and 111z signals. Reference numeral 6 denotes a timekeeping circuit, which uses the lIlz signal as a manual input to perform a series of timekeeping operations such as seconds, minutes, hours, etc. Reference numeral 11 denotes a display device that displays the contents of the clock circuit 6. 4 is a waveform shaping circuit that receives the frequency-divided signal P3 as an input, outputs a voltage as described below from the output terminal Q8, and outputs a voltage as described below from the output terminal Q2 to an amplifier/down counter 6d (hereinafter referred to as UDC). A count input signal P5 is output for the counter.

5 is a voltage level detection circuit, which connects power supply terminals VDD and yss,
A level adjustment resistor R and a detection N-channel MO8) transistor Tr connected in series between them, and a data type flip-flop 5a (hereinafter simply referred to as D) for data storage.
The connection point X between the resistor R and the transistor Tr is connected to the data terminal of the DFF5a, and the gate of the transistor Tr and the DFF5
The sampling pulse P4 is supplied to the clock input terminal CL of a, and the magnitude of the divided voltage signal P6 taken at the connection point X is determined at the falling edge of the sampling pulse P4 (DF
(based on the threshold voltage vth of the transistor in FSa) and outputs it to the Q terminal as a signal P7.

6 is a control counter composed of a switching circuit consisting of AND gates 6a, 6c and an inverter 6b, and a UDC 6d, and the signal P7 is used as a switching control signal to output the UDC 6d.
It is configured to selectively switch and input the signal P5 to the down input terminal DOWN or the up input terminal UP of
3 as signals S1 to S.

Reference numeral 7 denotes a pulse width adjustment circuit which receives the frequency-divided signal P2 as an input and outputs a signal P8 having a different pulse width depending on the output state from the output terminals Q and -Q3 of the UDC 6d.

8 is a voltage averaging circuit, and the signal P8 is averaged by an f-wave circuit including inverters 8a, 8b and a resistor R capacitor C to become a voltage signal P9, which is output to a terminal Q. The level signal P becomes the gate input of the power amplifier circuit 9, which is a step-down circuit configured with a P-channel MO8) transistor as a source follower, and changes the ON resistance of the power amplifier circuit 9 according to the voltage level of the signal P9. It is configured. Moreover, the power amplifier circuit 9 is turned on with respect to the impedance between the power supply terminals of the oscillation circuit 1, the frequency dividing circuit 2, the waveform shaping circuit 4, and the voltage level detection circuit 5.
Since the resistors are connected in series, the result is that the signal P
The output potential VSS can be controlled depending on the magnitude of the voltage level of Q.

That is, the output potential VSS of the power amplifier circuit 9.

is proportional to the potential of the level signal P, and the level signal P9
When the potential approaches VDD, the output potential VSS of the power amplifier circuit 9 also approaches VDD. The potential yss of the power supply battery 10 is the clock circuit 6 and the display device 11.
, power amplification circuit 9, UDC 6, pulse width adjustment circuit 7,
and the negative power terminals of the voltage averaging circuit 8. Also, the potential vDD-■
A switch Sw and a lamp L are connected in series between S82.

FIG. 2 is a specific circuit diagram of the pulse width adjustment circuit 7 shown in FIG. 1.

7a is a flip-flop (hereinafter referred to as FF) 71-7
6, the frequency-divided signal P
Count at the falling edge of 2, and send the count contents to signals 01 to 0.
Output as 6.

7b is a zero detection circuit composed of NOR gates, which inputs the output signals 01 to 06, and receives the output signals 01 to 06.
When all are 0, the zero detection signal is output as 1.

7c is a coincidence detection circuit, exclunbu OR (hereinafter gXo
It is composed of the output signals 81 to S3 and the output signals 01 to 06, and outputs a coincidence detection signal as 1 when they match.

7d is a pulse generation circuit composed of a reset priority set/reset flip/frog (hereinafter referred to as 5RFP) 78, which uses the zero detection signal as a set input signal and uses the -number output signal as a reset input signal to generate a signal P8. Output.

The time chart in FIG. 3 shows the frequency division signal P2 of the frequency division circuit 2,
Sampling signal P4 of voltage level detection circuit 5, UDC
6d count input signal P5, and a signal P8 [Sl, S2, S3] taken by the pulse width adjustment circuit 7 corresponding to the count number of the UDC 6d, that is, the contents of the signals 81 to S3.
That is, a signal P8 pressure waveform diagram is shown.

Next, the operation of the electronic timepiece with the above configuration will be explained.

First, the voltage VDD-VSS2 of the power supply battery 10 is set to 1.5v.
and the output signals 81 to S3 of the UDC 6d are [0,0
, 0] will be explained.

The output signals S, ~S3 of the UDC 6d are [0, 0, 0]
At this time, the output signals 01 to 06 of the period determining counter 7a become [0] due to the input of the frequency dividing signal P2 of the frequency dividing circuit 2
, O10], the zero detection signal of the zero detection circuit 7b and the coincidence detection signal of the -multiple output circuit 7C both become 1, and the output signal P8 is output to reset the S RFF 7q.
■Takes the S82 level signal. From this state, when the frequency division signal P2 is input to the period determination counter 7a, the zero detection signal of the zero detection circuit 7b and the -several output circuit 7
Both of the coincidence detection signals of c become 0, and the output signal P8 of the 5RFF7q maintains a signal at the vS82 level. Result 3rd
A signal with a level of <yss, as shown by pit[o,,0.0] in the figure is taken. Next, the output signal 81~ of the UDC6d
The case where S3 is [1, 0, 0] will be explained.

First, the output signals 01 to 06 of the period determining counter 7a
Consider the case where is [0, 0, 0].

At this time, the zero detection signal of the zero detection circuit 7b is 1, and the -
Since the coincidence detection signal of the several-building output circuit 7C becomes O, the above-mentioned 5R
FF7q is set and a VDD level signal is output as output signal P8. From this state, the frequency-divided signal P2 is used as the period determining counter 7b, and the output signals 01 to 01-
When 06 becomes [1, 0, 0], the zero detection signal of the zero detection circuit 7b becomes 0, while the coincidence detection signal of the coincidence detection circuit 7c becomes 1, so rq'B SRF'F 7
q is reset and a signal of level yss is outputted to the output signal P8, and a signal of level SS2 is outputted until the output signals 01 to 06 of the period determining counter 7a become [0, 0, 0]. continue. P8 of result figure 3 [1
, 0, 0] as shown in the output signal. Hereinafter, the output signal P8 controlled by the output signals S, ~S3 is P8[0
, 1, 0] to P8 [1, ■, 1].

The output signal P9 of the voltage averaging circuit 8 is the signal P8[0,0,
OV when the signal is 0], approximately 01 when the signal P8 is [1, 0, 0]
9■, approx. 0.38V when signal P8 [0, ■, 0], approx. 0.57V when signal P8 [1, 1, O], signal P8 [
0,0,1], approximately 075V, signal P8[1,0,1
], about 0.94V, signal P8 [Oll, 1], about 1.13V, signal P8 [1,1,1], about 1
．． There is a proportional relationship of 31V, and the signal P8 [0,0,
0], yDn-y is controlled by the power amplification circuit 9.
ss, the mold pressure reaches a maximum of approximately 1.5■, and below, the signal P
8 [1, 0, 0] to signal P8 [1, ■, ■], the mold pressure between VDD and VSSI changes to 1.
It changes as 4v, 1.3■...0.8■.

For example, if the signal P8 [0, 0, 0] is taken in the initial state, when the sampling signal P4 is input to the voltage level detection circuit 5, the transistor Tr is turned on, and the ON resistance of the transistor Tr and the resistance R are The magnitude of the divided voltage signal P6 resulting from the voltage dividing operation at the connection point X is written into the DFF 5a at the falling timing of the sampling signal P4, and the output signal P7 is set to the logic O level. When the output signal P7 is at the logic 0 level, the AND gate 6a constituting the control counter 6 is in the OFF state, while the AND gate 6c is in the ON state because the output signal P7 is inverted by the inverter 6b and becomes a logic level. The UDC 6d enters the up mode, counts at the falling timing of the count input signal P5 in FIG. 2, and outputs [1, 0, 0] from the output signals 81 to S3 of the UDC 6d. The output signals 81 to S3 are set to the pulse width adjustment circuit 7 by [1, 0, 0].
The output signal P8 has a pulse width as shown in FIG.
8[1,0,0] is output. The output signal P8[1,
0,0] is the voltage between vDD and 7881 which is set to 1 in order to raise the gate potential of the voltage averaging circuit 8 and the power amplifier circuit 9.
．． 4 Works to lower VK.

In this way, until the voltage level detection circuit 5 reaches the judgment potential adjusted by the resistor R of the voltage level detection circuit 5, the voltage level detection circuit 5 outputs an up control signal, that is, a logic 0 level signal P7 to the control counter 6, and outputs the count input signal U by P5
The DC 6d continues to count up, and when it finally settles down, a desired low voltage is always supplied to the oscillation circuit 1, etc., and an operating state with low power consumption is assumed.

Next, turn on the switch Sw, turn on the lamp L, and turn on the battery 1.
A case will be described in which the voltage between VDD and vS82 drops due to the influence of the internal impedance of 0. V n D-
When the voltage between V S "' 2 decreases, VDD-yss,
The potential between them also decreases relatively, and the voltage level detection circuit 5
When the sampling signal P4 is input to the DFF 5a, the divided voltage signal P6 becomes higher than the determination potential, and the output signal P7 of the DFF 5a outputs a logic level at the falling timing of the sampling signal P4. The output signal P is an AND game) 6a
is turned on, and inverted by inverter 6b, AND
In order to turn off the gate 6c, the UDC 6d is set to down mode and the count input signal P is output.

Performs down-count operation at the falling edge of .

When the down-count operation continues, the pulse width adjustment circuit 7
The output signal P8 is output in the order from signal P8 [1, 1, ■] to signal P8 [0, 0, 0] in FIG. , the voltage between VDD and 7885 increases, and the voltage necessary to maintain the oscillation operation is automatically supplied to the oscillation circuit 1 even under heavy load driving conditions such as lighting the lamp L. can.

As described above, according to the present invention, an electronic watch can save power consumption by supplying a voltage obtained by stepping down the power supply voltage to circuits with a relatively high operating frequency, such as an oscillation circuit and a frequency dividing circuit. Long life is possible. In addition, the stepped-down voltage is used to light lamps, etc., and even when the power supply voltage fluctuates due to an increase in battery internal resistance at low temperatures, the stepped-down voltage is constantly corrected to supply the desired voltage at which the IC can operate, so oscillation does not stop. It is possible to provide an electronic clock that can be operated without any need.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the pulse width adjustment circuit 7 shown in FIG. 1,
FIG. 3 is a time chart showing the main voltage waveforms in FIG. 1. 1... Oscillation circuit 5... Voltage level detection circuit 6... Control counter 6d... Up/down counter 7...
・Pulse width adjustment circuit 7a...Counter for period determination 7b...Zero detection circuit 7c...-Several sheet output circuit 8...Voltage averaging circuit 9 ...Power amplifier circuit 10...Batteries P1 to P, ...Signal y<2, y2 0:1001 Q) c. CLCLCL CL

Claims (1)

[Claims] an oscillation circuit, a step-down circuit connected in series to a power supply terminal of the oscillation circuit, a voltage detecting circuit for detecting the voltage supplied to the oscillation circuit, a bell detection circuit, and an output from the voltage level detection circuit; A control counter whose amplifier down counting operation is controlled by a signal, a pulse width adjustment circuit which outputs adjusted signals having different pulse widths corresponding to each count taken by the control counter, and the pulse width adjustment. a voltage averaging circuit that receives the output signal of the circuit as an input and supplies an averaged voltage to the input of the step-down circuit means; a zero detection circuit that outputs a zero detection signal when the contents of the period determination counter become zero, and the contents of the period determination counter and the control counter, - a coincidence detection circuit that outputs a number output signal; and a pulse width that corresponds to a period from when the zero detection signal from the zero detection circuit is output to when the coincidence detection signal from the minus number output circuit is output. and a pulse generating circuit that generates a signal to be adjusted, and the step-down circuit means is comprised of a MOS (MOS) run sister whose ON resistance is controlled by the voltage level of the voltage averaged. Clock voltage supply device.