JPS5846906B2 - memory kudohoshiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal writing/reading method for AD converting an image signal, storing it in a memory, and supplying the stored signal to a plurality of scanning systems having different scanning speeds, scanning directions, etc. It is something.

When copying a high-speed signal such as a television image signal onto paper or film, the scanning speeds of television scanning and hard copy scanning are very different, so the high-speed signal must be directly applied to the note copy recording device. I can't.

This requires some sort of scan conversion device.

The present invention relates to an image signal writing/reading method suitable for this scan conversion device.
An embodiment in which sampling is performed at 6 points and 96 points horizontally, one pixel is stored in a memory as a 6-bit resolution, and this is recorded and reproduced as a copy image will be described.

Figure 1 is a diagram showing the memory drive system for 1 bit when one pixel is decomposed into 6 bits. In reality, a circuit is required for each bit of one pixel, but here we will explain the circuit processing for one bit of one pixel.

In FIG. 1, numeral 1 denotes a main memory, which has a capacity to store at least one screen worth of image signals, and has a number of bits equal to or greater than the number of sampling points of screen image signals.

For this embodiment, it is sufficient that the number of bits is 96×116=11136 bits or more.

The image signal T to be recorded is input to the input of the main memory 10.
One bit of the 6-bit digital signal AD-converted by the D converter 18 and the output signal of the main memory 1 itself are transferred to a switch circuit 5 consisting of Nant gates 51, 52, 53, and an inverter 54. are added alternately through.

The switch circuit 5 receives a gate pulse G applied to the terminal 24.
It can be switched by

Buttons 2 and 3 are sub-memories for monitor display, each having a capacity of half the number of samplings in the horizontal direction, 48 bits in this embodiment.

The output of the main memory 1 is supplied to the sub-memory 2, and the output of the sub-memory 2 is supplied to the sub-memory 3.

The outputs of the sub-memory 2 button and sub-memory 3 are connected to terminals 21.
Control pulse HC and clock pulse C1 applied to 22
The signal passes through a switch circuit 6 controlled by $ and their inverted pulses HC and C, passes through a DA converter 8, and is applied to a monitor television 9.

14, 15, 16, and 17 are inverters.

Reference numeral 4 denotes a recording submemory, which has a capacity of 116 bits in the number of bits in the vertical direction, which is equal to the number of samplings in the vertical direction.

The sub-memory 4 is supplied with a signal for one column in the vertical direction from the main memory 1 via the Nantes gate 7, and the signal is supplied to the D
After being converted into an analog signal by the A converter 10, it is supplied to the recording device 11.

It is assumed that the recording device 11 performs main scanning from bottom to top and sub-scanning from right to left.

The Nantes gate 7 is opened and closed by the output from the Nantes gate 27 of a recording operation designation signal H, which is applied to the terminal 26 and is 1 when the recording device is in operation, and O when it is not in operation, and a recording control signal R, which is applied to the terminal 25. This NAND output is further inverted by the inverter 12 to open and close the NAND gate 13, thereby opening and closing the circulation path of the sub-memory 4.

28 is an inverter, and 29 is a Nant gate.

2 and 3 are timing diagrams for capturing an image signal from a television camera for one screen and displaying the still image on the monitor television 9. The terminals 21 and 2 in FIG.
2 and 24 are shown.

A control pulse HC which is O in the odd horizontal scanning period and 1 in the even horizontal scanning period is applied to the terminal 21, and the control pulse HC is applied to the terminal 22.
A clock pulse C1 is added to the clock pulse C1 in which the number of pulses to be pressed in one horizontal scanning period (hereinafter referred to as IH period) is 1/3 of the number of sampling points.

There are 116 and 48×232 control pulses HCi- and clock pulses C1, respectively, during the vertical scanning period (hereinafter referred to as 1v period).

The clock pulse C1 is used as a clock pulse for the main memory 1 during signal writing, and is also used as a clock pulse for the submemories 2 and 3.

A gate pulse G is applied to the terminal 24, with one peak for every four clock pulses C1.

The gate pulse G specifies the timing of writing a signal from the AD converter 18 to the main memory 1, and provides the sampling rate of the AD converter 18.

In this case, a clock pulse with a frequency of 2C1 is applied to the AD converter 18, and sampling is performed once every eight clock pulses.

This is because a sequential comparison type is used as the AD converter 18, and the first to sixth bits are compared at the timing of six clock pulses, and the other two are used to compare the first to sixth bits. Perform import and sample hold.

FIG. 4 shows the signal waveform used when reading signals. The signal R is 1 when the recording device 11 is in operation, that is, when H=1, 1 is at the time of recording when the recording pen etc. is in operation, and 1 is at the time of return. is a recording control signal which is O and is applied to terminal 25.

Pulse C3 is a clock pulse for sub-memory 4, and R-1
When R=0, 115×116 pulses are generated, and when R=0, 116 pulses are generated in one period of the period.

Next, a method of sampling an input image (input from the terminal 23) and importing it into the main memory 1 will be explained.

The scanning of a television camera includes 263 (or 262) horizontal scanning lines within one period in the NTScj5 format.

By the way, the number of pixels in the vertical direction required for this embodiment is 116, which is less than 1/2 of the number of horizontal scanning lines (263 or 262) included in the 1v period.

Therefore, two horizontal scans can correspond to one pixel in the vertical direction.

In this case, there will be a shift between the image input in the odd-numbered horizontal scan and the image input in the even-numbered horizontal scan, but this does not pose a problem in this embodiment and can be ignored. The number is 96, which is 1
If data is to be captured in the 2H period of the v period, the sampling frequency will be high, and an expensive AD converter with a speed of 1 μsec or less will be required.

Therefore, all pixels in the horizontal direction are taken in during the 2H period of the 4■ period.

In this way, the sampling frequency required to capture one screen's worth of information can be reduced to 1/8 (that is, by using the 2H period, it is reduced to 1/2, and by using the 4■ period, it is further reduced to 1/4). It can be dropped.

FIG. 5 illustrates the above method.

That is, during the IH period, sampling is performed at 8 points, and during the first vertical scan, during the horizontal scan...1, 9, 17, 25.
...89 Even number horizontal scanning ...2, 10, 1
8,26. ...90 During second vertical scanning, during odd-numbered horizontal scanning...3, 11, 19, 27.
...91 even number horizontal scanning ...4, 12, 2
0,28. ...92 During third vertical scanning, during odd-numbered horizontal scanning...6, 13, 21, 29.
...93 Even number horizontal scanning ...6, 14, 2
2,30. ...94 During the fourth vertical scan, during odd-numbered horizontal scans...7, 15, 23, 31.
...95 even number horizontal scanning...8, 16, 2
4,32. ...Sampling like 96.

In this way, the signal for one screen is extracted as a digital signal.

This digital signal is stored in the main memory 1 as follows.
will be written to.

When writing a signal, main memory 1 receives clock pulse C.
1 has been added.

On the other hand, the recording operation designation signal H applied to the terminal 26 is O.

Therefore, the gate pulse G is applied to the Nandts gate 51 via the Nandts gate 29 and the inverter 54, the Nandts gate 51 opens, and the digital signal from the AD converter 18 passes through the Nandts gates 51 and 53 and is input to the main memory 1 according to the clock pulse C1. Added.

Gate pulse G becomes O at the next moment, and Nantes gate 5
1 is closed and the Nantes gate 52 is opened.

On the other hand, three clock pulses C1 are generated until the next gate pulse G arrives.

Therefore, the contents of main memory 1 are rotated and shifted three times.

As a result, if the state in which the digital signal is captured in the main memory 1 is 1, and the state in which it is not captured is O, then one gate pulse G is applied, and then the next gate pulse G is applied.
1000 is memorized by the time .

When the next gate pulse G is input, a digital signal is applied from the AD converter 18 to the main memory 1, and the same operation is repeated thereafter.

In this way, 12 points are sampled per horizontal scan using 12 gate pulses G, and are written into the main memory 1 (the shaded area at the top right in the figure).

Next, in the second horizontal scan, the generation timing of the gate pulse G is delayed by one pixel, that is, 1/2 cycle of the clock pulse C1, compared to the first horizontal scan, and writing is performed in the same manner.

Thereafter, the same operations as the first horizontal scan are repeated for the odd-numbered horizontal scans, and the same operations as the second horizontal scans are repeated for the even-numbered horizontal scans, and the first vertical scan ends when the 232nd horizontal scan ends.

In the second vertical scan, the generation timing of the gate pulse G is delayed by two pixels, that is, one clock pulse C1, from that in the first vertical scan, and the same operations as in the first vertical scan are repeated.

During the third and fourth vertical scans, the timing of the generation of the gate pulse G is further shifted by one clock pulse C1, and the same operation is performed.

When the fourth vertical scan is completed in this way, all the signals for one screen are written into the main memory 1.

The written pixel is (171) + (3
, 1), (5, 1) (7, 1), ... (95° 1), (2, l), (4, 1), (6, 1).

(8,1),...(96,1), (1,2).

(3,2),..., (95t 2 ), (2
+2).

・・・・・・(96,2), ・・・・・・,(1t11
6) , (3t116), ...... (95,116
), (2,116: (4,116), ...... (9
6,116) 1:f136 pixels.

During the signal writing period, the output of the main memory 1 is circulated to the input of the main memory 1 according to the falling timing of the clock pulse C1, and the output of the sub memory 2 is also input to the sub memory 2 button and the Nantes gate 61. The signal is input to the sub-memory 3 (and NAND game) 62 and 63 in accordance with the falling timing of the clock pulse C1.

The output of the submemory 3 is input to one input terminal of the Nant gate 64.

The Nant gates 61 and -64 are opened and closed in response to the control pulse HC and the clock pulse C1. For example, during even-numbered horizontal scanning (HC=1), the sub-memory 2 displays (ltn) in the coordinate display shown in FIG. t(3tn)t・・・・・・(9
5, n), the main memory 1 stores (2jn)j(4
, n) t... (96, n),
It shifts with clock pulse C1.

When the clock pulse C1 enters, the Nantes gate 61 opens, while when the clock pulse C1 does not enter, the Nantes gate 62 opens. Therefore, the outputs of the sub memory 2 and main memory 1 pass through the Nantes gate 65 in response to the clock pulse C1. (ltn) in the coordinates shown in Figure 5.
j(2,n)j(3jn)? (4゜n),...
(96, n) are added to the DA converter 8 in the order of f'L, 2
It is converted into an analog signal at a sampling rate of C1 and displayed on the monitor television 9.

In this case, the scanning speed that can be pressed on the monitor TV 9 is the terminal 2.
It is the same as the scanning speed of the image signal added to 3.

During odd-numbered horizontal scanning (HC=O), the contents of submemory 2 are moved to submemory 3, the first 48 bits of the memory are moved to submemory 2, and the outputs of submemories 2 and 3 are alternated. In the coordinate display of Figure 5, (1, n), (2, n), (3,
n)...(96°n) are added to the DA converter 8 and displayed on the monitor television 9.

In this way, the same signal in the 2H section is displayed.

Therefore, the signal can be written into the main memory 1 and monitored on the monitor television 9 at the same time.

When reading a signal, the same clock pulse C1 as when writing is applied to the main memory 1.

A recording control signal R is applied to the terminal 25, and a clock pulse C3 is applied to the submemory 4.

The recording operation designation signal H input to the terminal 26 is 1.

Since R=0 in the recording preparation state when the recording pen returns, the Nantes gate 7 is opened.

At this time, the Nandt gate 13 is closed by the inverter 12.

The signals successively read out from the main memory 1 by the clock pulse C1 are applied to the submemory 4 through the Nant gate 7.

However, at this time, the clock pulse C of sub-memory 4
3 is 1v as seen in the timing chart in Figure 4.
During this period, 116 lines are generated, that is, at a rate of one every 2H, and the contents of the main memory 1 are read out to the sub memory 4.

Therefore, the signal stored in the submemory 4 is 1 every 2H.
Selected by percentage of sampling points.

This selected sampling point corresponds to a signal component on one vertical line.

That is, in the sub-memory 4, (n, 1
), (n, 2)... (n, 116).

In this way, signals for one line in the vertical direction are stored in the submemory 4.

Next, when R=1, the Nantes gate 7 is closed and the Nantes gate 13 is opened.

In this state, if clock pulse C3 is applied to sub-memory 4 (which has 116 sets of 115 pulses shown in FIG. 4), the contents of sub-memory 4 will be changed to 1.
The information is circulated through the Nantes Gate 13 each time the person in question receives the information.

Then, the contents of the submemory 4 are read out every 115 clock pulses, and within the period of R=1, the coordinates shown in FIG.
n, 116), (n, 115).

116 points are read out in the order of (n, 114)...(nti), added to the DA converter 10, and then added to the recording device 11.
The signal is converted into an analog signal at a sampling rate synchronized with the scanning rate of , and then applied to the recording device 11 where it is recorded by a recording pen.

The scanning speed of the recording device 11 is generally low, and in this embodiment, it is approximately 115 times faster than the scanning speed of the image signal input to the terminal 23.
It is about 00.

Note that the reason why the contents of the sub-memory 4 are shifted by 115 is because the order of writing to the sub-memory 4 is reversed.

When this operation is repeated 116 times, signals for one line in the vertical direction are read out.

When R=0 again, the signal of the next line in the vertical direction is stored in the submemory 4, and when R=1 again, it is read out.

When the same operation is repeated 96 times, all the signals of one stroke stored in the main memory 1 are read out, and the recording by the recording device 11 is completed.

Regarding the above-mentioned configuration, even if the button is pressed after the recording operation is specified by the recording device 11 or after the recording operation is finished, the monitor television 9
will be displayed.

In other words, when the recording operation designation signal H is 1, the Nant gate 29 is always closed.

Therefore, a circulation path of the main memory 1 is formed by the Nando games 52 and 53.

Further, the contents of main memory 1 are sent to submemories 2 and 3.

These are passed through the switch circuit 6 in response to the control pulse HC and the clock pulse C1 as described above, and are transferred to the DA converter 8.
After being converted into an analog signal, it is displayed on the monitor television 9.

If the main memory 1 is a dynamic shift register, the contents stored during the vertical retrace period may disappear.

To avoid this, an auxiliary pulse may be added to the end of the clock pulse C1 in each 1V period, and the capacity of the main memory 1 may be increased by an amount equal to the number of auxiliary pulses.

In the above embodiment, the scanning speed of the input image signal applied to the terminal 23 and the scanning speed of the image signal applied to the monitor television 9 are the same.

Therefore, it is also possible to directly apply the input image signal applied to the terminal 23 to the monitor television 9 without going through the main memory 1, submemories 2, 3, etc.

However, the image signal input to the terminal 23 is a moving image,
If you want to monitor a still image at a certain moment in the moving image, you cannot observe it even if you directly input the image input to the terminal 23 to the monitor television 9.

In such a case, it is necessary to write the input image to the terminal 23 in the main memory 1, submemory 2.degree. 3, etc. as in the above embodiment, read it out, and supply it to the monitor television 9.

Furthermore, in the above embodiments, the case where the input image is a television signal captured by a television camera has been explained, but image signals recorded on a videotape, video sheet, etc., and image signals obtained by a scanner, etc. may also be used. Applicable.

In the above embodiment, the scanning system is a low-speed recording device using a monitor television whose main scanning is horizontal and a recording pen whose main scanning is vertical. Something like this is fine.

As described above, the present invention converts an analog image signal such as a television signal into a digital signal and stores it in a memory. This provides an image signal writing/reading method in which multiple scanning systems with different scanning speeds or scanning speeds are driven by applying different clock pulses. The reproducing systems can be put into operation simultaneously or separately.

For example, by pressing the button in the embodiment of FIG. 1, it is possible to operate the monitor television 9, which scans from left to right at high speed, while recording device 11, which scans from bottom to top at low speed, is in operation.

Further, when recording in the recording device 11 is completed, the contents of the main memory 1 are displayed on the monitor television 9 even if the recording operation designation signal H remains in the recording operation designation state (H=1).

Therefore, as well as monitoring during hard copy recording,
Even when recording the same copy again after recording, or when the recording operation must be canceled due to a malfunction during recording, the recording operation designation signal H is set in the writing state (H
= O) without switching to the recording operation specified state (H =
1) The image to be recorded can be monitored.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the overall configuration of a memory drive system in an embodiment of the present invention, and FIGS. 2, 3, and 4 are pulse waveform diagrams used in the embodiment of FIG. FIG. 5 is an explanatory diagram of the image sampling method used in the present invention. 1... Main memory, 2, 3, 4...
Sub memory, 5, 6...Switch circuit, 7...
...Nant Gate, 8,10...DA converter, 9...Monitor TV, 11...
Recording device, 18...AD converter.

Claims (1)

[Claims] 1. A first digital memory having a capacity for at least one screen, a second digital memory having a capacity for at least one scan line in the first scanning direction, and a second digital memory having a capacity for at least one screen in the first scanning direction; a third digital memory having at least a capacity corresponding to one scanning line pixel in a second scanning direction for performing surface scanning; and a third digital memory for performing scanning in the same scanning direction as the first scanning direction; a first scanning system that repeats scanning in the same direction as the second scanning direction to form one screen; and a second scanning system that repeats scanning in the same scanning direction as the second scanning direction in the first scanning direction to form one screen. The input image signal is AD-converted and written intermittently to the first digital memory, and the writing point is sequentially shifted by multiple surface scans, so that the signal for one screen is accumulated, and the signal for one screen is stored in the first digital memory. The accumulation signal is accumulated in a second digital memory corresponding to the scanning speed of the first scanning system;
The signals stored in the digital memory of A portion of the output of the memory is supplied to the third digital memory, and the third digital memory is written at a speed corresponding to the scanning speed in the second scanning direction, and at a speed corresponding to the scanning line of the second scanning system. An image signal writing/reading method characterized in that the image signal is read out and supplied to the second scanning system, and scanning in the second scanning direction is sequentially repeated with respect to the first scanning direction.