JPS5846895B2 - Sentakuyobidashijiyushinsouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a selective call receiving device used in a selective call system that selectively calls a specific subscriber from among a plurality of subscribers, and particularly relates to an improvement in means for preventing erroneous calls.

In this type of selective calling system, the calling sensitivity is a factor that determines the basic performance, but the causes of decreasing the calling sensitivity vary depending on the communication method adopted.

For example, in a selective calling system that employs a digital method in which paging signals for individual subscribers are encoded and sent out in a time-division manner, the corresponding subscriber may not be called by the signal reproduced on the receiving side due to bit errors in the transmission path. Arise,
As a result, the calling sensitivity decreases.

As is well known, error control methods for controlling bit errors include a method using an error correction code, an error detection method, a transport verification method, and the like.

Among these methods, the error detection method, transportation verification method, and the like are useful in that they operate reliably without causing erroneous calls, but on the other hand, they are not very advantageous in terms of increasing call sensitivity.

On the other hand, if an error correction code is used, it is possible to correct errors within a certain number of bits in one code word, thereby increasing paging sensitivity.

However, in this case, since correction of errors exceeding the above-mentioned certain bits results in erroneous correction, there is an inherent drawback that a call is required as a result.

Therefore, the present invention provides a selective call receiving apparatus that is equipped with means for preventing erroneous calls that occur when the call sensitivity is improved.

That is, the present invention improves the call sensitivity by performing a discrimination operation on the selectively detected self-call signal only when the reception condition is good, and stopping the discrimination operation when the reception condition is poor. This is to prevent erroneous calls.

Examples will be described below.

FIG. 1 and FIG. 2 are diagrams showing one embodiment of the present invention.

In FIG. 1, 1 is a waveform shaping circuit that reproduces the received and demodulated baseband digital signal a, and the signal that has passed through this waveform shaping circuit 1 is differentiated by a differentiating circuit 2 at the next stage, and is converted into either a rising or falling signal. The polarity change point is detected.

The polarity change point detection signal of the differentiating circuit 2 is used to open the AND gates 3 and 4 and to reset the ring counter 5.

The ring counter 5 is a counter that counts the clock signal d, which is four times the data rate of the input signal a, generated from a high-speed clock source (not shown), with the number of states being 4, and the count content is "0".
The output corresponding to is sent to the down terminal of the up/down counter 6 via the AND gate 4, and the count content is "1" to "1".
3'' are respectively supplied to the up terminal of the up/down counter 6 via the OR gate and the AND gate 3.

The flip-flop 8 is reset when the count of the up/down counter 6 is "3" and set when the count is 0, and supplies a Q output to the memory 9.

This memory 9 holds the Q output for a certain period of time and continues to send it to the AND gate 10.

The reason why the memory 9 retains the Q output of "O" for a certain period of time is that when all the digital signals a consisting of an n-bit calling signal code string are detected, the calling signal detecting circuit 12, which will be described later, outputs its own calling signal. This is because since f occurs, it is necessary to inhibit the AND gate 10 until the time when the calling signal is generated.

On the other hand, the own calling signal f extracted by the calling signal detection circuit 12 from the specific time band of the digital signal a timed by the reproduced clock signal e in the retiming circuit 11 is supplied to the AND gate 10, and the other Only when the AND gate 10 is open due to the output of the memory 9 which is the input, the signal is applied to, for example, a call signal determining means (not shown).

The operation of the embodiment device configured as described above will be explained.

The ring counter 5 that counts the high-speed clock signal d is reset by the detection signal S, so if the time relationship between the signals is always constant, the count content of the ring counter 5 reaches "O" every time it goes around, and the signal S is reset. The phases match.

This means that the transmission and reception are synchronized, and generally corresponds to a case where the reception condition is good.

Therefore, the AND gate 4 is opened every time the polarity is changed, and the up/down counter 8 is counted up by 0'' of the ring counter 5.

If this state continues, the count content of the up/down counter 8 will be '0' as shown in FIG.
The Q output of is "1" and the AND gate 10 is open.

Therefore, the call signal f passes through the AND gate 10.

However, if the reception condition deteriorates and the polarity conversion point of digital signal a deviates from the normal position due to jitter, etc.
The count content "0" of the ring counter 5 and the signal S are out of phase.

Therefore, the count contents of the ring counter 5 at the time of polarity change are often other than 0'', and the contents of the up/down counter 6 cannot maintain 0''.

Under such a situation, the count contents of the up/down counter 6 change as shown in FIG. 2a.

When the content of the up/down counter 6 becomes 3", the flip-flop 8 is reset and the Q output becomes "O" as shown in FIG. C) for a period determined by the number of bits of the calling signal code string.

to close the AND gate 10.

In other words, the period during which the AND gate 10 is closed is sufficient to prevent the passage of the paging signal f detected after the content of the up/down counter 6 reaches 03'', and for example, if the paging signal code string is n bits. When configuring (n-1)
By closing the AND gate 10 for a period corresponding to the bit, passage of the calling signal f can be prevented.

Then, when the reception condition improves and the clock synchronization between the transmitter and receiver starts to be established again, the count content of the up/down counter 6 becomes "0".
Then, the flip-flop 8 is set.

In this way, since it is determined whether or not to use the detected paging signal according to the count contents of the up/down counter (frequency of clock synchronization), erroneous paging can be prevented even when paging sensitivity is improved using an error correction code. be able to.

It should be noted that the number of states of the ring counter 5 can be changed as appropriate according to the high speed clock signal d, and the number of states of the up/down counter or the count contents for driving the flip-flop 8 are not limited to the above-mentioned case.

The flip-flop 8 is the “0” of the up/down counter 6.
” is used as a set input, and “3” is used as a reset input. However, the signal that drives the flip-flop 8 is O” if the set input count content <reset input count content is met, but it is not necessary to limit it to 3. do not have.

The contents of the set input and reset input counts are determined by how much deterioration of the reception condition is determined to inhibit the ringing signal f detected by the ringing signal detection circuit 12. For example, the smaller the reset input count is, the smaller the reception condition is. Even if the reception condition worsens, the reset input count content may be increased if there is no problem even if the reception condition deteriorates to some extent.

Further, the rate of rise and rate of fall of the count contents of the up-down counter may be different.

As described above, the present invention determines whether or not to use the detected paging signal depending on the quality of the reception condition, so it is possible to prevent erroneous paging when using an error correction code to improve paging sensitivity. Moreover, since the received digital signal is directly used, it is possible to provide a selective call receiving apparatus that can quickly determine whether the reception is good or bad.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of an apparatus showing an embodiment of the present invention, and FIG. 2 is a signal waveform diagram of each part in the above-mentioned apparatus. 1...Waveform shaping circuit, 2...Differentiating circuit, 3,4゜10.21.23...AND gate, 5...Ring counter, 6 ...Up-down counter, γ...Or gate, 8...
...Flip-flop, 9...Delay circuit,
11...Retiming circuit, 12...
Ringing signal detection circuit.

Claims (1)

[Claims] 1. A circuit that obtains a polarity conversion point detection signal that changes depending on the reception condition from the received digital signal, and is reset by the polarity conversion point detection signal output from this circuit, and is approximately n times the digital signal (n is an integer). a ring counter that counts up to state n using a high-speed clock signal having a speed of Counting content output from this gate ″O
an up/down counter that counts down when `` and counts up when the count content is other than ``0'';
and means for inhibiting the gate for a predetermined period of time to prevent passage of the self-calling signal detected from the digital signal when the count value of the up-down counter reaches a predetermined deterioration amount that should prohibit reception. A selective call receiving device characterized by: