JPS5846747A - Circuit adaptor - Google Patents

Abstract

PURPOSE:To ensure the common control for circuit adaptors regardless of the presence or absence of an FIFO memory, by detecting a transmission overrun error through a URT even for a circuit adaptor using an FIFO memory. CONSTITUTION:A reception control circuit 7 inspects the state of a universal receiver transmitter (URT)5 and an FIFO memory respectively. Then the receiving data bit is forcibly shifted to the URT from the FIFO memory in case a receiving overrun is caused. In such way, the common control is carried out through a communication controller 2 regardless of the presence or absence of an FIFO memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a communication control device for a data communication device. In particular, it relates to a character buffer type line adapter that serves a bit buffer circuit.

Conventionally, as shown in FIG. 1, data received from a line is assembled into characters by a line adder 1 and then sent to a communication control device 2.
is received data in units of characters from the line adapter 1, and when this data is sent to the data processing device 3 and configured on the communication side 5, the processing time for that received character is temporarily reduced. It can be long.

Even in such a case, an in-fist first-out shift memory (hereinafter referred to as "rFI70 memory") is provided to prevent the received data from overflowing (to ensure normal reception).

However, in the conventional system using FIFO memory, as shown in Fig.
If a request is made to the communication control device 2 to receive received data from 1000, and FIFO memory 6 becomes full, the FIFO memory ・%96 is full, so the received data bits from the line are is lost, resulting in an overrun/error, so the reception control circuit 7 detects this overrun error and notifies the communication control device 2. Therefore, as the number of interface signals with the communication control device 2 increases, the processing of the communication control device 2 differs depending on whether or not the FIFO memory 6 is installed in the line adapter 1, and the communication control device 20 line adapter There was a drawback that the control for 1 could not be made common.

An object of the present invention is to solve the above drawbacks by configuring the URT to detect reception overrun errors even in line adapters using FIFO memory, and to control communication even when the line adapter has PIP9 memory. 1. without changing the interface between the device and the line adapter. Another object of the present invention is to provide a line adapter that does not require consideration of FIFO metrics in the processing of a communication control device.

5 This invention consists of an F, IPO memory that sequentially stores received data bits input serially from a line, and a communication control device that assembles the received data bits into a received character of a required bit length. It is equipped with a URT which transmits and receives data and performs various error checks, and a reception control circuit which controls the above PIFQ memory and the above URT, and sends data, pits, and bits received from the line to the URT via a FIFO memory. In addition, if the receiving cartridge, which was assembled just before, is not picked up by the communication control device and is in the FIFO format,
When the memory is full, K is forced to the FIFO
The content of the message is transferred to YURT and controlled.

The present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram of an adapter according to an embodiment of the present invention. In FIG. 3, each symbol corresponds to each symbol in FIG. 2, respectively. In the configuration of the external device of this embodiment, the URT 5 completes the assembly of the received data from the line into a Y character, requests the communication control device ♀ to accept the *signal character, and 1, and 71. When the FO memory 6 becomes full, a reception overrun detection circuit consisting of a packer memory provided in the URT 5 detects a reception overrun t-p based on the contents of the buffer memory. The previous communication control device 2 may be configured to display over-reception and -run indications.

With this configuration, the received data bit from the line is 1
Line adapter IK, added end. The data bits received from this line are stored in the FIFO memory 6,K in a tie synchronized with the line bit transmission rate.

Receive! , the control circuit 7 inspects the condition of the URT 5 for 1 m at a speed higher than the bit transmission speed of the line or at a tie-line, and if the URT 5 does not request the communication control device 2 to pick up the received character t-1, , the received data stored in the FIFO memory 6 is input to the vURT 5. Furthermore, when the URT 5 requests the communication control device 2 to retrieve the received character (assembly of one character is completed), K is stored in the FIFO memory 6 until the communication control device 2 retrieves the received character stored in the URT 5. Transfer from to URT5 is temporarily prohibited.

However, the URT 5 is requesting the communication control device 2 to take over the received character (from the FIFO memory 6 to the URT
5) and FIFO memory 6
When the FIFO memory 6 becomes full, the data bits received from the line are lost because there is no space in the FIFO memory 6, resulting in an over-two error.

The characteristic operation of the adapter of this embodiment is that in such a state, the received data stored in the FUFO memory 6 is forcibly transferred to the vURT 5, and the reception overrun detection circuit of the URT 5 detects an overrun error. Yes, I did a 5K.

As explained above, according to the present study, the reception control circuit
If the status of the RT and FIFO memories is checked and the reception overrun state occurs, the received data bits are forcibly transferred from the FIFO memory to the URT. There is a good effect that can be commonly controlled.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data communication system; FIG. 2 is a block diagram of a conventional line adapter. FIG. 3 is a block diagram of a line adapter according to an embodiment of the present invention. 1...Line adapter, 2...Communication control device, 3...
・Data processing device, 5...universal receiver・
'Transmitter (URT), 6...First-in first-out shift memory (FIFO memory)
, 7...reception control circuit.

Claims (1)

[Claims] (1) First-in, first-act shift memory that sequentially stores received data bits input serially from the line, and upper-level communication control that assembles the received data bits stored in this shift memory into a received character of the required bit length. A universal receiver transformer that sends and receives data to and from the device, detects tampering, and provides output to the host device, the first-in, first-out shift memory, and the universal receiver. It is equipped with a reception control circuit that controls each operation of the transmitter, and the bit transmission rate of this line, which is the basic data bit from the above line, is sequentially accumulated in the first-in, first-out, and shift mechanism. , when there is no request to take over the received data from the above communication control device,
The contents of the first act shift memory are sequentially dispersed at a timing faster than the bit transmission speed of -, input to the universal receiver (transmitter), and transmitted from the universal receiver transmitter to the transmitter. When requesting the control device to receive received data, the system is configured to temporarily stop the input of received data bits from the first-in/first-out shift memory to the universal resino (input of received data bits to the transmitter). In the line adapter [, the reception control circuit stores the received data bits from the -- in the first-in/first-out shift memory Klj and stores the first-in/first-out shift memory Klj when it is full.
When the universal receiver transmitter requests the communication control device to receive received data, the data is forcibly transferred from the first-in first-out shift memory to the universal receiver transmitter. A line adapter configured to transfer received data to.