JPS5844987B2 - Zero intersection detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a zero-crossing point detector, and more particularly to a zero-crossing point detector that prevents chattering due to noise components contained in an input signal, for example.

2. Description of the Related Art Conventionally, devices for measuring the phase of a signal, for example, have used a so-called zero-crossing point detector that detects a point where this signal crosses a certain level (threshold).

In such a zero-crossing point detector, chattering occurs due to noise components included in the input signal, causing malfunction.

Therefore, various methods have been proposed and implemented to prevent chattering caused by this noise component.

FIG. 1 is a schematic block diagram showing an example of a zero-crossing point detector as prior art of interest to the present invention.

That is, the signal applied to the input terminal 1 is applied to the voltage comparator 3 after only the noise component contained in the signal is removed by the analog low-pass filter 2 .

In this voltage comparator 3, a signal from which noise components have been removed is nullified (level discriminated) at a threshold level, and a rectangular wave signal having a rising or falling edge without chattering is outputted to an output terminal 4. Derive.

However, according to this method, the weighting when averaging the input signal is asymmetrical (temporally asymmetrical), and the tail is drawn in the past.

That is, the momentary output of the low-pass F wave device 2 is influenced by past inputs (integratively), but not by future signals.

Therefore, there was a drawback that past signals and future signals were not reflected equally in determining zero intersections.

FIG. 2 is a schematic block diagram showing another example of a zero-crossing point detector as prior art of interest to the present invention.

That is, the signal applied to the input terminal 1 is level-discriminated by the Schott circuit 5, and an output (rectangular wave) signal without chattering is obtained at the output terminal 4.

However, for this Schmitt circuit 5, a difference is made in the detection (discrimination) level between rising and falling, such as discriminating at a high level for a rising edge and discriminating at a low level for a falling edge. However, since chattering is prevented, there is a drawback that essentially accurate zero-crossing detection cannot be performed.

Therefore, the main object of the present invention is to provide a zero-crossing point detector which can prevent chattering due to noise fractionation and which can overcome the particular drawbacks mentioned above.

To summarize, the present invention is a zero-crossing point detector that detects a point where an input signal crosses a higher level. let me,
Logic “1” (or “0”) in this shift register in sequence
'') in an attempt to prevent chattering of the zero intersection signal.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention.

According to the configuration, an input signal is inputted to an input terminal 1 and applied to a voltage comparator 3.

The voltage comparator 3 has its comparison level selected at a predetermined level according to its requirements, and supplies its output signal C to the data input terminal of the flip-flop 12.

This flip-flop 12 receives the clock pulse a input to the input terminal 11 at its trigger input terminal, and outputs its output d to a shift register 1 consisting of, for example, 15 bits.
Give as input of 3.

This shift register 13 is sequentially shifted by the clock pulse a.

Outputs are derived in parallel from each bit cell of the shift register 13, and these bit parallel outputs are each inverted and provided as each input of an AND gate 14.

One input of this AND gate 14 is supplied with the inverted output d of the flip-flop 12, and its output f is supplied to a reset input terminal of a hexadecimal up-down counter 19, which will be described later.

Further, the final bit output of this shift register 13 is given to one input of an AND gate 18, which will be described later, and is also inverted by an inverter 15 and given as one input of an AND gate 17, which will be described later.

The clock pulse a further includes the AND gate 1
7 and 18 each are given as one-manpower.

The output d of the flip-flop 12 is applied to the remaining output of the AND gate 17, and the output of the inverter 16, which inverts the output d of the flip-flop 12, is applied to the output of the AND gate 18.

The output g of the AND gate 17 is given as an up-count input to the hexadecimal up-down counter 19.

Further, the output of the AND gate 18 is given as a down count input to the hexadecimal up/down counter 19.

The hexadecimal up/down counter 19 is, for example, a 4-bit up/down counter, and is capable of counting from 0 to 151.

That is, it increases every time the signal g is input, decreases every time the signal ri is input, and is reset to 0 when the signal f is input, but when the count value is between O and 7, 0", and when the count f shift is between 8 and 15, it is "1".
'' is derived as the output i.

This signal i is applied to the output terminal 4. FIG. 4 is a timing chart showing waveforms of various parts for explaining the operation of FIG. 3.

As an example, FIG.
The case where the comparison level of is changed from low to high is shown.

Now, the clock pulse a is shown in the fourth Va, and the input signal is shown in FIG.

In operation, the input signal is initially lower than the comparison level of the voltage comparator 3.

Therefore, the output C from the comparator 3 becomes a low level (Low Level 1; hereinafter referred to as "L") as shown in FIG. 4C.

Correspondingly, the output d of the flip-flop 12 also becomes "L" at this timing and is applied to the shift register 13.

At this time, since the shift register 13 is in its initial state, its bit parallel output is rLJ for all bits.
It is.

Therefore, the output f of the AND gate 14 is at a high level (H
highLevel: hereinafter "H") and is applied to the reset input of the hexadecimal up-down counter 19.

In response, this hexadecimal up-down counter 19 is reset to O.

That is, the hexadecimal up-down counter 19 at this time
The count value of “1” is stored in the 15-bit shift register 13.
” bit is not present at all.

Next, when the input signal gradually increases and exceeds the comparison level, the output C of the voltage comparator 3 becomes rHJ as shown in FIG. 4C.

Accordingly, the output d of the flip-flop 12 becomes "H" in response to the clock pulse a.

Therefore, the AND gate 14 inverts this output d (rLJ
), the output f becomes rLJ, and the reset of the hexadecimal up-down counter 19 is released.

Also, at this time, the final bit output e of the shift register 13 is "0", and the AND gate 17 derives the rHJ signal g corresponding to the clock pulse a, which becomes the up-count signal of the hexadecimal up-down counter 19. .

Therefore, this hexadecimal up-down counter 19 is incremented by one and becomes "1".

That is, the hexadecimal up-down counter 19 is always 15.
This indicates the number of bits that are "1" in the bit shift register 13.

Next, when the input signal moves around the comparison level and finally exceeds this comparison level, the number of bits that become "1" in the 15-bit shift register 13 changes from "7" to "8".
i.e. the hex up-down counter 1
90 At the point where the count value changes from "7" to "8", the output i of this counter 19 changes from rLJ to rHJ,
It is derived from the output terminal 4 as a zero crossing signal.

Note that -1 here, the input signal is as shown in Figure 4.
Although we have only explained the case where the comparison level crosses from low to high, when the input signal crosses the comparison level from high to low, the AN
The rHJ signal is derived from the D gate 18 and becomes the down count input of the hexadecimal up/down counter 19.

Therefore, this hexadecimal up-down counter 19 counts down, and at the point where the count value changes from "8" to "7", it changes from rHl to "L" and becomes a zero crossing signal.

As described above, according to this embodiment, the sampling result of the input signal is delayed by writing it to the shift register, so that the weighting for averaging the input signal is symmetrical, and almost all digital circuits are used. Since it can be configured with , it has excellent reproducibility and reliability.

Another advantage is that the system requirements can be easily satisfied by appropriately selecting the length of the shift register, the number of bits (and the accompanying capacity) of the up/down counter, and the clock speed.

FIG. 5 is a block diagram showing another embodiment of the invention.

In this embodiment, the number of bits that become "1" in the 15-bit shift register 13 is detected in an analog manner.

That is, each bit output of the shift register 13 is added in parallel through fixed resistors having the same resistance value, and is input to the voltage comparator 30.

This voltage comparator 30 performs level discrimination according to the added voltage of each bit of this shift register 13, and derives a zero crossing signal to the output terminal 4.

In operation, the input signal is level-discriminated by the voltage comparator 3, sampled by the flip-flop 12, and input to the shift register 13 for shifting, which is the same as in the embodiment shown in FIG.

Furthermore, the comparison level at the voltage comparator 30 is determined when the number of bits that are "1" in the 15-bit shift register 13 is "1".
7” and the number of bits that become “1” is “8”.
” is determined between the additional voltage when

Therefore, the output of the voltage comparator 30 is rLJ when the number of bits that become "1" in the 15-bit shift register 13 is O to 7.
At the point where it changes from 7 to 8, it changes from rLJ to rHJ, and at "8 to 15" it becomes rHJ.

In this way, the zero intersection detection signal is derived from the output terminal 4.

Although each fixed resistor has the same resistance value in the above-described embodiment, it is also possible to change the weighting at the time of addition by appropriately setting this resistance value.

FIG. 6 is a block diagram showing another embodiment of the invention.

In terms of construction, this embodiment is substantially similar to the embodiment of FIG. 5, except for the following points.

That is, the parallel outputs of each bit of the 15-bit shift register 13 are applied to each input of a majority logic circuit 31 having 15 signal input terminals.

The output of this majority logic circuit 31 is derived from the output terminal 4 as a zero crossing detection signal.

Regarding the dynamic rF, the majority logic circuit 31 receives the contents of each bit of the shift register 13 in parallel, and detects whether the number of bits that become "1" is "8" or more or "7" or less. As a result, "1" in the shift register 13
If the bit is "7" or less, rLJ is output, and if it is "8" or more, rHJ is output.

Although the above-described embodiments have been described with reference to the case where the input signal is an analog quantity, this can also be implemented in the same way when the input signal is originally a digital quantity, for example, the chattering of a noise, the chattering of a relay contact, etc.

Further, the present invention can be applied not only to the phase measurement of an input signal but also to the output of the demodulation section of a frequency shift type modulator/demodulator.

As described above, according to the present invention, chattering due to noise components is prevented, and since the weighting when averaging input signals is symmetrical, a zero-crossing point detector with good reproducibility can be obtained.

[Brief explanation of the drawing]

1 and 2 are schematic block diagrams illustrating a zero-crossing detector as prior art of interest to the present invention. FIG. 3 is a block diagram showing one embodiment of the present invention. FIG. 4 is a timing chart showing waveforms of various parts to explain the operation of FIG. 3. FIG. 5 is a block diagram showing another embodiment of the invention. FIG. 6 is a block diagram showing another embodiment of this valve surface. In the figures, the same reference numerals indicate the same or equivalent parts, 1 is a signal input terminal, 3 and 30 are voltage comparators, 4 is an output terminal, 11 is a clock pulse input terminal, 12 is a flip-flop, and 13 is a 15-bit shift Resinuta, 14.
17 and 1B are AND gates, 19 is a hexadecimal up/down counter, and 31 is a majority logic circuit.

Claims (1)

[Claims] 1. A zero-crossing point detector for detecting a point at which a human input signal crosses a certain level, the device comprising: level-discriminating the input signal at the certain level defined by the equation to derive a first state or a second state output; A zero-crossing point detector comprising: means for applying a clock pulse; a shift register comprising a plurality of bits and receiving the output of the level discrimination means in response to the clock pulse; and means for examining the contents of the shift register. 2. Claim 1, characterized in that the means for checking the contents of the shift register detects the number of bits in the first state for each bit of the shift register and generates a zero crossing detection signal. The zero crossing detector described. 3. The first aspect of the present invention, wherein the means for checking the contents of the shift register is an up/down counter that counts the number of bits in the first state for each bit of the shift register in response to the clock pulse. Zero crossing detector according to item 1 or 2. 4. The means for checking the contents of the shift register detects the number of bits in the first state by adding the contents of each bit of the shift register in an analog manner. Zero intersection detector according to item 2. 5. The zero-crossing point detector according to claim 1 or 2, wherein the means for checking the contents of the shift register is a majority logic circuit that receives the contents of each bit of the shift register.