JPH0528349B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is applicable to pulse signal specification measuring devices, particularly radar, ESM (Electronic Support Measures),
ECM (Electronic Counter Measures) etc.
The present invention relates to a device for measuring the specifications of a pulse signal containing noise.

[Conventional technology]

Conventional devices of this type include those shown in FIGS. 5, 6, and 7. FIG. 5 is a block diagram showing the configuration of a conventional pulse rise detection device. In the figure, 1 is an analog-to-digital conversion circuit (hereinafter abbreviated as A/D) that converts the voltage of an analog pulse signal 2 into a digital value. , 3 is A/
4 is a threshold signal detection circuit that distinguishes between signals and noise depending on whether the digital amplitude value 3 is larger than a certain level; 5 is the output of the threshold signal detection circuit 4; A signal detection signal 6 indicates that a certain signal has been detected; as the digital amplitude value 3 is input, a level calculation circuit 8 outputs a clock pulse as a storage command signal 7 every time the amplitude value changes beyond a certain level; is an amplification value storage circuit that stores the digital amplitude value 3 in response to a storage command signal 7; 9 is a pre-stored amplitude value that is the first amplification value input in the amplification value storage circuit 8; 12 is a time value that is the output of the time counter 11; 13 is a time memory circuit that stores the time value in accordance with the storage command signal 7; and 14 is an amplitude value memory when the pulse rising detection signal 15 becomes valid. This is a pulse rise time detection circuit that detects a pulse rise time based on the stored amplitude value 16 that is the output of the circuit 8 and the stored time 17 that is the output of the time storage circuit 13. It is difficult to detect the pulse rise time at the time the pulse rises. This is because even if the pulse rise point is the point in time when the pulse amplitude gradually increases and exceeds a certain level, it is impossible to predict how the pulse amplitude will change after that point. Therefore, the usual method is to detect the rising time of the pulse and calculate the rising time from the falling time, assuming that the shape of the pulse is approximately symmetrical around the peak point. This is because the falling point of the pulse is after the peak point of the pulse, and the peak point of the pulse can be easily detected. 18 is a storage circuit control signal which is the output of the pulse rise time detection circuit; 19
is the pulse rise time, 20 is the digital amplitude value 3
21 is the peak amplification value which is the output of the peak detection circuit 20. Further, 23 is a pulse fall detection circuit, and 24 is a pulse fall detection level. This detection level is 1/1 of the pulse peak amplification value.
Set it to about 2. If the peak amplification value of the pulse is expected fairly accurately, the detection level 24 can be set corresponding to the expected peak value. Further, since the pulse falling point always comes after the pulse peak value, after detecting the peak value, the falling detection level 24 can be set each time in relation to the peak value.

FIG. 6 is a circuit diagram showing the configuration of the amplitude value storage circuit 8 and the time storage circuit 13 of a conventional pulse signal specification measuring device, and the same reference numerals as in FIG. 5 indicate the same parts or the same signals, and 8a ₁ - 8a _o and 13a ₁ to 13a _o are storage elements, and 8b ₁ to 8b _o and 13b ₁ to 13b _o are tristate buffers. Further, FIG. 7 is a time chart showing the operation of the device.

The conventional pulse signal specification measuring device is constructed as described above, and when the pulse signal 2 is input to the A/D 1, a digital amplitude value 3 is obtained every time the clock pulse 10 is applied, as shown in FIG.

Before starting the calculation, the amplitude value storage circuit 8 is reset. The level calculation circuit 6 performs a calculation to subtract the current digital amplitude value 3 from the stored amplitude value 9 stored in the amplitude value storage circuit 8, and the value of the calculation result is equal to or higher than a certain level (increase level constant). Then, the amplitude value storage circuit 8 and the time storage circuit 1
3, a storage command signal 7 is output. The amplitude value storage circuit 8 and the time storage circuit 13 receive the storage command signal 7.
is input, the memory elements 8a ₁ to 8a _o-1 , 13a ₁
~13a _o-1 information is stored in storage elements 8a ₂ ~8, respectively.
a _o , 13a ₂ to 13a _o , and store the new amplitude value and time from the time counter 11 in the memory elements 8a ₁ , 1
Store each in 3a ₁ . The threshold detection circuit 4 compares whether the digital amplitude value 3 exceeds the threshold level, and if it exceeds the threshold level, it is a signal, and other noises are distinguished from noise and signals. , when a signal is detected, outputs a signal detection signal 5.
Furthermore, the peak detection circuit 20 stores the largest amplitude value using the signal detection signal 5 and the digital amplitude value 3. This operation is repeated until the pulse fall detection signal 15 becomes valid. When the signal detection signal 5 is input, the pulse falling detection circuit 23 compares the digital amplitude value 3 with the falling detection level (which is the same as the rising detection level and is 1/2 of the peak amplitude value). When the digital amplitude value 3 becomes smaller, a pulse fall detection signal 15 is output. When the pulse fall detection signal 15 is input to the pulse rise time detection circuit 14, the pulse rise time detection circuit 14 outputs the memory circuit control signal 18 to the two memory circuits 8 and 13, and the memory amplitude value 16
and memory time 17, and enter the peak amplitude value 21.
An operation is performed to subtract the stored amplitude value 16 from , and the stored time corresponding to the storage element having the amplitude value closest to the rising edge detection level is stored, and this is output as the pulse rising time 19.

[Problem that the invention seeks to solve]

Since the conventional pulse signal specification measurement device described above is configured as described above, the peak amplitude value 21 and the falling edge are detected due to noise before the input pulse signal 2 exceeds the threshold level. There is a problem in that when the amplitude value increases to a value close to the difference from the level, the time at which the amplitude value is input is mistakenly recognized as the pulse rise time, despite the noise.

The present invention has been made to solve these problems, and aims to provide a pulse signal specification measuring device that can eliminate the influence of noise on pulse rise detection and detect correct pulse rise times.

[Means for solving problems]

The pulse signal specification measuring device according to the present invention clears the previously stored amplitude value and time when the amplitude value of the input pulse signal falls before exceeding the threshold level. This is what I did. That is, when a new descending reset circuit is provided, and the digital amplitude value 3 is below the threshold level, and the current digital amplitude value is smaller than the stored amplitude value,
A reset signal is generated to reset the amplitude value storage circuit 8 and the time storage circuit 13, erasing the previous memory.

[Effect]

The pulse signal specification measuring device in this invention includes:
Even if the amplitude value of the pulse signal rises to a value close to the difference between the peak amplitude value and the falling detection level due to noise, if the amplitude value falls before exceeding the threshold, the stored amplitude value and time will be cleared. Therefore, the influence of noise on the pulse rise time can be removed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 to 21, 23, and 24 are fifth
22 indicates the same or equivalent parts as the same reference numerals in the figure, and 22 determines whether the digital amplitude value 3 has fallen before exceeding the threshold level, and sends a reset signal 25 to the amplitude value storage circuit 8 and the time storage circuit 13. and a descending reset circuit which outputs a descending storage command signal 26.

FIG. 2 shows the falling reset circuit 22 shown in FIG.
In this circuit diagram, 22a is an R-S flip-flop, 22b is a comparator, and 22c is an AND circuit.

FIG. 3 is a circuit diagram showing the configuration of the amplified value storage circuit 8 and the time storage circuit 13 shown in _FIG .
a _o , 8b ₁ ~ 8b _o , 13a ₁ ~ 13a _o , 13b ₁ ~ 13
b _o indicates the same part as the same reference numeral in Fig. 6, and 8
c and 13c are OR circuits. Also, Figure 4 shows the 7th
FIG. 3 is a time chart showing the operation of the device according to the present invention, similar to the figure.

Next, the operation of the apparatus according to the present invention will be explained. When the pulse signal 2 is input to the A/D conversion circuit 1, a digital amplitude value 3 is obtained every time a clock pulse 10 is applied, as shown in FIG. In the down reset circuit 22, the R-S flip-flop 22a, which is a signal presence/absence detection circuit, memorizes whether or not a signal is input based on the signal detection signal 5 from the threshold detection circuit 4.
Also, the previously stored amplitude value 9 from the amplitude value storage circuit 8,
The digital amplitude value 3 is compared by the comparator 22b, which is a magnitude determination circuit, and if the output of the R-S flip-flop 22a is "L" and the calculation result of the comparator 22b is that the digital amplitude value 3 is smaller, the amplitude value is stored. A reset signal 2 is applied to the circuit 8 and the time storage circuit 13.
5 and a descending memory command signal 26 are output. When the reset signal 25 is input, the two memory circuits switch to 8a ₂
Clear the memory elements of ~8a _o , 13a ₂ ~13a _o ,
By inputting the descending memory command signal 26,
The new amplitude value and time are stored in the memory elements 8a ₁ and 13a ₁ . The reset signal 25 and the down memory command signal 26 are the same signal, as is clear from FIG. 2, and the above-mentioned operations are always performed at the same time. Therefore, even if the amplitude value is stored in the amplitude value storage circuit 8 due to noise before the pulse input signal exceeds the threshold, the stored amplitude value 9
It is cleared by making the digital amplitude value 3 lower than , and the influence of noise can be removed.

If the digital amplitude value 3 exceeds the threshold level, the R-S flip-flop 2
Even if the output of 2a becomes "H" and the output of the comparator becomes "H" thereafter, the two memory circuits 8 and 13 are not cleared, and the correct amplitude value due to the input pulse signal is stored in the memory circuit. Ru. The operation when the difference obtained by subtracting the amplitude value from the digital amplitude value 3 becomes larger than the rising level and the process of detecting the pulse rising time after detecting the falling edge of the pulse are similar to the conventional apparatus shown in FIG.

Next, the effects of this invention will be explained by comparing FIG. 4 and FIG. 7. The storage result by the conventional device is the 7th
As shown in the figure, at time t ₁₃ , this time value is stored in 13a ₁ of the time storage circuit 13, its amplitude is stored in 8a ₁ of the amplitude storage circuit 8, and then the amplitude stored in 8a ₁ is changed to the amplitude When it is determined that the _amplitude value is _the peak value of However, in FIG. 4 using the device of the present invention, the memory of points t ₁ to _{t 7} is reset by the downward reset circuit 22, and the value t ₃ of the pulse rise time 19 is output by _mistake . points, t ₁₁ points, t ₁₂ points, t ₁₃
Since only the memory of the point remains, if the value stored in 8a ₁ is the peak value, the amplitude value closest to the rising detection level is the amplitude stored in 8a ₃ , and correspondingly, 13a ₃ The time value stored in is output as the pulse rise time 19.

In the above embodiment, an R-S flip-flop was used as the signal arrival storage element of the falling reset circuit, but a J-K flip-flop or other 1-bit storage element may also be used.In addition, in this embodiment, the digital amplitude value and the Although a comparator is used as a magnitude determination circuit to determine the magnitude of the stored amplitude value, the same effect can be obtained by using a subtractor. Further, in the above embodiment, the reset signal is also output to the time memory circuit, but since the pulse rise detection is performed by comparing and determining the amplitude values, there is no need to clear the time memory element.

Furthermore, in the above embodiment, the removal of the influence of noise has been described, but even when a weak pulse signal arrives before a specific pulse signal, the influence can be removed and the correct pulse rise time can be detected.

〔Effect of the invention〕

As explained above, the present invention has the effect of obtaining a low-cost and highly accurate pulse rising edge detecting device by adding a falling reset circuit consisting only of an R-S flip-flop, a comparator, and an AND circuit to the conventional pulse rising edge detecting device. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a pulse rising edge detection device showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the falling reset circuit 22 shown in FIG. 1, and FIG. Amplitude value storage circuit 8 shown in
and a fourth circuit diagram showing the configuration of the time storage circuit 13.
The figure is a time chart showing the operation of the present invention, and FIGS. 5 to 7 are diagrams showing the configuration and operation of a conventional device. 4 is a threshold signal detection circuit, 6 is a level calculation circuit, 8 is an amplitude value storage circuit, 13 is a time storage circuit, 14 is a pulse rise time detection circuit, 2
0 is a peak detection circuit, 22 is a falling reset circuit,
22a is an R-S flip-flop, 22b is a comparator, and 22c is an AND circuit. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] 1. An analog-to-digital conversion circuit that samples an input pulse signal using a clock pulse of a predetermined period and converts the amplitude value from an analog value to a digital amplitude value; a threshold signal detection circuit that detects whether or not the digital amplitude value exists and outputs a signal detection signal; a level calculation circuit that outputs a storage command signal each time the digital amplitude value changes by a predetermined level or more; an amplitude value storage circuit that sequentially stores digital amplitude values; a time storage circuit that sequentially stores time values based on the storage command signal; and a magnitude determination circuit that outputs a signal when the digital amplitude value is smaller than the previously stored amplitude value; A signal presence/absence storage circuit that inputs the signal detection circuit, stores whether or not a signal is input, and outputs a signal presence/absence output when a signal is present, ANDs the output of the comparison circuit and the signal presence/absence storage circuit to generate this signal. The presence/absence storage circuit consists of an AND circuit that outputs a reset signal and a falling storage command signal when the output is a signal presence output and the comparison circuit is not present, and if the digital amplitude value falls before exceeding the predetermined threshold level. a falling reset circuit that detects the amplitude value and clears the amplitude value storage circuit and the time storage circuit; and a peak detection circuit that detects the peak of the digital amplitude value when the digital amplitude value exceeds the predetermined threshold level. circuit, and after the peak of the digital amplitude value is detected by the peak detection circuit, when the digital amplitude value gradually decreases and becomes below a predetermined falling detection level corresponding to the peak of the digital amplitude value; a pulse falling detection circuit that detects that point and outputs a pulse falling detection signal; and the amplitude value storage circuit that outputs a storage circuit control signal when the pulse falling detection signal is input, and uses this storage circuit control signal. and the time storage circuit to read the contents of these storage circuits, and select the digital signal whose difference between the peak of the digital amplitude value and each digital amplitude value stored in the amplitude value storage circuit is closest to the falling detection level. What is claimed is: 1. A pulse signal specification measuring device comprising: a pulse rise time detection circuit which takes an amplitude value as a pulse rise digital amplitude value and determines a time when the pulse rise digital amplitude value is inputted as a pulse rise time.