JPS5844541A - Code error deciding circuit - Google Patents

Abstract

PURPOSE:To avoid producing an alarm due to a step-out which is caused when the input signal is cut off in the application mode of a power supply, resetting an FF by means of a signal disturbance detecting circuit that detects the disturbance of the digital transmission signal. CONSTITUTION:A step-out detecting circuit 12 is connected to FF7-9 within a code error deciding circuit to detect a frame step-out when the power supply is applied to the signal receiving and transmitting devices or the input signal is cut off to the signal receiving device. When the circuit 12 detects a frame step- out, the reset pulse is transmitted to the FF7-9. When these step-outs arise, the code error pulse is continuously fed to a code error deciding circuit. Thus the pulse of level 1 is fed to the FF7-9. However, the level values fed to the FF7- 9 are all reset with the reset pulse supplied from the circuit 12. As a result, no alarm is produced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sign-It error determination circuit for determining whether the number of sign errors 9 per unit time of a digital transmission signal is greater than or less than a predetermined number. ftP#4 in Fig. 41 uses the conventional code dA selection/judgment circuit.

- Figure 81 is a diagram showing the configuration of a conventional code error determination circuit. In Figure 0, l is the code #4 low pulse input terminal (
(hereinafter referred to as input terminal), s is code error stitch number counter, and is set/reset fridub 70 tabs (hereinafter referred to as 7 rip 7
0 block), 4 is a timer, 5 is a differential circuit, ・ is a slow #1 circuit, 7 to 9 are D-7 rip 7 alternating blocks (hereinafter referred to as flip 7
0 Tsub), 1otd AND gate, 11 indicates an alarm output terminal □ input terminal IK A sign error p pulse obtained by an arbitrary known sign error detection circuit is input. The counter S counts this code W4p pulse, and when the counter S exceeds a predetermined number of 5K-kyts,
At the same time, a pulse of "1" level is sent to the 7-lip flop 1, and the counter S itself resets the sensitivity of the sign error detected by the counter jK#ta.1. It is input again from input terminal l. The needle starts to forgive the 9 pulses with wrong sign. In other words, the counter 8 differentiates the pulse from the first timer by @S to create a pulse whose ll@ level is short in time, and converts it to A.
Depending on the Il@ level of the pulse delayed by the delay circuit 6, if the threshold until reset is greater than the predetermined value set in the counter S, the number of input codes gnO is greater than the predetermined value set in the counter S. Send II level pulse to 7 lip 70 tube 8. In the fritag flop 8 to which the pulse of III level is input from the counter S, the pulse t-7 of 7t"1 level is continuously input until the pulse of level 114 from delay IgJ about 6 is inputted. YK
Keep sending. In clip 70 Tsug 7, which inputs continuous @l level pulses, when it receives a 111 level pulse from the output of the differential circuit S.

Retrieve the stored level value, 170. At the same time, the level value inputted from the fritag flop 8 is stored. Also, when the differential struggle [output of 5] @1 level pulse is received by the 7 rip 70 tug 7, the 7 rip flop 8 and 9 will also be received.Therefore, the 7 rip flop 8 will change the memorized level value to 7. At the same time, the level at from the clip 70 knob 7 is stored.
Also.

In 7 rip 7a tug 9, input the memorized level value to AND gate 10 i! 1 is issued, and the level value from 7 rip 7 cost tsug 8 is stored. From each of these 7 rip 70 knobs 7 to 9 - jp I 111 input level is manually input to A7 and 10, this AND GO) 101 C input sg level 1IL [is all 111's taste, AND GO) lad- report is output. for'.

A pulse of ψ level is sent to the output signal 1 t'.However, such a conventional configuration has the following drawbacks.

That is, the conventional code error #qji! In the A-way, when the transmitting device and the receiving device used in the digital transmission system are turned on, or when the receiving device's input gIg is disconnected, the 7-frame IWIM is restored.

The purpose of this is to prevent rutting due to loss of synchronization due to input signal disconnection, etc. In the code determination circuit, the signal 1 is set to 1. It is a thing whose purpose is to do something.

The gs diagram is a diagram showing the configuration of the original 940 code determination path. This figure shows the structure of the present invention added to the 18th 7-lip links 17-9. In this figure, at i,
1m is an out-of-synchronization detection circuit.

The following is a description of the IM dog of the present invention. ・The code I @ pulse is input from the input terminal l, and the counter S counts the sign error, and the hand value is set in the counter 2 in advance. 11 when the specified number is exceeded.
“Send a pulse of level 7 vp74g aK.7
Rig 7a block 8 sends the stored level value to 7 rip 70 block 8 when the pulse of @1 level is input, and the level value from 44C7 lip flop 8 is derived. At this time, 7 rig 70 tsubu 8 memorize i
Next, the bell value is sent to 7 rip 7 o tug 9 and the FC
The level value from the ylJ gate 70 is stored. Also, the level value from the 7 lip-flop 9 is stored and sent to the friendbell at-and gate lo.

7 Rip 7 Memorize the level value from Yotsubu Hatake・ζ0%
The level values sent from the 7sy f 7 a knobs 7 to 9 are also input to the ANDGOO)10, and this ANDGOO)
When the 8110 level value input to 1G is pan @ 1m, and goo) 10IIi "l" level * @ output terminal 1
To 1? 5 and issue an e-report.

The above operation is the same as the conventional code w74] judgment circuit. However, when the 7th frame timing is off, such as when the receiving device and the transmitting device otm are sent, or when the input signal of the receiver 11IsIIIf is interrupted, etc. The following operations are performed: - In the present invention, when the power of the receiving device and the transmitting device is turned on, or when the input signal 11 of the receiving device is turned off, The out-of-synchronization detection circuit 11 detects the out-of-synchronization of the receiver and the transmitter when the receiver and the transmitter are turned on or when the receiver is turned on. 7 when input 11 is interrupted, etc.
When frame synchronization is detected
Send a reset pulse t' for 9. When synchronization occurs when the receiving and transmitting devices are powered on, or when the input signal to the receiving device is cut off, the code @Rubarus is naturally output to the code error judgment circuit. Since the input is continuous, there are 11 in the 7 lip 70 knobs 7-9 of the code #4 judgment circuit circle.
Lebel's pulse is input. However, in the flip 70 tubes 7 to 9, the glue set parameter 'V' is detected from the out-of-synchronization detection circuit.
Since the reset pulse is given priority to this reset pulse, even if the input signal error signal is 11 lbel, it will all be reset.In other words, the level input to 7 rip 20 knobs 7 to 9 will be reset. value.

Since everything is reset by the reset pulse from the out-of-synchronization detection circuit, no alarm is issued.

As is clear from the above explanation, misfire @ prevents the generation of an alarm due to a code error due to frame 1IIj being out of phase when the receiving device and transmitting device are powered on, or when the input signal to the receiving device is cut off. can do.

Furthermore, by replacing 1j) out-of-synchronization detection -wI with the time lI& for detecting the dominance of another value code, it is possible to prevent the issuing of an alarm for code IA9 due to causes other than out-of-synchronization.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional code error 9 determination circuit. FIG. 1 is a diagram showing the configuration of a code error determination circuit according to the present invention. In the figure, l is the code #A) pulse input signal, S is the code I/I
4 stitches counter, easy to set/reset 7 lips 7R
y', * is p4=r+, s is the differential 1gIwI, 6 is the delay circuit, 7 to 9 are the D-7 amplifier Qyp, I. is an AND gate, 11Fi alarm output terminal, and 11 is an out-of-sync detection circuit.

Claims (1)

[Claims] The code 1149 of the unit time of the digital transmission signal is counted, and when the counted value exceeds a predetermined number and 9 o'clock, a counter that outputs an output is placed, and the output from the counter is arranged, and the predistribution amount is shifted to the next stage. It has a predetermined number of 2 lips and 70 tubes,
In the code error detection circuit which uses the #IIHA output of the 7-lip 70-two output as an alarm output, the output of the signal disturbance detection circuit for detecting disturbance of the digital transmission signal is used.
Code auq constant circuit characterized by resetting the a7 trip 70 tube.