JPS584401A - Process controlling system - Google Patents

Abstract

PURPOSE:To facilitate the process control, by setting the estimated time for the end of process with a main processor in response to a processable flag set at a follower processor and knowing the end of process for the follower processor at said set time. CONSTITUTION:A main processor 11 checks a table 13 and at the same time checks the registers 3-6 in a prescribed order at its turn to receive the priority from an MPU13 to detect that a processable flag is set at the register 5 for example. Then the processor 11 indicates the start of process to an MPU3 and at the same time sets the estimated time for the end of process at a timer 14. The processor 11 also checks whether the timer 14 has counted the estimated time for the process end. In the same way, the registers 7-10 are checked by the processor 11 in a prescribed order respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processing control method in which a processing time is set in advance to enable multiple processing of a plurality of processes.

-In addition, the assembly process of the 11 circuits is done from each S device.
Conventionally, these devices have had their processes automated using digital computers due to their comparative capabilities.

This automation sends interrupt signals issued from various folded casings during the assembly process to the digital computer, and when the interrupt request is accepted by the computer, it issues the interrupt request and performs the necessary operations. is configured to start.

Since such interrupt means generally require complicated control,
It is too crude a means to be incorporated into a computer with relatively low processing power, such as a microcomputer. The present invention has been devised in view of these circumstances.

The purpose of the present invention is to set a predetermined time for completion of # & treatment by the main processing device in response to the treatment enable flag set in the spinal W device, and from this II-0II onward, the main processing device It is an object of the present invention to provide a K-processing control system in which there is no need to know the completion of the O-processing, and therefore, by simplifying the control, even a V icon can perform multiple control of the Australian number-O processing.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a transfer scissor system and a wire bonder holder installed in an integrated circuit assembly shop 8. It is controlled by the processing W device (hereinafter referred to as MPU) K, and the MPU executes various procedures performed by the device.
DeUvrMPU2, MPUtMpυ for processing device B2
3, the MPtJ for the transport device C is indicated by MPU4. Each of these MPUs has a processable flag display mode, for example, Regis JB, 4#5.6, and J611 7 lag display mode.

These MPUs are controlled by the main unit [11].

12 is the central part m device CPυ of the main part ring 911, 1fi,
ia is the processing fee request flag table, which is the CPU 12
They are referenced under llll1l and are used to establish priorities for each process that has been preempted as they should. Reference numeral 14 denotes a timer, which may be formed by, for example, a means for counting the number of times a program takes an OK time to complete one cycle when a counter is subtracted or added. Tie 114 will be generalized as many times as necessary for IJ & Ri.

The above-mentioned priority order in the above device configuration is as follows.

Priority Process Type 1 Sending out objects from transport device 2 Taking out objects from processing device B2 3 Taking out objects from processing device i11 4 Requesting objects from processing device 11i*flB1 5II & requesting IN of objects from processing device II2 These Each of the processing iit*request flags, which represents the priority order of the
It is configured to be set at a corresponding position on the table 13 of the main i* device 11 via the IPU.

The operation of the nine components described above will now be explained.

Assume that the above-mentioned device system starts operating and objects are being sequentially moved from conveyance device M to conveyance device C in an assembly line manner.

In this state, for example, the MPU 3 for the Jl&ll device 1 issues a processing request, and this
IK is set at a predetermined position in the table 13, that is, the processing request flag is set in the table 13, and the MPU 3
Set the &Wi enabled flag in the register @. At this time, table 13 contains not only the flags mentioned above but also 0 flags.
411107 Easy to set 4 times.

The main processing unit 11 checks the table 13-M1'
U3 is given priority, iI Karibai is returned, and each register, 4,5゜6, is checked in the prescribed order to ensure that the division enable flag is set in register 5. When it is found, the main unit m device 11 sends 4 to the MPU 3.
61111, the scheduled time of completion of the 1st O process is set in the timer 14, and the control for the other Asahi 11 is similar to that described in 9 above.

Even if such control is entered, the main processing unit 11ti timer 1
To check whether the scheduled processing completion time has arrived in 4. At this time, depending on the type of equipment from 114 companies, it may be a little before the processing is completed.
Sometimes 11 liters will come, and sometimes it will come when the process is completely completed.

On the other hand, when the device (for example, Asahi M2) completes the process, it sets a processing completion flag in Lujistar, and also provides necessary information such as the main part of the m device 11 of information indicating what number of processing device the device is. Prepare for transfer to O.

On the other hand, registers 7, 8, and 9.10 are checked in the main 46
1mm! 11 in a predetermined order.

As in the example above, in response to the fact that the above-mentioned well-worked reward completion flag is set at the arrival time of the scheduled completion time, Nanao Koshi Ilk will first pay the amount and perform the required processing. Establish completion in its control system. At this time, the process enable flag and process completion flag are reset by #I.

The above-mentioned nine operations are generated in each device O processing im*, and the processing of each device is carried out in multiple ways by the main control device 11, and these OII and operations are performed without K11l, which is equivalent to the conventional interrupt method. can be done.

The above embodiment describes the control of various devices used during the assembly process of integrated circuits, and it will be easy for those skilled in the art to understand that it can be used to control other devices.
This can be easily understood. 9, the above-mentioned scheduled time of completion is not a constant time as mentioned above, but the time of completion is
K1 so that this can be changed to an appropriate time according to changes.
It is 40 that can be achieved by 11. Alternatively, the time may be expressed as elapsed time.As is clear from the above description, the following effects can be obtained according to the present invention.

(2) The simplification of multiprocessing may be compromised.

(2) [So, for the information department m device with low processing capacity, 4,
A multiple processing function equivalent to an interrupt function can be provided.

■ Implementation of such functions can be achieved with relatively small amounts of hardware and shiftware, and is likely to be cost advantageous.

4. 11110 simple WiL light #11- is used for each KW & Il during the integrated circuit assembly process.
FIG. 2 is a diagram showing the structure of the ossification device and the massaging device.

In the figure, 1lFi royal treatment S* position, MPUI, -MPU4 is the spinal cord part 11! I position, 3...6 are processable flag display means,
7...9 are processing completion flag display means, 13 is a table, and 14 is a timer.

Patent issuer: Fujitsu Limited

Claims (1)

[Claims] 1) A process S for controlling the Asahi l of the spinal m apparatus by the main processing unit.
In the control method, in response to the processing enable flag set by the VL Asahi 1 intramedullary device, the main processing device causes the intramedullary device to start processing, and at the same time sets the expected processing completion time. Main part m apparatus and the above spinal part 1ii
Once the connection with the i-station is disconnected, check the arrival of the scheduled completion time of the above-mentioned processing by the above-mentioned main mm device.
A processing control system characterized in that the main processing unit is caused to control the slave processing unit again in response to the J611 completion 7 toggle set by the marrow part mat. 2) If there are multiple mI devices mentioned above, the medullary *a device processes the II number, a predetermined priority is given to these mI devices, and the mswJ* flag is set according to the priority order. 1111. The O processing control system as set forth in claim 1111, wherein priority is given to the slave processing device so that the required processing is performed by the slave processing device.