JPS5843946B2 - Television receiver with clock - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus in which a clock is added to a television receiver that receives a time signal multiplexed television signal in which a time signal is multiplexed with a television signal.

Traditionally, mechanical clocks using springs were the mainstream, but electronic clocks have become popular in recent years.

In particular, many watches are manufactured using commercial frequencies.

In addition, many devices combine a clock and a radio, and the radio is turned on and off using the clock's timer function.

Clocks that use these commercial frequencies have fairly high commercial frequency accuracy, so they can display time with relatively high precision.

■Claim 1: A time signal for detecting a time signal in a device for receiving a time signal multiplexed television signal in which a time signal for displaying the time at a predetermined position of the television signal is superimposed. A detection circuit and a clock device that counts and displays the time using a prescribed clock signal are provided,
A television receiver with a clock, characterized in that it is provided with means for calibrating the time of the clock device with the time detected by the time signal detection circuit. The present invention relates to a device in which a clock is added to a television receiver that receives time signal multiplexed television signals obtained by multiplexing signals.

Traditionally, mechanical clocks using springs were the mainstream, but electronic clocks have become popular in recent years.

In particular, many watches are manufactured using commercial frequencies.

In addition, many devices combine a clock and a radio, and the radio is turned on and off using the clock's timer function.

Clocks that use these commercial frequencies have fairly high commercial frequency accuracy, so they can display time with relatively high precision.

However, once the power went out, this clock could not return to the correct time even after the power was restored, and a person had to set the time.

On the other hand, as a means of obtaining accurate time, a method of inserting a time signal into the vertical blanking period of a television signal and displaying it on a cathode ray tube was proposed in the Journal of the Society of Television Engineers (1977).
This method is proposed in Vol. 25, No. 10, "Precise synchronization of time and frequency using TV double signals".

This method allows ``“ within the vertical blanking period of the television signal.
In this method, a time signal is sent by pulses of O" and "1", the time signal is extracted on the receiver side, and the time is converted into a character waveform and presented on a cathode ray tube.

According to this method, in addition to the conventional television circuit, there is also a circuit that detects and extracts the time signal sent during the vertical retrace period, a character generation circuit that converts the detected time signal into a character waveform, and a character waveform that is converted into the Eirin signal. By adding an image synthesis circuit that superimposes the images on the images, it is possible to display accurate time on the cathode ray tube.

However, with this method, the time could not be displayed on the cathode ray tube when the power was turned off and the watch was not receiving television broadcasts, so there was a constant need to turn on the watch so that it could not be used as a clock.

An object of the present invention is to eliminate the disadvantages of the clock using commercial frequencies and the disadvantages of the method using the time signal of a television signal, and to be able to return to the correct time even in the event of a power outage, and to provide a system for television broadcasting. To provide a device that can display the time even when the time is not being received.

The present invention includes a circuit that detects a time signal inserted into a television signal and a clock circuit whose clock is a commercial frequency or another frequency, and the time display of this clock circuit is
A function for detecting a time signal inserted into a television signal and calibrating using that signal is added, and these functions are added together as a clock section to a television receiver.

Specific embodiments of the present invention will be described. First, a time signal superimposed on a television signal, which is related to the present invention, will be described.

The time signal superimposed on the television signal is from March 1975.
It is not standardized at the lunar stage.

In the present invention, the above-mentioned document (Television Society Journal, 1
An example of this is the signal format described in "Precise Synchronization of Time and Frequency Using TV Signals" (1971, Vol. 25, No. 10).

FIG. 1 is a waveform diagram of a time signal superimposed on a television signal.

FIG. 1A is a waveform diagram of the 10th horizontal scanning period of the television signal.

In this waveform diagram, a indicates a horizontal synchronizing signal, and b indicates a burst signal, which is a conventional television signal.

C2d and C2e are time signals, which have signal waveforms in which the white level is logic "1" and the petestal level is logic "OJ+".

These signals c, d, and e are NRZ signals in which one bit has a time width of 0.5 μs.

C is a mark pattern, which is a 24-bit, 12 μs pulse pattern with a predetermined fixed waveform.

This 24-bit signal serves to distinguish the time signal from other signals.

d is a time display signal, and e is i Q 9 of the signal of d.
9. This is a signal obtained by inverting l"1'°.

FIG. 1 is a diagram showing bit assignments of the time display signal d of FIG. 1OGt and FIG. 1A;

The symbol f at the beginning of FIG. 1 is an HMS signal consisting of 4 bits indicating that the time display signal d is hours, minutes, and seconds.

The 4 bits of g are a signal representing 100 seconds, that is, from 0 seconds to 9 seconds.

h is 101 seconds, i is 100 minutes, j is 101 minutes, k is 10
8 o'clock and 1 are signals representing 101 o'clock.

g + h + l t J t k t ' is each composed of 4 bits and is expressed in binary coded decimal system (hereinafter referred to as BCD).
(abbreviated as ).

m is a reserved bit.

According to the above-mentioned document, a microsecond signal is also sent in addition to the hour, minute, and second signals5, but this will be omitted as it is too cumbersome to explain the present invention.

This time signal is sent at 1 second intervals.

In this signal format, the insertion position of the time signal is set to 10H, but if it is a position that does not cause interference to the television receiver,
It may be anywhere within the vertical retrace period.

FIG. 2 shows an embodiment of the present invention.

In FIG. 2, 122 is a clock section, and the remaining circuit blocks are the same as the conventional color television receiver.

100 is an antenna, 101 is a tuner, 102 is an intermediate wave amplification circuit, 103 is a video extension detection circuit, 104 is an automatic gain control circuit (hereinafter abbreviated as AGC), and 105 is an automatic frequency control circuit (hereinafter abbreviated as A, FC). ).

106 is an audio intermediate wave amplification circuit, 107 is an audio detection circuit,
108 is an audio amplification circuit, and 109 is a speaker.

110 is a video expansion amplifier circuit, 111 is a matrix circuit, 1
12 is a band amplifier circuit, 113 is a color demodulation circuit, and 114 is a color synchronization circuit.

115 is a synchronous separation circuit, 116 is a horizontal deflection circuit, 117
1 is a vertical deflection circuit, 118 is a high voltage circuit, 119 is a color cathode ray tube, and 120 is a power supply circuit for the television receiver.

121 is a commercial frequency power input terminal.

The power supply circuit 120 of the television receiver unit has a power input terminal 12
A voltage to be supplied to the entire television set is generated by a commercial frequency power source coming from 1 and distributed to each block via a signal path 123.

In FIG. 2, the destination of the signal path 123 is omitted because the circuit diagram would be complicated.

Except for the clock section 122, a description of the conventional color television receiver will be omitted.

The clock section 122 has input terminals 1, 70, 71, 72°74
and input various signals.

Input terminal 1 is a terminal to which a commercial frequency power source arrives.

Input terminal γ4 is a terminal to which a +5V DC voltage arrives.

The input terminal 70 is a terminal to which a video signal arrives via the signal path 124.

The input terminal T1 is a terminal to which a horizontal synchronizing pulse arrives via a signal path 125, and the input terminal 72 is a terminal to which a vertical synchronizing pulse arrives via a signal path 126.

SL is a power switch for the television receiver, and S2 is a power switch for the clock section 122.

Sl and 82 are independent switches.

The above is the relationship between a conventional television receiver and a clock section.

Next, the configuration and operation of the clock section shown in FIG. 2122 will be explained in more detail.

FIG. 3 is a block diagram showing the clock section 122 in FIG. 2 in more detail.

In FIG. 3, 10 is a 60750 frequency divider circuit.

11.13 is a 10 frequency divider circuit, 12 and 14 are 6 frequency divider circuits,
15 is a 24 frequency divider circuit.

1γ, 18° 19.20, 21.22 is a BCD display conversion circuit that converts the BCD signal to the main display of the numerical table, 23
24, 25, 26, 27, 28 are numeric displays.

50 is a 24-bit shift register, 5152.53
, 54, 55, 56, and 57 are 4-bit shift registers.

64 is a matching circuit, 58 is a NAND circuit, 59 is an inverter circuit, and 60 is an identification circuit.

61 is a pit clock oscillator, 62 is a clock control circuit, and 63 is a power supply circuit for the clock section.

S3 and 83' are cutoff switches for time calibration, and S4 is a frequency changeover switch for commercial frequency.

In Fig. 3, the input terminals 70, 71, 72, 74, 1 are connected to the second
This is the same terminal as shown in the figure.

Next, the operation of the clock section in FIG. 3 will be explained.

The commercial frequency power source coming from the input terminal 1 is converted by the power supply circuit 63 into various DC voltages to be supplied to each circuit, and distributed to all the clock sections via the signal path 78.

In FIG. 3, the destination of the signal path 78 is omitted to avoid cluttering the circuit diagram of FIG.

Similarly, the commercial frequency power input from the input terminal 1 is divided into 50 or 60 by the 60750 frequency dividing circuit 10.
The frequency is divided into 2 and outputs a second pulse.

Here, the 60750 frequency divider circuit 10 is configured to switch between areas where the commercial frequency is 50Hz and 60Hz using the commercial frequency changeover switch S4.
The frequency division number is changed depending on the Hz region, so that pulses are generated at exactly 1 second intervals.

Therefore, the 60750 frequency divider circuit 10 can be used as a 60750 frequency divider circuit in the 50H2 area by using the selector switch S4.
In the Hz region, the 5 Hz circuit functions as a divide-by-60 circuit.

The second pulse outputted by the 60750 frequency divider circuit is N
The signal is supplied to the 10 frequency divider circuit 11 via the AND circuit 58.

The 10 frequency divider circuit 11 and the 6 frequency divider circuit 12 constitute a 60 frequency divider circuit and count units of seconds, that is, from 00 seconds to 59 seconds.

In exactly the same way, a 60 frequency divider circuit is configured by the 10 frequency divider circuit 13 and the 6 frequency divider circuit 14, and the minute unit, 00 to 59
Count up to.

Further, the frequency dividing circuit 15 counts from 00 o'clock to 23 o'clock.

The processes counted by the frequency divider circuits on the ground 11, 12, 13, 14, and 15 are output by the parallel outputs of each frequency divider circuit.

These frequency dividing circuits are composed of counters that output BCD, so their parallel outputs are 17.18, 19, 2.
The BCD display conversion circuit for 0, 21, and 22 converts the code into a numeric display signal.

With this converted signal, 23.24, 25, 26,
The time is displayed on numeric displays 27 and 28, making it visually recognizable.

Here, the number display 23 is the 10° second digit, 24 is the 101st second digit, 25 is the 10° minute digit, 26 is the 101st minute digit, and 21 is the 10° digit.
The hour digit, 28, represents the 101 hour digit.

The operations described above are the operations of a clock using commercial frequencies.

Next, a method for displaying a time signal inserted into a television signal will be explained.

A video detection output signal arrives at the input terminal 70 via the signal path 124 shown in FIG.

The identification circuit 60 is a circuit that distinguishes the level of the film repair signal into a pulse signal of "O" and "1", and a signal path 77 has a pulse that makes the petestal a logic "0" and the white level a logic "1". A signal is output.

The pit clock oscillator 61 is an oscillator that generates a 2 ME (zo bit clock) with a width of 0.5 μS and a frequency of 2 ME (zo), which is the same as the pit clock of the time signal.

The clock control circuit 62 is a circuit that controls the phase and oscillation period of the pit clock pulse.

The phase of the pit clock pulse is adjusted to the same phase as the transmitted time signal using the time of the trailing edge of the horizontal retrace period signal.

Regarding this phase control, please refer to the literature, Television Society of Japan, Image Transmission Study Group, Document No. 9-7 "TV Multiplexed Still Image Reception □
Details are given on page 6.

The oscillation period of the pit clock is limited to the vertical retrace period.

This is to limit the time period during which the time signal is extracted to the vertical retrace period, and to prevent other signals from being erroneously extracted as the time signal.

A horizontal synchronizing pulse arrives at the input terminal 71, and the input terminal 72
The vertical sync pulse arrives.

These pulses are supplied to the clock control circuit 62,
It serves as a time reference and a gate signal for oscillating the pit clock as described above.

A 52-bit pulse whose start time is n in FIG. 1 is output from the pit clock oscillator 61 to the signal path 75.

The period is only the vertical return period of 1 m as described above.

This 52-bit pulse is the sum of 24 bits of mark pattern C in FIG. 1 and 28 bits of the time display signal excluding m.

The 52-bit pulse arriving on the signal path 75 is transmitted to the shift registers 50, 51, 52, 53, 54°55.56.5.
7 and arrives at the signal path 7T.
1'' signal to each shift register 50゜51, 52, 53
, 54, 55, 56, 57.

The shift register 50 is a shift register for detecting the mark pattern shown in FIG.
This is a shift register that detects cODE.

The shift register 50 stores a 24-bit mark pattern,
51 introduces data into each shift register in order to detect the 4-bit 0011 HMSCODE signal.

At this time, the minus number circuit 64 determines whether each bit of the shift register 50 and each bit of the shift register 51 are predetermined pulses, and if all the bits match, the signal path 76 is supplied with a logic "on" pulse. This is a circuit that outputs .

This circuit 64 has an exclusive OR circuit for each bit to be compared, and all NANs of the exclusive OR circuit for each bit.
It has a configuration of D, and is a circuit often used as a pulse pattern matching circuit.

When the matching circuit 64 outputs a matching output, it can be determined that the pulse pattern of the shift register 50, 51 is the desired time signal.

Therefore, at this time, shift registers 51, 52, 53,
54,55゜56.57, gyhz shown at the entrance in Figure 1
This means that the time display signal LtJtk,l has arrived.

Also, 100 seconds is stored in the shift register 52, and 10 seconds is stored in the shift register 53.
The time display signals of 1 second, 100 minutes at 54, 101 minutes at 55, 10 degrees at 56, and 101 o'clock at 57 are accumulated at one point in time.

The parallel outputs of these shift registers 52 to 5T are supplied to parallel inputs of a 10 frequency divider 11, a 6 frequency divider 12, a 10 frequency divider 13, a 6 frequency divider 14, a 24 frequency divider 15, and arrive at a signal path 76. Each frequency dividing circuit 11 to 15 is loaded depending on the timing of the matching pulse.

Therefore, each of the frequency dividing circuits 11 to 15 is connected to the shift register 5.
The time stored in 2 to 57 is stored separately, and the above-mentioned clock operation is similarly performed via BCD display conversion circuits 17 to 22.
The time is displayed on numerical displays 23-28.

The data contents of the shift registers 50 to 57 are updated every horizontal period within the vertical retrace period,
is loaded as a parallel input only when the -number circuit 64 detects the arrival of the time signal.

Therefore, the time signal sent at 1 second intervals is transmitted to the frequency divider circuit 1.
1 to 15 will be loaded at 1 second intervals.

In this way, the time signal inserted into the television signal is displayed on the numeric displays 23-28.

Next, the relationship between the clock operation using the commercial frequency of this clock section and the operation using the time signal will be explained.

Switches S3 and 83'' are interlocking switches.

When S3 and 83' are in position B, this clock section operates only as a commercial frequency clock.

That is, when the switch 83' is in position B, the signal path 79 is held at a potential of +5V and the TT voltage as shown in this example is maintained.
In LIC, it is at logic “H” level, so frequency divider circuit 1
1 to 15 are not loaded with parallel input.

Furthermore, when the switch S3 is in position B, the input of the inverter circuit 59 is at logic "L" and its output is at logic "Hjl".
Therefore, the NAND circuit 58 always passes the output of the 60150 frequency divider circuit and applies a second pulse to the frequency divider circuit 11.

Therefore, the clock section always performs a clock operation using the commercial frequency.

Next, when the switch S3, 83' is in position A, the clock section will display the calibrated time.

When switch 83' is in position A, the output signal of minus number circuit 64 passes through signal paths 76 and 79 to frequency divider circuits 11 to 11.
15 and loads the time signal to each frequency divider circuit.

At this time, the switch S3 is in position A, and the signal at the input terminal 74 is applied to the input of the inverter circuit 59.

As shown in FIG. 2, the input terminal 74 receives a +5V voltage supplied from the power supply 120 of the television receiver section.

In FIG. 2, when the switch S1 is turned off, that is, when the television receiver section is turned off, the input terminal 74 becomes OV, and when the television receiver section is turned on, the input terminal 74 becomes +5V.

Therefore, the input terminal 74 is an input terminal that transmits whether the television receiver section is turned on or off.

When a voltage of +5V arrives at the input terminal 14, that is, when the television receiver section is on, the input level of the inverter circuit 59 becomes H'' and its output becomes L''.

Therefore, the NAND circuit 58 has a 60,750 frequency dividing circuit 10.
cannot pass the output of

Therefore, the clock section displays accurate time based on the time signal.

With switches S3 and 83' in position A, switch 8 in FIG.
1, that is, when the television receiver section is turned off, the input terminal 74 becomes OV, and the NAND circuit 58 outputs 60150 through the inverter circuit 59.
It works to pass the output of the frequency divider circuit.

The frequency dividing circuits 11 to 15 hold a time signal when the television receiver section is on, and when the television receiver section is turned off, they count the time using the commercial frequency based on the held time. Start.

Conversely, if you turn on the television receiver from a state where it is off and counting the time using the commercial frequency, it immediately changes from counting based on the commercial frequency to displaying the time signal, and the accurate time is displayed. S will be calibrated to S.

Furthermore, even if the clock stops due to a power outage, once the power is restored, this clock section can accurately set the time using the time signal.

In FIG. 2, switch S1 and switch S2 are inverted power switches, 81 is the power switch for the television receiver section, and S2 is the power switch for the clock section.

Normally, the switch of the clock section S2 is kept on at all times, and the clock section 122 always functions as a clock even when the switch of the television receiver section is turned on and off.

Further, the switches S3 and 83' work in conjunction, and can be switched to operate at the commercial frequency all the time without being calibrated using a time signal.

To summarize the embodiment shown in Figure 3 above, the device of this embodiment is as follows:
The shift registers 50 to 57, the coincidence circuit 76, the identification circuit 60, the pit clock oscillator 61, and the clock control circuit 62 constitute a clock signal detection circuit that detects a time signal, and the frequency division circuits 11 to 15, BCD display conversion circuits 17 to 22, numeric displays 23 to 28, 60150 frequency dividing circuit 10, NAND circuit 58, and inverter circuit 5
9 constitutes a clock circuit, and this device has an added function of calibrating the time using the coincident pulse arriving at the signal path 79.

As described above, according to the present invention, it is possible to obtain a clock that can automate the time setting during a power outage in a clock using a conventional commercial frequency and can always return to the correct time.

In addition, the method of displaying the time signal on a cathode ray tube cannot be used as a clock when the television receiver is turned off, but as in the present invention, a number display 23 to 2 is added to the television receiver separately.
8, it can be used as a constant clock and can also be calibrated using a time signal, making it extremely convenient and effective to use as an accurate clock.

In addition, the method of displaying the time on a cathode ray tube may be difficult to see when receiving a TV program due to the spacing of characters, but if a separate display is provided as in the present invention, it can be mounted in a position that is easy to see and separate from the cathode ray tube. It is convenient.

In the above detailed explanation of the present invention, the signal format shown in FIG. 1 was shown as an example of a time signal to be inserted into a television signal, but the signal format shown in FIG. 1 is not necessarily required.
Similar to this, if the time signal is inserted into a television signal and transmitted, the apparatus of the present invention can be implemented using exactly the same method.

In addition, in the present invention, a clock up to one second has been described, but it is shown in the above-mentioned document (Journal of the Television Society 1) that even more accurate clocks can be realized depending on the format of the time signal.
971, No. 2541'-Precise synchronization of time and frequency with TV signals").

Further, although an example in which a numeric display is used as a time display has been shown as an embodiment of the present invention, a mechanical time display or a time display using hands may be used.

In the present invention, a commercial frequency is used as the clock for the clock, but if even more precise time is required, the horizontal synchronization pulse built into the television receiver,
If a 3.58 MHz color synchronization signal for color subcarrier reproduction is adopted, an extremely accurate and stable clock can be obtained.

[Brief explanation of drawings]

FIG. 1A2 is a waveform diagram showing an example of a time signal inserted into a television signal, FIG. 2 is a block diagram showing an embodiment of a television receiver with a clock according to the present invention, and FIG. FIG. 3 is a block diagram showing the clock section in FIG. 2 in detail. 17-22: BCD display conversion circuit, 23-28: Numerical display, 50-57: Shift register, 64 double coincidence circuit, 58: NAND circuit, 59: Inverter circuit, 60:
Identification circuit, 61: Bit clock oscillator, 62: Clock control circuit, 63: Power supply circuit.

Claims (1)

[Claims] 1. A device for receiving a time signal multiplexed television signal in which a time signal for displaying the time at a predetermined position of the television signal is superimposed, including a time signal detection circuit for detecting the time signal; A clock device is provided that counts and displays the time based on the received clock signal,
A television receiver with a clock, characterized in that it is provided with means for calibrating the time of the clock device with the time detected by the time signal detection circuit.