JPS5843698U - digital signal storage device - Google Patents
digital signal storage deviceInfo
- Publication number
- JPS5843698U JPS5843698U JP13685581U JP13685581U JPS5843698U JP S5843698 U JPS5843698 U JP S5843698U JP 13685581 U JP13685581 U JP 13685581U JP 13685581 U JP13685581 U JP 13685581U JP S5843698 U JPS5843698 U JP S5843698U
- Authority
- JP
- Japan
- Prior art keywords
- data
- control circuit
- digital signal
- predetermined range
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Analogue/Digital Conversion (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例のブロック構成図を示す、
第２図はこの考案の第１の制御回路の第゛１実施例を示
す、第３図はこの考案の第２の制御回路の一実施例を示
す、第４図は第１の制御回路の第２実施例を示す。
１は記憶回路、３は第１の制御回路、４は第２の制御回
路、５は記憶制御回路。FIG. 1 shows a block diagram of an embodiment of this invention.
FIG. 2 shows a first embodiment of the first control circuit of this invention, FIG. 3 shows an embodiment of the second control circuit of this invention, and FIG. 4 shows the first embodiment of the first control circuit of this invention. A second example is shown. 1 is a memory circuit, 3 is a first control circuit, 4 is a second control circuit, and 5 is a memory control circuit.
Claims (1)
なディジタル信号のデータＡのうち該不正確なレベルを
除く所定範囲のレベルのディジタル信号のデータＢのみ
を記憶する記憶回路と；前記データＡのデジタル信号の
うち前記所定範囲のレベルまたは前記所定範囲の最下位
レベル以上のレベルのディジタル信号を受領したときに
制御信号を出力する第１の制御回路と；前記データＡの
デジタル信号のうち前記所定範囲の最下位レベルを越え
たレベルのディジタル信号を受領したときに制御信号を
出力する第２の制御回路と；前記第１の制御回路の制御
信号を用いて前記記憶回路に前記データＢを記憶さ讐、
かつ前記第２の制御回路の制御信号を用いて前記記憶回
路の動作を停止させたのち、 前記第１の制御回路の制御信号を用いて再び前記記憶回
路に前記データＢを記憶させるための記憶制御回路とを
備えたディジタル信号記憶装置。[Claims for Utility Model Registration] Out of data A of digital signals with irregular levels including inaccurate levels exceeding the processing capacity, only data B of digital signals with levels within a predetermined range excluding the inaccurate levels. a first control circuit that outputs a control signal when receiving a digital signal of the data A at a level within the predetermined range or a level equal to or higher than the lowest level of the predetermined range; a second control circuit that outputs a control signal when receiving a digital signal of a level exceeding the lowest level of the predetermined range among the digital signals of the data A; using the control signal of the first control circuit; storing the data B in the storage circuit;
and a memory for storing the data B in the memory circuit again using the control signal of the first control circuit after stopping the operation of the memory circuit using the control signal of the second control circuit. A digital signal storage device comprising a control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13685581U JPS5843698U (en) | 1981-09-15 | 1981-09-15 | digital signal storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13685581U JPS5843698U (en) | 1981-09-15 | 1981-09-15 | digital signal storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5843698U true JPS5843698U (en) | 1983-03-24 |
| JPS6134640Y2 JPS6134640Y2 (en) | 1986-10-08 |
Family
ID=29930163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13685581U Granted JPS5843698U (en) | 1981-09-15 | 1981-09-15 | digital signal storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5843698U (en) |
-
1981
- 1981-09-15 JP JP13685581U patent/JPS5843698U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6134640Y2 (en) | 1986-10-08 |
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