JPS5843043A - Call instruction system for data processor - Google Patents

Abstract

PURPOSE:To realize easily a reentrant subroutine, by performing automatically the evacuation of the register group, the security of a working area and the setting of a static link respectively on a stack and by means of hardwares when the subroutine is called. CONSTITUTION:The contents of a general-purpose register 3 is evacuated to a work register 5. The register 3 is shown by a static link address designating register number of an instruction which is read out by a main storage device 1. Then a program status word 4 is pushed down to a stack, and the contents of the head address of a subroutine is evacuated to a work register 6. The contents of the register 3 is pushed down to a stack in accordance with a register save pattern. The contents of a work register 9 is subtracted by an operator 10, and the contents of the register 6 and the static link address of the register 5 are pushed down to the stack. Finally the contents of the word 4 receives the addition of (1) through the operator 10, and the head address of the main body of the subroutine program is obtained for execution.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an efficient subroutine call command system in a processor.
′.

When a small routine call occurs in the data processing device, the program processing that was being executed up to that point is interrupted, the process moves to a subroutine, and then the original program is returned and the processing is resumed. Therefore, the processes necessary when switching from a program in progress to a subroutine program include a process to save restart information in order to restart the program in execution later, and a process to prepare before executing the subroutine.

The former is, for example, saving the contents of a program counter or a cash register in use, and the latter is, for example, securing a work area for use in a subroutine. Here, if a block structure is adopted as the program structure, it is also necessary to set up a static link (also called a static chain) for the latter.Static links are set up according to the conventions of the block structure. ?It is statically determined at the time of execution, and uniquely defines the reference data i or program of the program to be executed.This is the parent that is allowed to reference the data lock specific to the executed program This can be realized by linking addresses to data blocks one after another.

When subroutine i and exit are executed in the subordinate program, the hardware saves only the program status words ps and w (program counter and processor status information) at the time of interruption to the stack, and executes the subroutine from the first address. In order to start the process, all processes such as saving the register, saving the work area, and setting static link must be performed by software, and if the number of subroutine calls is large,
This has had the disadvantage that the automatic head count of the software has increased, and the time allotted for actual effective processing has been relatively reduced, resulting in a significant reduction in the processing capacity of the data processing device.

Also, depending on the stack structure, it was not possible to set static links on the stack using software, and this was accomplished using a separate control area. In this case, in order to realize program recursive calling (calling the same program multiple times), it is necessary to manage complex control networks, and the software's automatic cost increases even further. : Ni Nishi, a'It#'*f6fc
kl>, xp Ex! In a data processing device having a structure and a subroutine call instruction, a first control information field P that specifies a group of registers to be saved to the stack in a subroutine and a size of a work area on the stack used in the subroutine is specified. A second control information field is added to the current stack □ in the subroutine call instruction.

It has a third control information field for statically linking the above data block to the previous data block. The present invention has a node-ware structure that saves the contents of the entry, reply, and ri and sets a link according to the contents of the second control information field, so that efficient subroutine calls can be executed. The drawings will be described in detail below.

The drawings illustrate embodiments of the invention. FIG. 1 shows a data processing system according to the present invention, in which 1 is a main memory (MM) containing subroutine call instructions, subroutine programs, stackers, etc., and 2 is a central processor having logic specifications of 32 bits per word. In the device (OPtJ), general-purpose register 3. Program counter language (P8W)4. First work register (WRI) 5° Second work register ('wa2) 6. Decoder 7゜Memory At, Res Register (M A a ) s *Third Work Register (
WB2)9. Arithmetic unit and shifter (ALU AND 5
HIFTER) 10, Data Nonotsufaregi Urayu (D
BR) 11, Processor Nose (BUS) ST ON
g) Circuit (Pl'LM)14. Instruction interpretation execution control unit (O
TL) Contains 15.

To execute an instruction, the contents of the program counter included in the program status word 4 are set in the memory address register 8 via the processor node 12, and the contents of the address indicated by the memory address register 8 are set in the data node buffer. The command interpretation and execution control unit 15 reads the command on the first day of the month. After the instruction is executed, the program counter is incremented by 1 and indicates the storage address of the next instruction.

Reading and writing of the contents of the main memory device 1 in conjunction with the execution of an instruction is also performed by setting the target address in the memory address register 8 and via the data transfer register 11.

In addition, the stack node has been successfully implemented by allocating a part of the main memory It1 and indicating the latest address with the stack pointer (sp). In this embodiment, register R14 in the general-purpose register 3 is used as a link pointer. Writing to the stack buffer is performed by subtracting 1 from the contents of the stack pointer, setting the value in the memory address register 8', and setting write data in the data buffer register 11. For this reason, the stack is called a low address r from a high address. Conversely, reading from the stack node 7a is performed by setting the contents of the stack pointer in the memory address register 8, thereby reading the data to the data node z' buffer register 11. Thereafter, the stack pointer is incremented by one.

The operation of reading from the stack buffer is called pop-up.゛Figure 2 shows the format of the current blue routine i issuing instruction in the present invention, and 101 is the general-purpose register number (1't ), 103 is the start address of the subroutine (JP
A).

FIG. 3 shows the structure of a subroutine program. 201 is a work area size designation field r (YARN) on the stack used in the subroutine, and 202 shows details of registers to be saved on the stack in the subroutine. It is a register saver (R8P). 203
is the general term for the work area size specification field 201 and the register save button 202, and is the entry point (EP).
It is called. 204 is an instruction to return to the original program. Figure 4 shows the format of the writing register save button ξ button 202, where the bit position numbers θ to 15 are the register number R.
Corresponding to O~R1"5, the bit position number 1) star where 1 is set is the target of saving. -
゛Figure 5 is an explanatory diagram showing the state of the stack at the time of execution of a subroutine call.
I will clarify. , - Now call the subroutine using the vero procedure.

(1) In a certain static lean command, the contents of the general-purpose register 3 indicated by the register number 102 are read and saved in the first work register 5.

(2) Push down the program status word 4, which indicates the state of the currently executing program, onto the stack. After the operation is completed, the stack and pointer are shown in Figure 5, 9SPO.
The position is shown in .

(3) Read the contents of the start address 103 of the subroutine indicated by the operand address part of the instruction, set the entry numbers 203 and 4, and save it to the second work register 6. After that, the upper 16 bits of Entry Norin 203,
is saved in the third work register 9 as the working area size limit 201, and the lower 16 bits are saved as the register save button 202 in the fourth work register 13.
evacuate to. 1, (4) Fourth work register 1
3 detects the rightmost 910 pit position by the FRM circuit 14 and outputs the corresponding general-purpose register 3 through the decoder and 7.
Each register is selected. Of the selected registers,
The data is pushed down to the stack, and the RM circuit 14 converts the rightmost ♀1 to O, outputs a nonitan, and stores it again in the fourth work register 13 through the processor node 12. This operation is repeated until the corresponding register is stored. are pushed down onto the stack one after another, and the operation ends when the contents of the fourth work register 13 become all 0. At this time, the stack pointer is S in Figure 5.
The position is indicated by PI.

(5) The work area size indicated by the contents of the third work register 9 and the contents of the stack pointer are subtracted by the arithmetic unit 10. This operation brings the l stack pointer to the position indicated by sP2 in FIG. As a result, a work area corresponding to the work area size is secured in the stack.

(6) Push down the contents of the second work register 6, that is, the entry button 203, onto the stack. This operation causes the stack pointer to move to s in Figure 5.
This will be the position at p3. , entry, button 203 is required to identify the size and Resta group when subroutine processing is completed.

(7) Saving to the first work register 5.

Shush down static ring addresses to child tack.

As a result, the parent data block stack pointer of the data block used in this subroutine is 9 in Figure 5.
The position is indicated by P4.

(8) Finally, the contents of the program counter included in the program 4 are added by 1 through the arithmetic unit '10 to find the starting address of the subroutine program cursive, and the execution of the subroutine program is started.
- At this point, the subroutine calling operation by the hardware is completed, and the next step is taken over by the software.

By using the hardware mechanism described above, efficient subroutine calls can be realized.

Next, save the register group using the hardware described above 5
Is it possible to use the functions to secure mIJ and set static links? This section describes an example of a program structure with a block structure and the state of the stack.

FIG. 7 shows an example of a block structure program, in which subroutines 5UB-A, 5UB-B, and 5
Each subroutine of uBL-c and 5oB-n is shown.

' Figure 8 shows the data blocks realized on the stack and their static links when each subroutine is called in sequence. Each data block has the configuration as described above with reference to FIG.
, , A31d is the address of each deniter block.

Currently, routine 5UB-A is being executed and sub-A/-chin S is running.
The data block of UB2A is indicated by reference numeral 401 in FIG. 8, and the address A of the parent cheat block before subroutine 5OB-A is called is set in its static link setting area 405, and the address A of the parent cheat block of UB2A is set in the static link setting area 405. The size of the work area to be used and the specification of the register group that needs to be saved are set in the encoder 203 at the start address of the subroutine 5UB-B, and the subroutine 5tJB-B saves the data of the subroutine 5UB-A according to the block structure convention. Assuming that the book is linked to the block (as determined at the time of Connoril), the address AO of the data block 401 of subroutine 8UB-A (currently being executed) is set to the register number R1 of general-purpose register 3, for example,
When the subroutine call command 301 according to the present invention is executed, the operation of the supplementary hardware is displayed on the stack of FIG.
After completing the operation, data block 4 of subroutine 8UB-B
"02 is secured, and address AO of data block 401 of subroutine 5UB-A is reserved in the static link setting area.
is set.

Similarly, data block 403 of SAZORUCHI:/'5UB-0 is linked to data block 402 of subroutine 1chin 5UB-B, but subroutine 5UB-
If subroutine 5UB-D is called during execution of subroutine 0, data block 404 of subroutine 5UB-D is secured and static link setting area K
This is determined by the difference in the depth of the block structures of the a subroutine SUB-0 and SUB, and is determined by the controller ξ when the controller is executed.

By setting the static link above,
References in other data blocks can be easily made by sequentially following static links on the stack. Now, from subroutine 5UB-D, only the data and program entries in its own data block 404 and subroutine 5UB-person's data block 401 can be referenced, and subroutine 5IJB-B, subroutine 5UB
-C! Program structure that does not interfere with melting (block structure)
The static link (is something that is managed and set by the program that calls the subroutine.If the subroutine call instruction according to the present invention is not used, the stack position shown in this embodiment (shown in Figure 5) is It is impossible to set a static link value to 8P4) considering the stack extension direction.

As explained above, in the present invention, when calling a subroutine,
Saving the register group, securing the work area, and setting the static link are automatically performed by software (including firmware) on the stack, resulting in the following advantages.

(1) By automatically securing a save area and a work area for register groups on the stack, 1. A reentrant subroutine can be easily realized.

Here, the reentrancy of a subroutine means that while one user is executing the subroutine, another user can start executing the same subroutine. It is useful in

(2) Setting up static links on the stack.

Therefore, a referable parent data block can be accessed simply by sequentially following static links, so a program with a block structure that allows recursive calling of subroutines can be easily realized.

(3) The above processing (saving the register group, securing the work area, and setting the static link) includes firmware/%
) Since it is performed by 4ware, it can be accelerated by using the parallel processing function of barware or firmware. As a result, efficient subroutine calling ability!
realizable. Additionally, the 8C description of software is also explained in a concise manner.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a block diagram of a data processing device, FIG. 2 is a diagram showing the format of a subroutine call command, and FIG. 3 is a diagram showing the format of a subroutine call command. The configuration diagram of the subroutine program including the entry button, Figure 4 is the Regis voice 7-B A in the entry button.
FIG. 5 is an explanatory diagram showing the state and state of the stack when a subroutine call instruction is executed, FIG. 6 is an execution sequence diagram of the present invention, and FIG. 7 is an explanatory diagram showing an example of the block structure program structure. FIG. 8 is an open diagram showing the state of data blocks on the stack and links when the subroutine in FIG. 7 is called. 1... Main memory (MM), 2... Central processing unit (
CPU), 3... General-purpose register, 4... Program status word (PF3W), 5, 6, 9, 13... 1st, 2nd. Third. 4th register (WRI, WB2゜WB2, V14), 7... Decoder, 8... Memory address register (MAR), 10-... Arithmetic unit and shifter (ALU AND 8HIFTER),
11...Body-Tough 9 Tsuhuareshita (DBI'L), 1
2...Processor nose, 14...F garlic M circuit, 1
5...Command Interpretation Execution Control Unit' ゛ Oki Electric Industry Co., Ltd. (4 others) Representative Patent Attorney 5PO - Ichigo Figure 6 311 - Figure 8 Procedural Amendment (Voluntary) June 1982 July 1st, Commissioner of the Japan Patent Office 'Shima' 1) Haruki, Display of items 1981 Patent application No. 1, Name of the invention Method of invoking command for data processing device 3 Relationship with the case of person who corrects sleeves Patent applicant's residence Location 1-7-12 Toranomon, Minato-ku, Tokyo Name (
029) Representative of Oki Electric Industry Co., Ltd. (4 others)
Nankai Hashimoto Subject of the 5th amendment "Column for brief explanation of drawings in the specification" Contents of the 6th amendment (1) Between "each" and "shi" on page 18, line 16 of the specification K "work" ” to join. (2) In the figures, Figures 3 and 8 will be corrected as shown in the attached sheet.

Claims (1)

[Claims] In a data processing device having a stack mechanism and a subroutine call instruction, the first control information field specifies a group of registers to be saved to the stack in the subroutine, and the second control information field specifies the size of a work area on the stack used in the subroutine. A data processing device having a control information field, and having a mechanism for setting and flooring a work area on a stack according to the contents of the first control information field /l/)' at the time of full execution. Call command method. −