JPH01217635A - Register saving system - Google Patents

Register saving system

Info

Publication number
JPH01217635A
JPH01217635A JP63043793A JP4379388A JPH01217635A JP H01217635 A JPH01217635 A JP H01217635A JP 63043793 A JP63043793 A JP 63043793A JP 4379388 A JP4379388 A JP 4379388A JP H01217635 A JPH01217635 A JP H01217635A
Authority
JP
Japan
Prior art keywords
register
task
registers
save area
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63043793A
Other languages
Japanese (ja)
Inventor
Yutaka Kawabata
川端 豊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63043793A priority Critical patent/JPH01217635A/en
Publication of JPH01217635A publication Critical patent/JPH01217635A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To ensure the quick switch of tasks by saving and restoring a register with the use of a tag bit and a saving area address register and using the bus idle time during the execution of a switched task or a procedure or every time register reference and replacement instructions are issued. CONSTITUTION:The register reference/replacement instructions are carried out after a called task is started. In this case, the present register contents are saved into a saving area pointed by a calling side saving area address register 21 as long as the tag bit of the relevant register is equal to 0. In addition, the data are read out of a saving area pointed by a called side saving area address register 22 and the register is restored. In such a way, the register is not saved nor restored at the switch of registers but the tasks are first switched. Thus the register is saved and restored by means of an idle bus during the run of the switched task or at the time point when the register is referred to and replaced in a task execution mode. As a result, the tasks are switched quickly.

Description

【発明の詳細な説明】 〔発明の概要〕 コンピュータでタスク切替えが行なわれ、または割込み
が入り、あるいは手続(サブルーチン)を呼び出したと
きのレジスタの退避方式に関し、切替えを迅速に行なう
ことができ、プログラム作成誤まりによりレジスタ内容
を喪失したりすることがないレジスタ退避方式を提供す
ることを目的とし、 タスク切替え、割込み、または手続き呼び出し時の中央
処理装置のレジスタのデータ退避、復元方式において各
レジスタにタグビットを設け、また呼び出し側退避域ア
ドレスレジスタと呼ばれ側退避域アドレスレジスタを設
け、これらのタグビット及び退避域アドレスレジスタを
用いてレジスタ退避、復元を、切換ねったタスクまたは
手続きの実行中にバス空き時間を利用して、またレジス
タ参照、更新命令が出たときにその都度、行なう構成と
する。
[Detailed Description of the Invention] [Summary of the Invention] Regarding a method for saving registers when tasks are switched in a computer, an interrupt occurs, or a procedure (subroutine) is called, switching can be performed quickly, The purpose is to provide a register saving method that does not cause register contents to be lost due to programming errors. A tag bit is provided for the caller, and a save area address register called the caller save area address register is provided, and these tag bits and the save area address register are used to save and restore registers, and execute the task or procedure that was switched. The structure is such that the register reference and update commands are performed each time a register reference or update command is issued, using bus free time during the process.

〔産業上の利用分野〕[Industrial application field]

本発明は、コンピュータでタスク切替えが行なわれ、ま
たは割込みが入り、あるいは手続(サブルーチン)を呼
び出したときのレジスタの退避方式に関する。
The present invention relates to a method for saving registers when a computer switches tasks, receives an interrupt, or calls a procedure (subroutine).

タスク切替え、割込み、または手続き呼出し時には、前
に動作していたタスクまたは呼出し元手続きの環境を保
存するため、従来方式ではO8または呼ばれた手続きに
おいて、プログラムの責任で、機械語命令によって、全
レジスタの退!/復元をしなければならない。
At the time of task switching, interrupt, or procedure call, in order to preserve the environment of the previously running task or calling procedure, in the conventional method, O8 or the called procedure is the program's responsibility to execute all operations using machine language instructions. Retirement of the register! / Must be restored.

〔従来の技術〕[Conventional technology]

第5図〜第7図にレジスタの退避、復元の要領を示す。 5 to 7 show the procedure for saving and restoring registers.

第5図はタスク切替時のそれで、タスクA実行中にタス
クBへの切替え事象が発生するとOS (Operat
ing System)は、CPUの全レジスタの内容
を読出して退避域Aへ格納し、次いで退避域Bより、退
避させてあったタスクB処理時のレジスタの内容を読出
してこれを該当レジスタへセットし、こうしてタスクB
実行環境を整えた後、タスクBに実行を措示する。
Figure 5 shows the situation when switching tasks. When a switching event to task B occurs while task A is being executed, the OS
ing System) reads the contents of all registers of the CPU and stores them in save area A, then reads the contents of the registers saved during task B processing from save area B and sets them in the corresponding register. , thus task B
After preparing the execution environment, task B is instructed to execute.

第6図は割込み時のそれで、タスクA実行中に割込みが
入るとO8は全レジスタの内容を退避域Aへ退避させ、
割込み処理終了後、全レジスタを復元し、タスクAに再
起動をかける。
Figure 6 shows an interrupt. When an interrupt occurs while task A is being executed, O8 saves the contents of all registers to save area A.
After interrupt processing is completed, all registers are restored and task A is restarted.

第7図は手続き呼び出し時のそれで、実行中の手続き八
が手続きBを呼び出すと、手続Bは全レジスタの内容を
退避域Aへ退避させ、然る後手続Bの実行に入り、その
実行完了で、退避域Aを読出して全レジスタの復元を行
ない、手続きAの実行継続へ復帰させる。
Figure 7 shows when a procedure is called. When procedure 8 in execution calls procedure B, procedure B saves the contents of all registers to save area A, then starts executing procedure B, and completes its execution. Then, the save area A is read out, all registers are restored, and the execution of procedure A is resumed.

しかしこの従来方式には次のような問題がある。However, this conventional method has the following problems.

即ち、■レジスタの退避、復元に時間がかかる。That is, (1) It takes time to save and restore registers.

これはレジスタの数の多いCPUはど著しい。レジスタ
の退避、復元に要する時間は、特に割込み処理において
は応答時間に影響するため極めて重大である。また■レ
ジスタの退避、復元がプログラムの責任でなされるため
、プログラムに誤りがあると(プログラマが退避、復元
の命令群を書き加えるのを忘れたりすると)レジスタの
内容が保証されず、自タスクまたは自手続きばかりでな
く他タスクまたは他年続きの動作まで妨害することにも
なる。
This is especially noticeable in CPUs with a large number of registers. The time required to save and restore registers is extremely important, especially in interrupt processing, as it affects response time. In addition, the program is responsible for saving and restoring registers, so if there is an error in the program (for example, if the programmer forgets to add a set of instructions for saving and restoring), the contents of the registers are not guaranteed, and the self-task Or, it may interfere not only with its own procedures but also with other tasks or operations that continue in other years.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明はか−る点を改善し、切替えを迅速に行なうこと
ができ、プログラム作成誤まりによりレジスタ内容を喪
失したりすることがないレジスタ退避方式を提供するこ
とを目的とするものである。
SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned problems and to provide a register saving method that allows rapid switching and prevents loss of register contents due to programming errors.

〔課題を解決するための手段〕[Means to solve the problem]

第1図に示すように本発明ではCPU (中央処理装置
)のレジスタ11.12.・・・・・・にタグピッ)1
1a、12a、・・・・・・を付加し、また呼び出し側
退避域アドレスレジスタ21および呼ばれ側退避域アド
レスレジスタ22を設け、これらによりレジスタの退避
、復元をCPUが自動的に行なうようにする。
As shown in FIG. 1, in the present invention, registers 11, 12.・・・・・・Tag Pi) 1
1a, 12a, . . . are added, and a calling side save area address register 21 and a called side save area address register 22 are provided so that the CPU can automatically save and restore registers. do.

〔作用〕[Effect]

CPUはタグビットIla、12a、・・・・・・およ
び退避域アドレスレジスタ21.22を用いて、次のよ
うな動作でレジスタ退避を行なう。
The CPU uses the tag bits Ila, 12a, . . . and the save area address registers 21, 22 to save the registers in the following manner.

■タスク切替え時に全レジスタのタグビットを0にクリ
アする。また退避域アドレスレジスタを更新する。即ち
、呼ばれ側退避域アドレスレジスタ22の内容を呼び出
し側退避域アドレスレジスタ21に移し、前者〈レジス
タ22)には今呼び出そうとしているタスクの退避域ア
ドレスを格納する。
■Clear the tag bits of all registers to 0 when switching tasks. Also updates the save area address register. That is, the contents of the called side save area address register 22 are transferred to the calling side save area address register 21, and the save area address of the task that is about to be called is stored in the former (register 22).

■呼び出されたタスクが起動した後、レジスタを参照/
更新する命令を実行するとき、そのレジスタのタグビッ
トを見てそれが0 (レジスタの内容は無効、未退避で
内容は呼び出し側のときのま\)ならば現在のレジスタ
内容をレジスタ21の指す退避域に退避し、更にレジス
タ22の指す退避域からデータを読出してきてレジスタ
を復元する(この復元処理は、手続き呼び出しの場合は
不要)。復元したら、レジスタのタグビットを1(レジ
スタの内容は有効、即ち更新済みでありレジスタ内容は
呼ばれ側のそれ)にセットする。
■After the called task starts, refer to the register/
When executing an instruction to update, check the tag bit of that register and if it is 0 (the contents of the register are invalid, unsaved, and the contents are the same as when they were called), the current register contents are pointed to by register 21. The data is saved to a save area, and further data is read from the save area pointed to by the register 22 and the register is restored (this restoration process is unnecessary in the case of a procedure call). Once restored, set the register's tag bit to 1 (the contents of the register are valid, ie, have been updated, and the contents of the register are those of the called party).

■上記■以前にも、呼び出されたタスクが起動したその
命令の実行と並行して、バスの空き時間を利用して自動
的に■の操作即ちタグがOのレジスタについての退避、
復元を行なう。
■Before ■ above, in parallel with the execution of the instruction started by the called task, the operation of ■, that is, the saving of the register with tag O, was performed automatically using the bus free time.
Perform restoration.

このように本発明ではタスク切替え時にレジスタ退避、
復元を行なうのではなく、先ずタスク切替を行ない、切
替ったタスクが走行中にバスの空きを利用してまた該タ
スク実行でレジスタ参照、更新があればその時点でレジ
スタ退避、復元を行なうので、タスク切替えを迅速に行
なうことができる。バス空き時間を利用してレジスタ退
避、復元が済んでしまえば、これに要する時間は表面に
現われなくなり、無いのと同じになる。
In this way, the present invention saves registers and saves registers when switching tasks.
Rather than performing restoration, the task is first switched, and while the switched task is running, the bus is used for free space, and if there is a register reference or update during the execution of the task, the register is saved and restored at that point. , task switching can be performed quickly. Once the registers are saved and restored using the bus free time, the time required for this will no longer appear on the surface and will be as if it had never existed.

また退避、復元はCPUが自動的に行なうので、プログ
ラム作成誤まりによってレジスタの退避、復元ができず
動作に支障を与えることはない。
Furthermore, since the CPU automatically performs the saving and restoring, there is no possibility that registers cannot be saved or restored due to a programming error, thereby causing a problem in operation.

〔実施例〕〔Example〕

第2図にタスク切替(または割込み、または手続き呼び
出し、を含むが、これらは適宜省略する)命令実行時の
レジスタ退避、復元に関する処理を示す。この処理では
■全レジスタのタグをOにクリアし、■呼び出し側退避
域レジスタXの内容を呼ばれ倒退避域レジスタYの内容
に切替える。タスクAをタスクBに切替える場合を例に
すると、タスクへの退避域アドレスはレジスタYに入っ
ており、上記■の処理でそれがレジスタXに移される。
FIG. 2 shows processing related to saving and restoring registers during execution of a task switching (or interrupt, or procedure call, although these are omitted as appropriate) instruction. In this process, (1) the tags of all registers are cleared to O, and (2) the contents of the calling side save area register X are switched to the contents of the called save area register Y. Taking the case of switching task A to task B as an example, the save area address for the task is in register Y, and is moved to register X in the process (2) above.

次に■レジスタYヘタスクBの退避域アドレスをセット
し、これでタスク切替時の処理は終りである。
Next, the save area address of task B is set in register Y, and this completes the task switching process.

第3図は切替ったタスクが実行中にレジスタ参照、更新
命令が出たときの、レジスタ退避、復元に関する処理を
示す。■実行対象の命令があるレジスタに対する使用(
参照/更新)命令か否がチエツクし、使用命令であれば
■そのタグは0が否かチエツクし、0なら■レジスタX
が示すアドレスへ当該レジスタの内容を退避させ、代っ
て■該しジスタへレジスタYが示すアドレスのメモリ内
容をセットし、■該しジスタのタグを1にセ・ノドする
。これでレジスタの退避、復元が完了し、当該命令の実
行に移る。
FIG. 3 shows processing related to register saving and restoring when a register referencing/updating instruction is issued while a switched task is being executed. ■Usage for the register containing the instruction to be executed (
(Reference/Update) Check whether it is an instruction, and if it is a used instruction, ■ Check whether the tag is 0, and if it is 0, ■ Register
The contents of the register are saved to the address indicated by , and instead: 1) the memory contents of the address indicated by register Y are set in the register Y, and 2 the tag of the register Y is set to 1. This completes the saving and restoring of registers, and the execution of the relevant instruction begins.

この第3図の処理はレジスタ参照/更新命令が出る毎に
、従って各レジスタ毎に行なわれる。図示しないが、バ
スに空き時間があればその時も(レジスタ退避/更新命
令が出ていなくても)各レジスタにつき逐次、退避/復
元が行なわれ、タグビットを0から1に切替える。レジ
スタ退M/更新命令でまたはバス空きを利用してが\る
処理が行なわれ、それが全レジスタに及んだとき、レジ
スタ退a/復元処理は終了である。退避、復元用アドレ
スはレジスタX、Y(第1図の21.22)にある。こ
れはレジスタ群に対する共通のものであるが、その中の
個々のレジスタに対するアドレスは、第2レジスタ、第
2レジスタ、・・・・・・などの順番を用いることで固
定的に決定される。
The process shown in FIG. 3 is performed every time a register reference/update command is issued, and therefore for each register. Although not shown, even if there is free time on the bus (even if no register save/update command has been issued), each register is sequentially saved/restored and the tag bit is switched from 0 to 1. The register save/restore process is completed when the register save M/update command or the process using the empty bus is performed and the process reaches all registers. The save and restore addresses are in registers X and Y (21.22 in FIG. 1). This is common to a group of registers, but the addresses for individual registers in the group are fixedly determined by using the order of the second register, second register, etc.

第4図はレジスタ退避/復元例を示す。レジスタは1つ
(11)のみ示すが、他のレジスタ12゜・・・・・・
1nについても同様である。(a)タスク切替前にレジ
スタ11の内容が1111、タグビットは1、レジスタ
21の内容は2222、レジスタ22の内容は2222
であったとし、タスクAが実行中でこれがタスクBに切
替わるとする。レジスタ22の内容3333はタスクA
の退避域アドレスで、メモリ30のこのアドレスに本例
では9999なるデータが入っている。
FIG. 4 shows an example of register saving/restoring. Only one register (11) is shown, but the other registers 12°...
The same applies to 1n. (a) Before task switching, the contents of register 11 are 1111, the tag bit is 1, the contents of register 21 are 2222, and the contents of register 22 are 2222.
Assume that task A is being executed and is switched to task B. The contents 3333 of register 22 are task A
In this example, data 9999 is stored at this address in the memory 30.

(blタスク切替命令実行で、レジスタ11のタグビッ
トはOにクリヤし、レジスタ21にレジスタ22の内容
−3333をセント、そしてレジスタ22にタスクBの
退避域アドレス5555をセットする。
(By executing the bl task switching instruction, the tag bit of register 11 is cleared to O, the contents of register 22 -3333 are written to register 21, and the save area address 5555 of task B is set to register 22.

(C)レジスタ使用命令実行で、レジスタ11の内容1
111はレジスタ21が示すメモリアドレス3333ヘ
スドアされ、レジスタ11へはタスクBの退避域アドレ
ス5555のメモリデータ6666がセットされ、レジ
スタ11のタグビットは1にセットされる。
(C) Content 1 of register 11 when register usage instruction is executed
111 is addressed to memory address 3333 indicated by register 21, memory data 6666 of save area address 5555 of task B is set in register 11, and the tag bit of register 11 is set to 1.

図示しないが、タスクBから更にタスクCに切替わると
きは第4図(C)を同(a)にした状態となり、次のス
テップでレジスタ11のタグビットをOにクリア、レジ
スタ21にレジスタ22の内容5555をセット、レジ
スタ22にタスクCの退避域のアドレスをセットし、レ
ジスタ使用命令実行でレジスタ11の内容6666をレ
ジスタ21が示すアドレス5555へ退避、レジスタ1
1へはレジスタ22が示すアドレスのデータをセットす
る。
Although not shown, when switching from task B to task C, the state shown in FIG. 4(C) becomes the same as that shown in FIG. Set the contents 5555 of , set the address of the save area of task C in register 22, save the contents 6666 of register 11 to address 5555 indicated by register 21 by executing the register use instruction, register 1
The data at the address indicated by the register 22 is set to 1.

手続き呼び出しではレジスタ退避はするが、復元(呼び
出された手続のレジスタデータのレジスタへのセラ日は
しないから、第2図のステップ3および第3図のステッ
プ■は不要である。
When a procedure is called, the register is saved, but it is not restored (the register data of the called procedure is saved to the register), so step 3 in FIG. 2 and step (2) in FIG. 3 are unnecessary.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明では、タスク切替え時にはレ
ジスタの退避、復元は行なわないので、切替え時間を短
縮することができる。バスの空き時間を利用してレジス
タの退避、復元をするため、最高では従来の退避、復元
命令の実行時間だけタスク切替えが速くなる。バスが空
かず、レジスタ参照/更新命令でのみレジスタ退避/復
元を行なった場合が最悪であるが、この場合でも所要時
間は従来と同じである。
As described above, in the present invention, registers are not saved or restored when switching tasks, so the switching time can be shortened. Since registers are saved and restored using free bus time, task switching becomes faster at best by the time it takes to execute the conventional save and restore instructions. The worst case is when the bus is not available and register save/restore is performed only by a register reference/update instruction, but even in this case, the required time is the same as in the conventional case.

また本発明では退避、復元はCPUが自動的に行なうた
め、プログラムの誤りによって他タスク(信子続き)に
影響を与えることがない。
Furthermore, in the present invention, since the CPU automatically performs the saving and restoring, errors in the program will not affect other tasks (continued by Nobuko).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理説明図、 第2図はタスク切替時の処理を示す流れ図、第3図はレ
ジスタ退避、復元動作を示す流れ図、第4図はレジスタ
退!/復元処理例の説明図、第5図〜第7図は従来のレ
ジスタ退避、復元の説明図で第5図はタスク切替時、第
6図は割込み時、そして第7図は手続き呼び出し時であ
る。 第1図で11.12.・・・・・・はCPUのレジスタ
、11a、12a、・・・・・・はそのタグビット、2
1は呼び出し側退避域アドレスレジスタ、22は呼ばれ
側退避域アドレスレジスタである。
Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a flowchart showing processing when switching tasks, Fig. 3 is a flowchart showing register saving and restoring operations, and Fig. 4 is register saving! /An explanatory diagram of an example of restoration processing. Figures 5 to 7 are explanatory diagrams of conventional register saving and restoration. Figure 5 is at the time of task switching, Figure 6 is at the time of interrupt, and Figure 7 is at the time of procedure call. be. 11.12 in Figure 1. . . . is the register of the CPU, 11a, 12a, . . . are its tag bits, 2
1 is a caller side save area address register, and 22 is a called side save area address register.

Claims (1)

【特許請求の範囲】 1、タスク切替え、割込み、または手続き呼び出し時の
中央処理装置のレジスタのデータ退避、復元方式におい
て 各レジスタ(11、12、……)にタグビット(11a
、12a、……)を設け、また呼び出し側退避域アドレ
スレジスタ(21)と呼ばれ側退避域アドレスレジスタ
(22)を設け、 これらのタグビット及び退避域アドレスレジスタを用い
てレジスタ退避、復元を、切換わったタスクまたは手続
きの実行中にバス空き時間を利用して、またレジスタ参
照、更新命令が出たときにその都度、行なうことを特徴
とするレジスタ退避方式。 2、タスク切替え時に全レジスタのタグビットを0にク
リアし、また呼ばれ側退避域アドレスレジスタ(22)
の内容を呼び出し側退避域アドレスレジスタ(21)へ
移し、呼ばれ側退避域アドレスレジスタへは呼ばれ側の
タスクの退避域アドレスをセットし、 呼ばれ側のタスクを実行中にレジスタ参照、更新命令が
出たとき、当該レジスタのタグビットを見てそれが0な
らば、当該レジスタの内容を呼び出し側退避域アドレス
レジスタが示すメモリアドレスへ退避し、該レジスタへ
呼ばれ側退避域レジスタが示すメモリアドレスのデータ
をセットし、該レジスタのタグビットを1にセットする
ことを特徴とする請求項1記載のレジスタ退避方式。
[Claims] 1. In the data saving and restoring method of the registers of the central processing unit during task switching, interrupts, or procedure calls, tag bits (11a
. A register saving method is characterized in that it is carried out by utilizing bus free time during the execution of a switched task or procedure, and whenever a register reference or update instruction is issued. 2. Clear the tag bits of all registers to 0 when switching tasks, and also clear the called side save area address register (22)
The contents of are moved to the caller side save area address register (21), the save area address of the called task is set in the called side save area address register, and the register is referenced and updated while the called task is being executed. When an instruction is issued, check the tag bit of the register and if it is 0, save the contents of the register to the memory address indicated by the save area address register of the caller, and save the contents of the register to the memory address indicated by the save area register of the called side. 2. The register saving method according to claim 1, wherein data of a memory address is set and a tag bit of the register is set to 1.
JP63043793A 1988-02-26 1988-02-26 Register saving system Pending JPH01217635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63043793A JPH01217635A (en) 1988-02-26 1988-02-26 Register saving system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63043793A JPH01217635A (en) 1988-02-26 1988-02-26 Register saving system

Publications (1)

Publication Number Publication Date
JPH01217635A true JPH01217635A (en) 1989-08-31

Family

ID=12673623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63043793A Pending JPH01217635A (en) 1988-02-26 1988-02-26 Register saving system

Country Status (1)

Country Link
JP (1) JPH01217635A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02284235A (en) * 1989-04-26 1990-11-21 Agency Of Ind Science & Technol Register preserving system
JP2008282105A (en) * 2007-05-08 2008-11-20 Fujitsu Microelectronics Ltd Microprocessor and register saving method
JP5433676B2 (en) * 2009-02-24 2014-03-05 パナソニック株式会社 Processor device, multi-thread processor device
JP2016087256A (en) * 2014-11-07 2016-05-23 株式会社三共 Game machine
JP2019017929A (en) * 2017-07-21 2019-02-07 株式会社三洋物産 Game machine

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02284235A (en) * 1989-04-26 1990-11-21 Agency Of Ind Science & Technol Register preserving system
JP2008282105A (en) * 2007-05-08 2008-11-20 Fujitsu Microelectronics Ltd Microprocessor and register saving method
US8484446B2 (en) 2007-05-08 2013-07-09 Fujitsu Semiconductor Limited Microprocessor saving data stored in register and register saving method
JP5433676B2 (en) * 2009-02-24 2014-03-05 パナソニック株式会社 Processor device, multi-thread processor device
US8850168B2 (en) 2009-02-24 2014-09-30 Panasonic Corporation Processor apparatus and multithread processor apparatus
JP2016087256A (en) * 2014-11-07 2016-05-23 株式会社三共 Game machine
JP2019017929A (en) * 2017-07-21 2019-02-07 株式会社三洋物産 Game machine

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