JPS584250Y2 - transient killer circuit - Google Patents

transient killer circuit

Info

Publication number
JPS584250Y2
JPS584250Y2 JP1977080354U JP8035477U JPS584250Y2 JP S584250 Y2 JPS584250 Y2 JP S584250Y2 JP 1977080354 U JP1977080354 U JP 1977080354U JP 8035477 U JP8035477 U JP 8035477U JP S584250 Y2 JPS584250 Y2 JP S584250Y2
Authority
JP
Japan
Prior art keywords
feedback
resistor
circuit
amplifier
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1977080354U
Other languages
Japanese (ja)
Other versions
JPS548348U (en
Inventor
山上攻
Original Assignee
オンキヨー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by オンキヨー株式会社 filed Critical オンキヨー株式会社
Priority to JP1977080354U priority Critical patent/JPS584250Y2/en
Publication of JPS548348U publication Critical patent/JPS548348U/ja
Application granted granted Critical
Publication of JPS584250Y2 publication Critical patent/JPS584250Y2/en
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は電源ON時のショック音を除去するための音声
増幅器におけるトランジェントキラー回路に関する。
[Detailed Description of the Invention] The present invention relates to a transient killer circuit in an audio amplifier for eliminating shock noise when the power is turned on.

従来の音声増幅器におけるトランジェントキラー回路は
、電源ON、OFF直後の一定時間音声増幅器の入力信
号ラインを短絡する方式、或は、第1図に示すように音
声増幅器1の出力側に増幅器出力と負荷(スピーカー)
とを断続するリレー2を設け、このリレー2を電源ON
直後の一定時間開放状態に保持して出力信号ラインを開
放することによって、電源ON時のショック音を除去し
、また、電源OFF直後リレー2を直ちに開放状態にし
て出力信号ラインを開放することによって、電源OFF
時のショック音を除去する方式が採用されていた。
The transient killer circuit in conventional audio amplifiers is a method that short-circuits the input signal line of the audio amplifier for a certain period of time immediately after the power is turned on and off, or a method that connects the amplifier output and the load to the output side of the audio amplifier 1 as shown in (speaker)
A relay 2 is installed to intermittent the
By keeping the output signal line open for a certain period of time immediately after, the shock noise when the power is turned on is removed, and by immediately opening the relay 2 and opening the output signal line immediately after the power is turned off. , power off
A method was adopted to eliminate the shock noise caused by the time.

本考案はこのような従来方式とは根本的に異なる新規な
、かつ極めて単純な構成のトランジェントキラー回路を
提供するものである。
The present invention provides a novel transient killer circuit that is fundamentally different from such conventional methods and has an extremely simple configuration.

本考案は、帰還量によって増幅利得が制御される負帰還
増幅器において、帰還量を電源ON。
The present invention is a negative feedback amplifier in which the amplification gain is controlled by the amount of feedback, when the feedback amount is turned on.

OFF或は給電停止直後の一定時間増大せしめることに
よって、増幅利得を著しく低下せしめて、電源ON時の
ショック音を実質的に除去する点に特徴を有する。
It is characterized in that by increasing the amplification gain for a certain period of time immediately after turning off or stopping the power supply, the amplification gain is significantly lowered and the shock noise when the power is turned on is substantially eliminated.

以下、第2図において代表的な実施例を説明する。A typical embodiment will be described below with reference to FIG.

第2図は電源ON時のショック音を除去す実施例である
FIG. 2 shows an embodiment that eliminates the shock sound when the power is turned on.

図において、3は2電源力式の周知の負帰還型の音声増
幅器で、その出力が帰還回路4を通して入力側に帰還さ
れる。
In the figure, reference numeral 3 denotes a well-known negative feedback type audio amplifier of two power supply type, the output of which is fed back to the input side through a feedback circuit 4.

即ち、増幅器3の出力端に帰還抵抗R2,R3を直列接
続し、この帰還抵抗R3の接地側端子をコンデンサ及び
スイッチイブトランジスタQ3を通して接地しうるごと
く構成すると共に、上記直列接続した帰還抵抗R2t
Raの接続点を入力差動増幅器の入力トランジスタQ1
と対をなす他方のトランジスタQ2のベースに接続して
、増幅器出力を帰還抵抗R2t Rsで分圧して入力側
に帰還する構成を有する。
That is, feedback resistors R2 and R3 are connected in series to the output terminal of the amplifier 3, and the ground terminal of the feedback resistor R3 is configured to be grounded through a capacitor and a switchable transistor Q3, and the feedback resistor R2t connected in series is
The connection point of Ra is input to the input transistor Q1 of the differential amplifier.
The amplifier output is connected to the base of the other transistor Q2 paired with the transistor Q2, and the amplifier output is divided by a feedback resistor R2tRs and fed back to the input side.

上記スイッチングトランジスタQ3のベースには、電源
回路6によって得られる十B電源が制御トランジスタQ
4を通してそのエミッタ出力として供給されるごとく、
制御トランジスタQ4のエミッタが接続され、そのコレ
クタは上記電源回路6に接続される。
The base of the switching transistor Q3 is supplied with a 10B power source obtained from the power supply circuit 6.
As provided as its emitter output through 4,
The emitter of the control transistor Q4 is connected, and its collector is connected to the power supply circuit 6.

そして、この制御トランジスタQ4のベースは、電源O
N直後の一定時間遮断状態を保持して、そのエミッタ出
力により上記スイッチングトランジスタQ3を遮断状態
に保持せしめるごとく、電源回路6に並列に接続された
比較的大きい時定数(数十秒)を有する時定数回路(充
電回路)5を構成する直列接続した抵抗R1とコンデン
サC1の接続点に接続され、このコンデンサC1の端子
電圧(充電電圧)によって制御されるように構成される
The base of this control transistor Q4 is connected to the power supply O
When the transistor Q3 is connected in parallel to the power supply circuit 6 and has a relatively large time constant (several tens of seconds) so that the switching transistor Q3 is kept in the cut-off state for a certain period of time immediately after N and its emitter output is used to keep the switching transistor Q3 in the cut-off state. It is connected to a connection point between a series-connected resistor R1 and a capacitor C1 that constitute a constant circuit (charging circuit) 5, and is configured to be controlled by the terminal voltage (charging voltage) of this capacitor C1.

即ち、スイッチングトランジスタQ3は上記時定数回路
5とこれによって制御される制御トランジスタQ4の出
力によって、電源ON直後の一定時間遮断状態を保持し
て上記帰還抵抗R3の接地側端子を開放状態に保持し、
その後導通して、上記帰還抵抗R3の接地側端子をコン
デンサ、スイッチングトランジスタQ3を通して接地す
るように制御される。
That is, the switching transistor Q3 maintains the cut-off state for a certain period of time immediately after the power is turned on by the output of the time constant circuit 5 and the control transistor Q4 controlled by the time constant circuit 5, and maintains the ground side terminal of the feedback resistor R3 in the open state. ,
Thereafter, conduction is established, and the ground terminal of the feedback resistor R3 is controlled to be grounded through the capacitor and the switching transistor Q3.

以上の構成によれば、電源スィッチ7をONにしたとき
、時定数回路5に十B電源が供給され、抵抗R1を通し
てコンデンサC1に充電されて、その端子電圧は徐々に
上昇し、従って制御トランジスタQ4のエミッタ電位も
徐々に上昇する。
According to the above configuration, when the power switch 7 is turned on, 10B power is supplied to the time constant circuit 5, and the capacitor C1 is charged through the resistor R1, and the terminal voltage thereof gradually increases. The emitter potential of Q4 also gradually increases.

そして、一定時間経過後にコンデンサC1の端子電圧が
所定の電圧に達し、それに伴って制御トランジスタ屯の
エミッタ電位も所定の電圧に達すると、その出力により
スイッチングトランジスタQ3が導通して、帰還抵抗R
3の接地側端子がコンデンサ、スイッチングトランジス
タQ3を通して接地される。
Then, after a certain period of time has elapsed, the terminal voltage of capacitor C1 reaches a predetermined voltage, and the emitter potential of control transistor TIN also reaches a predetermined voltage.
The ground side terminal of No. 3 is grounded through a capacitor and a switching transistor Q3.

即ち、電源ON直後の一定時間帰還抵抗R3の接地側端
子が開放状態に保持され、従って、増幅器3はその出力
が帰還抵抗R2のみを通して入力側に帰還されるので、
即ち帰還量が正常動作時に比べて著しく大きい(実施例
で25dBに設定)ので、増幅器3の増幅利得は一時的
に著しく低下して、電源ON時のショック音が著しく抑
圧され、実質的に無視しうる程度に除去できる。
That is, the ground terminal of the feedback resistor R3 is held open for a certain period of time immediately after the power is turned on, and the output of the amplifier 3 is fed back to the input side only through the feedback resistor R2.
In other words, since the amount of feedback is significantly larger than during normal operation (set to 25 dB in the example), the amplification gain of amplifier 3 is temporarily significantly reduced, and the shock noise when the power is turned on is significantly suppressed and is virtually ignored. It can be removed as much as possible.

そして、一定時間経過後、帰還抵抗R3の接地側端子が
コンデンサ、スイッチングトランジスタQ3を通して接
地されると、増幅器3はその出力が帰還抵抗R2t R
sによって分圧されて入力側に帰還されるので、所定の
増幅利得が得られ正常に動作する。
Then, after a certain period of time has elapsed, when the ground side terminal of the feedback resistor R3 is grounded through the capacitor and the switching transistor Q3, the output of the amplifier 3 is connected to the feedback resistor R2t R.
Since the voltage is divided by s and fed back to the input side, a predetermined amplification gain is obtained and normal operation is achieved.

以上のように、本考案は負帰還増幅器の帰還量を電源O
N直後の一定時間増大せしめることによって、増幅利得
を著しく低下せしめて、電源ON時のショック音を実質
的に除去する新規な方式のトランジェントキラー回路で
あるのみならず、帰還量を制御する帰還抵抗を切換える
のみの極めて単純な構成である実用利点を有する。
As described above, the present invention reduces the feedback amount of the negative feedback amplifier to the power supply O
Not only is this a new type of transient killer circuit that significantly reduces the amplification gain by increasing the amplitude for a certain period of time immediately after N, virtually eliminating the shock sound when the power is turned on, but it also uses a feedback resistor that controls the amount of feedback. It has the practical advantage of being an extremely simple configuration that only requires switching.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のトランジェントキシ−回路の構成を示す
図、第2図は本考案のトランジェントキラー回路の構成
を示す図である。 3は増幅器、4は帰還回路、6は電源回路、5は時定数
回路、R2t R3は帰還抵抗、Q3はスイッチングト
ランジスタ、R1は抵抗、C1はコンデンサである。
FIG. 1 is a diagram showing the configuration of a conventional transient xy circuit, and FIG. 2 is a diagram showing the configuration of the transient killer circuit of the present invention. 3 is an amplifier, 4 is a feedback circuit, 6 is a power supply circuit, 5 is a time constant circuit, R2t R3 is a feedback resistor, Q3 is a switching transistor, R1 is a resistor, and C1 is a capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 帰還量によって増幅利得が制御される負帰還増幅器にお
いて、増幅器3の出力端に帰還抵抗R2゜R3を直列に
接続し、この両帰還抵抗R2,R3の接続点からの入力
側へ帰還すると共に帰還抵抗R3の接地側端子スイッチ
ングトランジスタQ3を通して接地しうるごとく構成し
た帰還回路4と、所定の電源電圧を得る電源回路6と、
この電源回路6の供給電源を抵抗R1を通してこの抵抗
R1ヲ直列に接続したコンデンサC1に充電し、このコ
ンデンサC1の端子電圧によって上記スイッチングトラ
ンジスタQ3をON、OFF制御する時定数回路5とを
具備し、電源ON直後の一定時間上記スイツチングトラ
ンジスタQ3を遮断状態に保持し、上記帰還抵抗R3の
接地側端子を開放して、帰還量を増大せしめることによ
って増幅利得を低下せしめることを特徴とするトランジ
ェントキラー回路。
In a negative feedback amplifier in which the amplification gain is controlled by the amount of feedback, a feedback resistor R2°R3 is connected in series to the output terminal of the amplifier 3, and the feedback is fed back to the input side from the connection point of both feedback resistors R2 and R3. A feedback circuit 4 configured to be grounded through the ground side terminal of the resistor R3 and a switching transistor Q3, and a power supply circuit 6 that obtains a predetermined power supply voltage.
A time constant circuit 5 is provided, which charges the power supplied from the power supply circuit 6 through a resistor R1 to a capacitor C1 connected in series with the resistor R1, and controls the switching transistor Q3 to turn on and off based on the terminal voltage of the capacitor C1. , a transient characterized in that the switching transistor Q3 is held in a cut-off state for a certain period of time immediately after the power is turned on, and the ground side terminal of the feedback resistor R3 is opened to increase the amount of feedback, thereby reducing the amplification gain. killer circuit.
JP1977080354U 1977-06-18 1977-06-18 transient killer circuit Expired JPS584250Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1977080354U JPS584250Y2 (en) 1977-06-18 1977-06-18 transient killer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1977080354U JPS584250Y2 (en) 1977-06-18 1977-06-18 transient killer circuit

Publications (2)

Publication Number Publication Date
JPS548348U JPS548348U (en) 1979-01-19
JPS584250Y2 true JPS584250Y2 (en) 1983-01-25

Family

ID=28999173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1977080354U Expired JPS584250Y2 (en) 1977-06-18 1977-06-18 transient killer circuit

Country Status (1)

Country Link
JP (1) JPS584250Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538084Y2 (en) * 1974-12-28 1980-09-06

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4958730A (en) * 1972-10-04 1974-06-07
JPS5040917U (en) * 1973-08-16 1975-04-25
JPS5068759A (en) * 1973-10-23 1975-06-09

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4958730A (en) * 1972-10-04 1974-06-07
JPS5040917U (en) * 1973-08-16 1975-04-25
JPS5068759A (en) * 1973-10-23 1975-06-09

Also Published As

Publication number Publication date
JPS548348U (en) 1979-01-19

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