JPS5842275A - Insulation gate type field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce the resistance when ON position is given as well as to reduce power consumption for the titled resistor by a method wherein a conductor layer to be used as an ohmic contacting current circuit is provided on the surface of the high specific resistance drain region of the MOSFET whereon the high specific resistance drain region is provided on the channel side. CONSTITUTION:An n<-> type layer 2 of high specific resistance is provided on an n<+> type substrate 1, a p type region 6 is formed thereon, an n<+> type region 8 to be turned to a source region is provided in the region 6, and then a gate electrode 11 is formed on the surface 9 of the remaining p type region which will be used as a channel region through the intermediary of an insulating layer 10. Also, an n<+> type region 5 is provided on the surface of an n<-> type layer 2 as a low resistance drain region, and a conductor layer 41 is provided as an ohmic- contacting current circuit on the surface of a high specific resistance drain region 7 located between a channel region 9 and a low resistance drain region 5. As a result, the series resistance between a source and a drain is reduced by the action of a conductor layer 41, thereby enabling to cut down the power consumption of the titled transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an isolated gate field effect twister.

Conventionally, an insulated gate field effect transistor has a semiconductor substrate 5 having a structure, as shown in FIG. Then, facing into the semiconductor region 2, from the main li4 on the opposite side to the semiconductor region 1 side,
+Semiconductor region 5 is formed in an island shape, and within semiconductor region 2, from its main surface, P@ semiconductor region 6 is formed on the main surface of semiconductor region 2. is formed to form an annular region 7 surrounded by the semiconductor region 2, and on the other hand, in the conductor region 6, from N to N+ff1 (f in the figure)
The semiconductor region 8 of ll) is formed to form an annular region 9 of the semiconductor region 6 surrounded by the semiconductor region 7 on the main surface 4 side of the semiconductor region 6, and the main surface of the region 9 of the semiconductor region 6 is A conductive layer 11 is placed on the surface of @4Fu through an insulating layer 10.
A conductive layer 12 is ohmically applied to the surface of the main surface of the semiconductor region 5, and a conductive layer 15 is ohmically applied to the surface of the main surface of the semiconductor region 8. In addition, a conductive layer 1 is formed on the 11th surface of the 11m4 side of the region 14 on the opposite side to the region 9 side when viewed from the semiconductor region 8 of the semiconductor region 6.
3, a conductive layer 15 which can be extended integrally with this is attached in an ohmic manner.

The semiconductor region 5 is a drain region of lit, the semiconductor region 2 is a second drain region, the semiconductor region 6 is a channel forming region, the semiconductor region 8 is a source region, and the mounting layer 10 is a gauge insulating layer and a conductive layer. 11% 12.15 and 15 respectively gate voltage ti.

A structure having a drain electrode, a north electrode, and a pack gate electrode has been proposed. However, in the case of the insulated gate field effect transistor shown in FIG. 1, the conductive layer 13 as the source electrode and the drain electrode With the required power source connected through the load to the conductive layer 12 threshold as
Between the conductive layer 13 and the conductive layer 11 as a gauge electrode, a binary value of "1" is displayed, meaning a voltage greater than the expected value (!11 value) with the conductive layer 11 side being positive. When a control voltage is applied, a channel consisting of an N-wave layer is formed on the surface (main 1i4 surface) side of region 9 of semiconductor region 6 as a channel forming region, and therefore the conductive layer 15° north region 8. Region 9 of semiconductor region 6
Region 7 of the semiconductor region 2 as a channel formed in the drain region of the semiconductor region 2. 5. Semiconductor region as drain region of tsl. An off state is obtained in which a current path is formed by the conductive layers 1s and 12.
With the required power supply connected to the second gate through the load.

If a control voltage of "0" is applied to the conductive layers 15 and 11 in a binary representation meaning a voltage smaller than the above-mentioned threshold value, the above-mentioned channel will not be formed, and therefore the above-mentioned current path will not be formed. In this case, an on state cannot be obtained, but an off state can be obtained.

Therefore, in the case of the conventional insulated gate field effect transistor described above, the required power supply through the load is expressed as a binary value "1" between the conductive layers 15 and 12.
n supplies a current from the power source to the load through the current path described above, while the conductive layers 13 and 11
If a control voltage of rOJ is applied to the lever in the above-mentioned binary display, it functions as a switching element in that it does not supply current to the load.

However, in the case of the conventional insulated gate field effect transistor described above in FIG. A on the surface of 7 (main 11i4 even surface).

This is a current path with extremely small spread.

Therefore, in the case of the conventional insulated gate deaf field effect transistor shown in FIG. However, it also had the disadvantage of high power consumption.

Conventionally, as shown in FIG. 2, in the configuration described above in FIG.
2 is omitted, and accordingly, an island-shaped region 27 of the semiconductor region 2 surrounded by the semiconductor region 6 is formed on the main surface 4 side of the semiconductor region 2, and the semiconductor region 211 of the semiconductor region 1 and The structure of FIG. 1 is similar to that of FIG. 1, except that a conductive layer 52 is attached on the opposite surface, and the semiconductor region 1 is used as the drain region of the lit, and the conductive layer s2 is used as the drain electrode. A device having a configuration similar to that of the case has also been proposed.

By the way, in the case of the insulated gate micro-field effect transistor shown in FIG. 112, it has the same configuration as the case of FIG. Same as in Figure 1. Conductive layer 13 as source electrode; Semiconductor region 8 as source region. Channel formed in region 9 of semiconductor region 6 as channel formation region, semiconductor range 2 as second drain region
Area 27. Semiconductor region 1 as first drain region
．． An off-state Im in which a current path is formed by the conductive layer 32 as a drain electrode, and an off-state Im in which no current path is formed are obtained, so that it functions as a switching element similar to the case of FIG. It is clear that

However, in the case of the conventional insulated gate field effect transistor shown in FIG. exists opposite the surface (main 114 surface) of the region 27 of the semiconductor region 2 serving as the drain region of
Semiconductor region 6 as a channel forming region on the surface side of region 27 of semiconductor region 2 as second drain region
On the 9th side of the castle.

The surface of the region 27 has a current path portion with extremely small spread in the θ direction.

Therefore, the conventional insulated gate field effect transistor shown above in FIG. This has the disadvantage of consuming a large amount of power.

JIs diagram 1 shows a first embodiment of an insulated gate field effect transistor according to the present invention, parts corresponding to @tg are given the same reference numerals, and details 111f11 are omitted4.
In the configuration described above in FIG. 1, an annular conductive layer 41 serving as a current path is formed on the main surface 4 side of the annular region 7 of the semiconductor region 2 serving as the second drain region. G1 has the same configuration as in the case of FIG. 1, except that it is ohmicly attached without being connected to the semiconductor region 6 as the formation region and the semiconductor region 5 as the first drain region. However, in this case, the conductive layer 41 is allowed to extend 6 to a position as close as possible to the semiconductor regions 6 and 5.

The above is the configuration of an embodiment of the insulated gate field effect transistor Ill according to the present invention.

According to this configuration, it has the same configuration as the case of FIG. 1 except for the matters mentioned above, so a detailed explanation thereof will be omitted. , the conductive layer 13 as a north electrode and the conductive layer 12 as a drain electrode are connected to a required power source through a load, and a first If a control voltage of "1" is applied in a binary representation similar to the amount described above in the figure, a channel will be formed in the region 9 of the semiconductor value range 6 as a channel formation region, as described above in FIG. Ru.

Therefore, a current path is formed that includes the region 7 of the semiconductor region 2 as the second drain region, as described above in FIG. 1, and the conductive layer 1! .

Semiconductor area 8. Char y formed in region 9 of semiconductor region 6
Next, the area of area 7 of semiconductor area 2! and conductive layer 4
1 leap area 42. Conductive layer 41, conductive layer 41 in region 7
and the region 4 between the semiconductor regions 5 and the semiconductor region 5. A current path is formed by the conductive layer 12 and the conductive layer 12, and an on state is obtained by the current path such as C.Also, as described above, when a required power source is connected between the conductive layers 13 and 12 through the load, the conductive layer In this case, an OFF state in which a magnetic layer 1s and a flow path are formed cannot be obtained, but an OFF state can be obtained.

Therefore, according to the insulated gate field effect transistor according to the present invention shown in FIG.
And if a control voltage of "1" is given to the 11th cabinet in the binary display mentioned above.

Supplying current from the power supply to the load through the above-mentioned current path,
However, if a control voltage of "0" is applied between the conductive layers 13 and 11 in the binary representation described above.

It exhibits a function as a switching element of not supplying current to a load in the same manner as the conventional insulated gate hot water field effect transistor described above with reference to FIG.

However, in the HS diagram of the insulated gate field effect transistor according to the present invention, the off state is the 11th! [As described above, in addition to the current path including the region 7 of the semiconductor region 2 as the second drain region, a current path including the conductive layer 41 in contact with the surface of the region 70 is formed, The equivalent resistance of the latter current path, that is, the on-resistance, is, since the region where the conductive layer 41 of the region 7 is in direct contact with the conductive layer 41 is short-circuited by the conductive layer 41.
This is much smaller than the on-resistance of the former current path; therefore, in the above-mentioned on state, most of the current flows through the latter current path that includes the conductive layer 41.

Therefore, in the case of the insulated gate field effect transistor according to the present invention shown in FIG.
This value is significantly smaller than that in the case shown in FIG. 1, and therefore there is no need for large power consumption as in the case shown in FIG.

It has this great feature.

Next, with $1411, we can block the second embodiment of the insulated Dartaki electric boost effect transistor by the device 11, the second!
In the configuration described above for SwAE, the insulating layer 10 as the gate insulating layer extends to above the surface of the region 42 between the semiconductor region 6 of the semiconductor region 2 as the second drain region and the conductive layer 41. The structure is similar to that of FIG. 5, except that the conductive layer 11 serving as the upwardly extending gate electrode is extended.

The above is the configuration of the second embodiment of the insulated gate field effect transistor according to the present invention, and according to this configuration, it has the same configuration as the case of ls5 except for the matters mentioned above. Although a detailed explanation will be omitted, a control voltage of "1" is applied between the conductive layer 1s as the source electrode and the conductive layer 11 as the gate electrode in the same binary display as described above in Section III. As in the case of Figure S, if we give
A channel is formed on the surface side of region 9 of semiconductor region 6 as a channel forming region, and a channel is formed on the 5iii side of region 42 of semiconductor region 2 as a drain region of 2.
An accumulation layer consisting of 11 layers is formed. Therefore, a current path similar to that in the case of FIG. S is formed, and a current path including the above-mentioned accumulation layer is also formed, so that an on state is obtained. Incidentally, the accumulation layer has a smaller resistivity than the area of the region 42 where such an accumulation layer is not formed. Therefore, in the on state, it mostly flows in the current path that includes the storage layer. Further, if a control voltage of 10'' in binary representation is applied to the conductive layers 13 and 11, the above-mentioned channel will not be formed and an OFF state will be obtained.

Therefore, in the case of the embodiment ts2 of the present invention described above in FIG. 4, although it has the same function as a switching element as in the case of FIG.
The equivalent resistance between 2 and 3, that is, the on-resistance, has a smaller value than in the case of Figure 3, and therefore, it has the characteristic that it does not involve large power consumption compared to the case of Figure 3. Next, to describe the fifth embodiment of the present invention with reference to No. 5811, the same reference numerals will be omitted for the parts corresponding to those in FIG.
Although the explanation of A is omitted, in the configuration described above in FIG. ,
The structure is similar to that of the Three Kingdoms, except that the ivy is in contact with it. The conductive layer 41 may be extended until it connects to the conductive layer 12 attached to the semiconductor region 5.

The above is the configuration of the third embodiment of the present invention. According to this configuration, it is the same as the case of FIG. The fact that it has been extended to above 5.

This means that the region 43 of the semiconductor region 2 is also interconnected by the conductive layer 41.

Therefore, in the case of the third embodiment of the present invention shown in SWJ&c,
Although the same function as a switching element as in the case of the third III can be obtained, the conductive layers 13 and 1 in the on state
The on-resistance between 2 is smaller than that of IE31El,
Furthermore, this book has the great feature of consuming less power than the case shown in FIG.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
* Parts corresponding to those in Figure a are indicated with the same reference numerals 4. In the configuration described above in FIG. 4, the conductive layer 41
It has the same structure as the case of FIG. 4 except that it extends to the semiconductor region s1 as the first drain region and is in ohmic contact with the semiconductor region s1.

The above is the configuration of the fourth embodiment of the present invention.

According to such a structure, it is good except for the matters mentioned above.
The conductive layer 41 has a similar configuration as described above in the figure.
As in the case of FIG. 5, it extends to above the semiconductor region s serving as the gill drain region, so a detailed explanation thereof will be omitted.

Although the function as a switching element similar to the one shown in FIG. 4 can be obtained, the on-resistance between the conductive layers 13 and 12 in the on state is smaller than that shown in FIG. I
This has the great feature that it does not involve large power consumption compared to the case of the s4 diagram.

Next, a fifth embodiment of the present invention will be described with reference to FIG. 7. Parts corresponding to those in FIG. 3 will be given the same reference numerals and detailed explanation will be omitted. In the configuration where
The conductive layer 41 serving as the current path is composed of conductive layers 4La and 41b that are juxtaposed and connected to each other in the direction connecting the semiconductor region 6 as the channel forming region and the semiconductor region 5 as the first drain region. It has the same configuration as the wts diagram except for. However, in this case, the conductive layer 4
When 1m and 41b are on the sides of semiconductor regions 6 and 5, respectively, the conductive layer 411 has a potential barrier with the opposite side of the conductive layer 41 being positive due to the ohmic contact with the region 7 of the semiconductor region 2. The conductive layer 41b is formed of a material having a low potential barrier, if any, or a negative potential barrier is formed, and the conductive layer 41b is formed by ohmic contact with the region 7. A material in which a potential barrier is formed with the 4Ib side being negative, or even if a potential barrier is positive, the potential barrier is low,
Therefore, when a current path is formed to obtain the on-state described above in FIG.
The conductive layer 41b is configured to flow differently from the conductive layer 41@, and the mobile charged electrons are configured to easily flow from the conductive layer 41b to the region 7.

The above is the configuration of the fifth embodiment of the present invention.

According to such a configuration, the matters described above are the same as in the case of FIG.
b, and for this reason, movable charged particles can be easily transferred between the conductive layer 41 and the area 7, so that it can function as a switching element similar to the case of the 3rd layer, but the conductivity in the OFF state is The on-resistance between the conductive layers 13 and 12 is such that it suppresses fire and mold. Next, with reference to FIG. In this case, the main EI! 4th side, ll11ノ) "L'
The structure is similar to that of the case shown in FIG. 2, except for the semiconductor region 1 serving as the in-region, which is formed as a current path without being connected to the semiconductor region 6 serving as the channel-forming region. However, in this case, the conductive layer 51 extends as close as possible to the semiconductor regions 6 and 1.
It is possible to increase the thickness and depth of 0.

The above is the sixth embodiment of the present invention, and according to this configuration, it is the same as the case of FIG. 2 except for the matters mentioned above. , happy 2
As in the case shown in the figure, since a channel is formed in the region 9 of the semiconductor region 6 serving as a channel forming region, a current path similar to that described above in FIG. 2 is formed.

Conductive layer 13. Semiconductor area 8. A channel formed in the region 9 of the semiconductor region 6, a region 52.1 of the region 27 of the semiconductor region 2, and the region 9 of the conductive layer 51.
tNk 51 , semiconductor region m 2 gF) region 1112
7, the region 55 between the conductive layer 51 and the semiconductor region 1. Semiconductor area 1. A current path is formed by the conductive layer s2 and the conductive layer s2, so that an on state is obtained by these current paths. Furthermore, if a control voltage of "0" is applied between the conductive layers 1s and 11 at a value of 200,000,000, the above-mentioned channel will not be formed, and therefore an off state will be obtained. * exhibits the same function as a switching element as in the case of the stripe 21El.

However, in the case of the configuration of the sixth embodiment of the present invention shown in Fig. 8, the current path that provides the above-mentioned off state is outside the current path including the region 27 of the semiconductor region 2 similar to the case of Fig. 2. ,
A current path including the conductive layer 51 is formed and obtained, *t,
The equivalent resistance, that is, the on-resistance, of the latter current path is significantly higher than that of the former current path, since the area where the conductive layer 51 of the region contact 7 is connected is short-circuited by the conductive layer 51. It has a small on-resistance. Therefore, in the on-state described above, most of the current flows in the latter current path including the conductive layer 51.Therefore, in the case of the sixth embodiment of the present invention shown in FIG. In this state, the on-resistance between the conductive layers 13 and 32 has a much smaller value than in the case of Fig. 112, and for this reason, power consumption is greater than in the case of Fig. 2. It has the great feature that it never happens.

Next, the seventh embodiment of the present invention will be described with reference to Figure 519. Parts corresponding to those in Figure 8 will be given the same reference numerals and detailed explanations will be omitted. In configuration E,
As described above in FIG. 4, an insulating layer 10 is provided as a gate insulating layer.

extended to the surface side 1 of the region 52 between the semiconductor region 6 of the semiconductor region 2 and the conductive layer 51 as a second drain region,
Then, the conductive layer 11 as a dirt electrode extends over the extended portion.
It has the same configuration as the case shown in Fig. 11118 except that it is extended.

The above is the configuration of the seventh embodiment of the present invention.

According to such a configuration, it is IE except for the matters mentioned above.
Since this is the same as in the case of FIG. 8, a detailed explanation thereof will be omitted, but although it has Il'#lA as a switching element similar to the case of the 8th WA, the insulating layer 10 as a gate insulating layer is in the region 52. Since the conductive layer 11 as a gate electrode extends above the extended portion, the conductive layers 13 and 32 in the on state extend in the same manner as described above in Figure 4. The on-resistance between them has a smaller value than that of GSM, and therefore, it does not consume much power compared to GSM.

Next, the eighth embodiment of the present invention will be described with reference to FIG. 10. Parts corresponding to those in FIG. In the configuration where
Region 2 of semiconductor region 2 as its second drain region
The recess formed in #7 reaches into the semiconductor region 1 as the first drain region #! is formed in the recess 50.
The structure is similar to that of 1gem except that a conductive layer 51 as a current path formed on the inner surface of the semiconductor region 1 is connected to the semiconductor region 1.

The above is the embodiment of the present invention in Fig. 8. According to this configuration, it is the same as the case of Fig. 1g8 except for the matters mentioned above, so a detailed explanation thereof will be omitted. Although it has the same function as a switching element as in the case of FIG. 8, since the conductive layer 51 is connected to the semiconductor region 1#c as the first drain region, the conductive layers 13 and 52 in the on state The on-resistance between them has a smaller value than that in the case of FIG. 8, and therefore has a percentage value that does not involve large power consumption compared to the case of FIG.

To give an example, parts corresponding to those in Figure 10 are given the same reference numerals and detailed explanations are omitted, but in the configuration described above in Figure 10, the same parts as described above in Figure 9 The insulating layer 10 as a gate insulating layer is extended to the surface 1 of the region 52 of the semiconductor region 2 as the second drain region, and the conductive layer 11 as a gate electrode is extended to the top of the elongated part.
It has the same configuration as the 10th m-th case except for the following.

Is this all about the invention? The configuration of the embodiment is as follows.
According to such a configuration, except for the matters mentioned above, the first
Since it is the same as the case of Figure 0, the detailed explanation will be omitted. The conductive layer 11 is the second
conductive layers 13 and 3 in the on state.
The on-resistance between 2 and 2 has a smaller value than that in the case shown in Fig. 10, and therefore it has the great feature that it does not involve large power consumption compared to the case shown in Fig. 10. be.

The above description merely shows a few embodiments of the present invention, and various modifications and changes may be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

Figure jlII and Figure 2 are line cross-sectional views showing conventional insulated gate field effect transistors, Figures 3, 4, and 5.
Figure, 4th! IQ and FIG. 7 respectively show the first insulated gate field effect transistor according to the present invention! 112,#! 3,
Route sectional view showing the fourth and fifth embodiments, No. 8FjA
%jIt diagram, FIG.
FIG. 7 is a general cross-sectional view showing JII8 and a ninth embodiment. In the figure, 1.2.5.6 and 8 are semiconductor regions, 3 is a semiconductor substrate, 4 is a main surface, 7.9.27.42.45.52 and 53 are regions, 10 is an insulating layer, 11.12 .13.15.
52.41 and F 51 are conductive layers, and 50 is a recess. Applicant Nippon Telegraph and Telephone Public Corporation NEC Kinsha 6

Claims (1)

Claims: 1. A semiconductor region of stripe 1 as a first drain region having a first conductive wave. connected to the first semiconductor region. 1ll having a first conductivity type and having a higher resistivity than the first semiconductor region;
a second semiconductor region as a drain region of I2; Although it is not connected to the ill semiconductor region, it is connected to the second semiconductor region. and a third semiconductor region as a channel forming region having a second conductive wave opposite to the first conductive wave. Although it is not connected to the first and #I2 semiconductor regions, it is connected to the 113th semiconductor region. A semiconductor region of 4 degrees as a source region having a conductive wave of 1 degrees. The second and! of the third semiconductor region! In a true insulating silver field effect transistor, a conductive layer as a gate electrode is disposed on the surface of the region between the semiconductor regions of s4 with an insulating layer as a gate insulating layer interposed therebetween. Although the third semiconductor region is not in ohmic contact, the second semiconductor region is in ohmic contact with a region between the first and third semiconductor regions. An insulated gate field effect transistor characterized by having a wIt2 conductive layer as a current path. 2 a first semiconductor region as a first drain region having a first conductivity type; connected to the first semiconductor region. A second semiconductor region as a second drain region that has a first conductive wave and has a higher resistivity than the first semiconductor region. A semiconductor region of *S as a channel λ forming region having a second conductive wave opposite to the conductive wave of tsl, which is not connected to the first semiconductor region but is connected to the second semiconductor region. . Although it is not connected to the above-mentioned l111 and the second semiconductor region, it is connected to the above-mentioned third semiconductor region. a fourth semiconductor region as a source region having a first conductivity type; a first conductive layer serving as a gate electrode disposed on a surface of a region between the second and fourth semiconductor regions of the third semiconductor region with an insulating layer serving as a gate insulating layer interposed therebetween; (Insulating Goo) In It field effect transistor. Although not in ohmic contact with the third semiconductor region, it is brought into ohmic contact with a region between the tlL1 and the third semiconductor region of the second semiconductor region. The insulating layer has a second conductive layer as a current path,
A surface of a region between the third semiconductor region and the second conductive layer of the second semiconductor region is extended upwardly. The first conductive layer is an insulated gate type, characterized in that the first conductive layer is formed by extending an extension portion 1 of the insulating layer between the TAS semiconductor region and the second conductive layer. Field effect transistor. (v) a first semiconductor region as a first drain region having a first conductivity type; Can be connected to the semiconductor area of armpit 1. a second semiconductor region serving as a second drain region having a first conductivity type and having a higher resistivity than the first semiconductor region; Although it is not connected to the first semiconductor region, it is connected to the second semiconductor region. The semiconductor region of the building 5 as a channel forming region having a second conductivity type opposite to the conductivity type of tIXl is not connected to the above 1111 and the second semiconductor region, but is connected to the fifth semiconductor region. . a semiconductor region of IIE4 as a source region having a first conductivity region; A conductive layer 1Ii11 as a gate electrode is provided on the surface of the region between the second and fourth semiconductor regions of the third semiconductor region through an insulating layer as a gate insulating layer. In insulated gate field effect transistors. Although it is not in ohmic contact with the sixth semiconductor region, it is in ohmic contact with a region between the IE1 and third semiconductor regions of the second semiconductor region, and is in ohmic contact with the lit semiconductor region. An insulated gate field effect transistor characterized by having 112 conductive layers as current paths. 4. A semiconductor region as a first drain region having a conductivity type of ill. connected to the first semiconductor region. A second semiconductor region serving as a second drain region having a first conductivity type and having a higher resistivity than the first semiconductor region. Although it is not connected to the first semiconductor region, it is connected to the second semiconductor region. a third semiconductor region as a channel forming region having a second conductivity type opposite to the first conductivity type; It is not connected to the first and second semiconductor regions. It can also be connected to the semiconductor region II3 above. a semiconductor region II4 as a source region having a first conductivity type; #Il! of the region between the second and fourth semiconductor regions of the fifth semiconductor region! In an insulated gate electric boost effect transistor comprising a first conductive layer as a gate electrode disposed through an insulating layer as a gate insulating layer.The third semiconductor region has an ohmic contact. If not, the second semiconductor region is in ohmic contact with the region between the 1111 and the third semiconductor region, and is also in ohmic contact with the first semiconductor region. The insulating layer extends over the surface of the fifth semiconductor region of the second semiconductor region and the second conductive layer, and the first conductive layer extends over the surface of the fifth semiconductor region and the second conductive layer. an insulating goo characterized by an extended portion (1) that extends to the surface (1) of the third semiconductor region of the layer and the region between the (112) conductive layers;
mill world effect to2y dista.