JPS5841488A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a memory cell construction with decreased number of components, by utilizing a flip-flop where inverters are cross-coupled as a storage for information. CONSTITUTION:An inverter in which an MOS transistor (TR)Q1 is connected to a high resistance element R1 and an inverter in which an MOS TRQ2 is connected to a high resistance element R2, are cross-coupled to constitute a flip-flop for data storage and connected between a power supply VCC and ground. To the flip-flop like this, a transfer gate MOS TRQ0 for data write/readout is connected, and another end of the TRQ0 is connected to a data line, where the data to write is supplied and readout data from the flip-flop are loaded, and a word line is connected to the gate to select a cell.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a static RAM memory device whose information storage unit is a flip-flop in which two inverters are cross-coupled.

As shown in FIGS. 1(a) to 1(c), a typical cell structure of a static RAM has conventionally been one in which two inverters are connected in a cross-coupled manner and a flip 70 tube is used for data retention. The difference between the cell structures in Figures 1 (a) to (C) is that the load elements of the flip-flops are each composed of a high resistance element, an enhancement type MOS transistor, or a depletion type MOS transistor. The cell structure is also common in that two transfer MOS transistors are provided for loading/reading data, one for each data line for high-level signals and one for data lines for low-level signals. The integration of semiconductor circuits is actively being carried out in the world, and high integration density is particularly required for semiconductor memories.The development of circuits that not only reduce the size of the element itself but also reduce the number of constituent primes as much as possible is required. is desired.

The present invention has been made in view of the above-mentioned demands for conventional memory devices, and provides a semiconductor memory device having a memory cell structure with a reduced number of constituent elements and a signal generation circuit that can operate them reliably. It is. The present invention will be explained in detail by giving examples below.

First, the memory cell structure is shown in FIG. 2), (b), and (c) in correspondence with the types of the load elements. The following explanation will be made using FIG. 2 (Ca) corresponding to FIG. 1 (a) in which high resistance elements R1 and R2 are used as load elements.

In FIG. 2(a), an inverter in which a MOS transistor Q1 is connected to a high resistance element R1, and an inverter in which a MOS transistor Q2 is connected to a high resistance element R2 are cross-coupled to form a flip-flop for data retention. A power supply is configured and connected between the power supply vcc and ground level. A transfer gate MOS transistor Q for writing/reading data with respect to such a flip-flop. If one is connected, the transfer game)
The other end of the MOS transistor QO is connected to a data line to supply data for writing and to carry data read from a flip-flop, and its gate is connected to a word line to select a cell.

That is, in the memory cell structure of this embodiment, the data holding flip-flop is connected to the data line through one transfer gate MOS transistor QO regardless of whether the signal is a high level signal or a low level signal.

In the above cell structure, the word line is shown in FIG. 1(a).
It is difficult to write high level data to a memory cell if the same word line signal is supplied as in the conventional cell structure shown in FIG. Therefore, in the circuit of the example,
The word line signal level VW during data writing is higher than the word line signal level VR during reading <(VW> V
R) Set. Assuming that the word line signal level VR during reading is selected as the power supply Vcc, as will be easily understood from the explanation below, for example, the word line signal level VW during writing
is set to (Vcc+Vth). However, vt-h is a transfer gate MO5) transistor Q. Let the threshold voltage be .

Next, using the voltage-current characteristic diagram of FIG. 3, it will be explained that data writing and reading operations are possible with the above cell structure using the word line signals Vw and VR. Curve 1 in Figure 3 is the voltage-current characteristic at point A on the data holding flip-flop when the transfer MOS transistor QO is ignored, and the polarity of the current is from point A to MOS transistor QO.
The direction flowing into the S transistor Q1 is defined as positive. MOS that constitutes a flip-flop) register Q, ,Q
The curve 1 may change depending on the shape of the 2 and the resistance values of the resistive elements R1 and R2, but if a flip-flop is constructed, the curve 1! At the determined OA point, the potential rises as the current increases, and in the process of inverting the inverter on the side including the MOS transistor Q2 whose gate is connected to the A point, the current decreases rapidly, and once the current reaches 0. After that, since the high resistance element R1 is connected, the current flows slowly in the opposite direction, shows an extremely gradual change, and the current becomes O again at the potential Vcc.

Transfer gate MOS
By selecting the voltage-current characteristics of the transistor QO, the operating point can be changed to enable writing/reading, especially writing high level data.

Financial Strategy 2 In the circuit of Figure (a), consider the operation when reading the data of the flip-flop onto the data line.When a signal of vCC is applied to the potential of the data line and the word line signal level at the time of 0 reading, the transfer gate MO8) The transistor Qo becomes a load to point A, and the voltage-current characteristics are as shown in curve 2 in Figure 8, with a low potential side 12 and a high potential side 1.
3, the curve intersects the curve 1 at 0. As a result, in the read operation, a stable state occurs at the intersection point 12 or 13 of the curve I and the curve 2. In other words, when point A is at a low potential, the intersection 12 on the low potential side is in a stable state, and the low potential at point A of the data retention flip-flop is maintained, so there is no risk of memory data being destroyed. . Further, when point A is at a high potential, a stable state is reached at the intersection 13 on the high potential side, and the held data will not be destroyed. That is, in a read operation, by applying a potential of Vcc to the word line, both low potential and high potential data are read to the data line without being destroyed.

Next, the data write operation will be explained. In the case of a write operation, the signal level applied to the word line is higher than the signal level Vcc at the time of reading, and the transfer gate MOS transistor Qo (D threshold value vth
(Vcc+Vth), and the slope of the voltage-current characteristic curve of the transfer gate transistor QO is made steep.

First, when writing low-potential data to the 7-lip flop, if the potential of the data line is set to a low potential (VB), then the voltage-current characteristic of the transistor 7 (agate MO5) transistor QO is as shown in curve 4 at the above-mentioned low potential. It shows a change that intersects curve 1 only at a voltage 14 that is even lower than VB. Therefore, due to the low potential VB of the input data line, the flip-flop becomes stable at the intersection 14, regardless of its original state. In the end, low potential data is written to point A of the flip-flop. Further, when writing high potential data to the clip-flop, a high potential VCC is applied to the data line, and a potential of about (vcc+vth) is similarly applied to the word line. At this time, the voltage-current characteristic of the transfer gate MOS transistor QO is as shown by curve 3, where the high potential VC
It intersects curve 1 only at point C (13 in the figure). As a result, high potential data can be written to point A of the flip-flop.

That is, a transfer gate MOS transistor Q.

Each transistor and the word line signal are adjusted so that the voltage-current characteristics of the data holding flip-flop have one intersection on the low potential side and one high potential side during writing, respectively, as described above. By selecting the level, data can be written and read. It is easy to design a memory cell using MO5) transistors or the like so as to have the above-mentioned intersection points.

Next, a word line signal generation circuit for executing the above write/read operation will be explained with reference to FIGS. 4(a) and 4(b).

That is, in order to reliably perform data read/write operations using the memory cell structure described above, it is necessary to set the power supply voltage to be approximately at the power supply voltage level VCC in the read state and higher than Vcc+ in the write state.
A decoder drive circuit that generates a word line signal having a potential of approximately Vth is required.

In FIG. 4(a), a MOS transistor 22 is connected to an input end 20 through an inverter 21, and the other end of the MOS transistor 22 is connected to the gate of an enhancement MOS transistor 23. ing. One end of the enhancement MO8) transistor 23 is connected to the power supply VCC, and the other end is led out as a word line signal output terminal out. A first boosting capacitor 24 having an MO-5 structure is connected to the output terminal out, and the other electrode of the capacitor 24 is given a write signal W that is generated only during a write operation.

In addition, a driving MOS transistor 25 is connected between the other end of the enhancement MO5) transistor 23 and the ground, and its gate receives a memory cell select signal which is obtained by inverting the output signal of the innocent transistor 21 further with an innocent 26. is given. The memory cell select signal is branched and passed through an in/outer 27 to a second memory cell select signal made of an MO3 structure.
The other electrode of the second boosting capacitor 28, which is applied to the boosting capacitor 28 of point niha even more MO
The gate and one end of the S transistor 29 are connected, and the M
The other end of the transistor 29 is connected to the power supply VCC along with the gate of the MO3) transistor 22 and one end of the enhancement MO5) transistor 23.

In the word line signal generation circuit, when a memory cell selection signal is applied to select a memory cell during a read/write operation, the signal waveforms at each point in FIG.
34, W, based on the inverted signal 30 via the inverter 21, the VCC signal shown in the waveform 34 is applied to the output terminal out.
A read signal of the level is derived, and a write signal level VW is derived by the write signal W at the write timing during the memory cell selection period.

In the circuit of FIG. 4(a), the source φ is connected between the gate of the enhancement MOS transistor 23 and the power supply.
By inserting a MOS transistor 29 whose drain is connected and connecting the gate of the MO3I transistor 29 to the gate of the enhancement MO5 transistor 23, the potential of both gate connection points 33 becomes Vcc+V.
It must not exceed th'. Note that v th' is the threshold value of the enhancement MOS transistor 23.

If the potential of connection 33 becomes more than Vcc+Vth',
The MOS transistor 29 becomes conductive and the power supply VCC
As a result, the potential at the connection point 33 becomes Vcc+Vt.
I settled on h'.

When the potential at the connection point 33 is Vcc+Vth', the word line output terminal 34 becomes approximately at the Vcc level, and when the write signal W is applied, the word line potential 34 is raised to VW by the action of the capacitor 24.

At this time, the enhancement MO5) transistor z3 is in a cut-off state.

If the MO3) transistor 29 is not connected, the potential at the connection point 33 may become Vcc+Vth', and even if the write signal W is applied to raise the word line potential, the enhancement MO5) transistor 23 will not be connected. There is a possibility that the word line potential will not become high because the cut-off state does not occur.Instead of connecting the MOS transistor 29 as described above, the second boost capacitor 28 is connected as shown in FIG. 5(a).
It can also be constructed by connecting a NOR gate to which the inhibition signal INH is input to one electrode of the circuit, but the signal waveform diagram shown in FIG. It is necessary to control circuit operations at appropriate timings.

As described above, according to the present invention, the number of elements constituting a memory cell can be reduced, and data read/write operations can be controlled with a simple signal generation circuit, and the cell structure and drive circuit are suitable for high-density memory devices. can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) are circuit diagrams showing a conventional memory cell structure, FIGS. 2(a) to (c) are circuit diagrams showing a memory cell structure according to the present invention, and FIG. 3 is a circuit diagram showing the same memory cell structure. Figure 4 (a) and (b) are voltage-current characteristic diagrams to explain the operation of the
) is a word line signal generation circuit diagram according to the present invention and signal waveform diagrams at each point in the circuit, and FIGS. 5(a) and 5(b) are other word line signal generation circuit diagrams and signal waveform diagrams at each point in the same circuit. It is a diagram. Ql, Q2: MOS transistor included in flip 70 tube, Qo nitrogen transfer gate M03 transistor,
Sister, 23: Ennoment MOS transistor, 24.28 = Boost capacitor, 29: MOS transistor, W: Write signal. Agent Patent Attorney Aihiko Fukushi sIrIA 7i2m No. 31M 2 (Evil 4m(b) Procedural Amendment August 12, 1980 To the Commissioner of the Japan Patent Office 1, Case Indication Patent Application 1982-] 37924 2. Name of the invention Semiconductor memory device 3, relationship with the amended person case Patent applicant address 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, 545 Japan
Name (504) Sharp Corporation 18 Agent 11 Address 22-22-5 Nagaike-cho, Abeno-ku, Osaka 545 Date of amendment order 6 Target of amendment 1) Detailed explanation of the invention in the specification Column γ, contents of amendment 1) The entire text from page 12, line 17 to page 13, line 3 of the specification will be deleted. 2) The full text of lines 4 to 8 on page 13 of the specification will be corrected as follows. Data read/write operations can be performed more reliably with the signal generation circuit, and a memory cell and drive circuit suitable for high-density memory devices can be obtained. 8) W14 specification, page 13, lines 15 to 17-k
. "Signal waveform diagram, Figure 5 (&)...This is a signal waveform diagram." will be corrected to "This is a signal waveform diagram." 4) Figure m, Figure 5-) and 伽) will be deleted. that's all

Claims (1)

[Claims] 1.Mo3) One transformer 7 agate Mos transistor is connected between a data line and a flip-flop in which two inverters including an resistor e are cross-coupled, and a data line is used for reading/writing data. A memory cell whose word line is the gate of the transfer gate Mos transistor, an enhancement MO transistor inserted between the power supply VCC and the lead line, and a memory cell selection signal connected to the gate of the enhancement MO transistor. Boost effect when applied 9 Vcc+Vt
h'(Vth': L key value of the enhancement MOS transistor (7) mentioned above) to generate a potential close to the power supply voltage on the word line, and a power supply on the word line by boosting for data write operation. The source and drain are connected between the gate and power supply of the enhancement MOS transistor and another capacitor provided on the word line to give a potential higher than the voltage. 1. A semiconductor memory device comprising: a MOS transistor connected to the semiconductor memory device;