JPS5840954A - Data transmitting system - Google Patents

Abstract

PURPOSE:To simplify the constitution and at the same time to improve greatly the promptness for collection of data at the main device side, by performing simultaneously both designation of address to plural data and the transmission of information which is carried out in response to the change of said address designation. CONSTITUTION:The output showing a periodical change which is delivered from a voltage or current stabilizing circuit that is controlled by a periodical signal (a) containing the synchronizing signals of different waveheights is transmitted from a main device ME. A secondary device SE counts CT the transmitted output changes of the device ME. According to this count result, the address is designated for the data, and then the output of the device ME is set under a load state in accordance with the change of the data and at the same time synchronously with the output change of the device ME. Then the change of the voltage at the main device side or the change of the control voltage of the voltage or current stabilizing circuit which is caused in response to the load state of the main device output is detected. In such way, the change of the data is transmitted to the device ME from the device SE.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission system with a simple configuration.

Conventionally, when it is easy to transmit a plurality of data generated in the sub-device 111 to the main device, or when data generated in a large number of sub-devices is distributed and transmitted to the main device,
Generally, a method is adopted in which the main device transmits a polling signal that individually designates each subdevice for each data item, and the subdevice that releases the polling signal sends data corresponding to the polling signal to the main device. Since the encoded polling signal is used in the evening, #I power becomes complicated, and it is not possible to transmit the polling signal and the data at the same time, and it becomes difficult to collect each data on the main device side. This has resulted in drawbacks such as lack of immediacy.

The purpose of this invention is to fundamentally solve the above drawbacks of the conventional technology, and to prevent periodic changes in voltage or current stabilizing circuits controlled by synchronous signals including synchronous signals with different peak values. The main device sends out an output indicated by the main device, and the sub device counts the changes in the transmitted output of the main device, specifies the address of the data according to the count result, and then specifies the address according to the change in the data, and By placing the main device output in a load state in synchronization with changes in the main device output, and detecting the corresponding change in the control voltage in the voltage or current stabilizing circuit on the main device side, changes in data can be detected from the sub device. The present invention provides an extremely effective data transmission method for transmitting data to a main device.

The details of the present invention will be explained below with reference to figures showing actual examples.

No. 1111 is a circuit diagram when a current stabilizing circuit is used, and the main device M1 is provided with a current stabilizing circuit consisting of an operational amplifier op, a transistor Qh (h, and a resistor casu to Rs). Driven by the output of the operational amplifier OP, the transistors QI and Ql operate complementary to each other in the linear region, and the output current is sent out from the connection point of the resistor R1e and circulated through the line Ll*Ll. By detecting changes in current as the terminal voltage of resistor R, and applying this to the inverting input of operational amplifier OP, the control voltage applied to the bases of transistors Qt and Qs is set in a direction that suppresses changes in output current. , and sends out a constant current output to the lines - and Ll.

In addition, a comparator CP is provided to compare the control voltage with the reference voltage V1m set in the potentiometer RVI, so that the control voltage is set to the reference voltage Vsl.
This is used to detect when the value has decreased.

As shown in Figure 2, a periodic rectangular square wave signal containing a synchronizing signal 8YN with different peak values is input to the non-inverting input of the operational amplifier OP ( a), an output current with the same waveform as this is sent to the line Ll @ t, , and the sub-device SE
of the square wave signal (1
) occurs across resistor R6.

This terminal voltage is applied to the comparison input of the comparators apl and CPs, and in the n1 comparator CP, it is compared with the reference voltage VaI determined by the potentiometer RV, and synchronous No. 16 5YN (b) is extracted. Yeah, this 2'
Kawanta CT is reset by LK.

In the comparator cp3, the terminal voltage of the resistor R is compared with the reference potential, and only the half wave is extracted to become the Glock pulse (C), which is given to the Kawanta CT, so the Kawanta CT is , periodic changes in the output current are calculated using the synchronization signal 8YN(b) as a reference, and the quantized result is sent from the output q and given to the selector SEL as a selection command.Selector 8EL outputs the output Q. A switch 81 indicating a plurality of data is used to sequentially select inputs D1 to Dn according to the selected output (d) and provide the selected output (d) to the base of the transistor Qs.
~8 in SrI. is on, the power supply +V is applied to the input D3, which is at the reference potential by the resistor R.
is applied, the selection output (d) is generated in synchronization with the fs2 bus of the clock pulse (C) based on the synchronous signal %5YN (b), the transistor Qs is turned on, and a low resistance value The resistor R- bridges the @paths L1 and L8, and forces the output current into a load state in synchronization with periodic changes in the output current.

Then, the output current does not change, but the control voltage (,) changes in the direction of decreasing and becomes lower than the reference voltage V11.
The specific absorber CP1 detects this n and generates a detection force (f) according to the change in data.

Therefore, the square wave signal (-) and the detection force (an
If it is applied to the D gate G, the output of this is sent to the switch 8. A reception output (ri) corresponding to the data situation indicated by is obtained.

In addition, in the sub device 81c@, the square wave signal 6) is
-)" It is rectified by DK, smoothed by capacitor C, stabilized by source stabilization unit REG K, and at the same time set to a predetermined voltage in the power supply V, and then supplied to each part.

FIG. 3 is a circuit diagram showing the main device ME when a voltage stabilization circuit is used, and similarly to FIG. 1, an operational amplifier OP, transistors Qt - Qz, and resistors R1, R are provided. , the connection point voltage of resistors R1, R, is applied to the inverting input of operational amplifier OP1, and these constitute a constant voltage circuit. In order to improve waveform distortion caused by VC transmission, a sine wave signal is used as the periodic signal.

Note that the configuration of the cleavage@SE@J is the same as that shown in FIG. 1, and operates as shown in FIG. 4, which shows the waveforms of each part in the sub-device SE of FIG. 3 and FIG. 1 as a timing chart.

That is, if a sine wave signal (-) containing the synchronization signal SYN with different peak values is applied to the non-inverting input of the operational amplifier OPl, an output voltage having the same waveform as this is sent across the line L1sI'1, and in the sub-device BΣ. is comparator CP2. C.P.
The synchronization signal 8YN(b) and clock pulse (ε
) is extracted, and if switch S3 is turned on, a selection output (d) is generated in the same way as described above, and transistor Q
s is turned on, and the output voltage between the lines L2 and L2 becomes a load state, so that the control 'ζ pressure <e> in Fig. 3 changes in the upward direction, and the reference voltage Vs1 of the comparator CP becomes υ higher. Then, a detection force of n is generated and a reception output (r) is obtained.

Data transmission is also performed by the main device ME in FIG. 3 in the same way as in FIG. 1.

However, in the case of Fig. 3, as shown in Fig. 4(f), the synchronization signal 5YNr (therefore, the received output (r) is generated, so based on the square wave signal (, ), the received output ([) is Is it necessary to eliminate the synchronization signal SYN and its counterpart?

Therefore, with a simple configuration, the switches 81 to 811
Addressing multiple data indicated by
Transmission of information according to these changes is performed at the same time, which simplifies the configuration and greatly improves the immediacy of data collection in the main device @, compared to the case where polling signals are used.

In addition, the signal waveform sent to line Ill + L2 is as follows:
A square wave, a sine wave, or the like may be used depending on the condition of φ, and the same may be applied to a single-polar wave instead of a double-current wave, and other switching elements may be used in place of the transistor Q3.

Furthermore, the constant current and constant voltage circuits may be arbitrarily selected as long as they have similar functions, and the number of sub-devices SE may be plural, and the present invention can be freely modified in various ways.

As is clear from the above description, according to the present invention, with a simple and inexpensive configuration, it is possible to transmit a plurality of data in a timely manner, and it exhibits a remarkable effect when used for data collection at a remote location.

[Brief explanation of drawings]

The figures show an embodiment of the present invention, Fig. 1 is a circuit diagram when a constant current circuit is used, Fig. 2 is a timing chart showing waveforms of various parts in Fig. 1, ft, and Fig. 3 is a circuit diagram showing a constant voltage circuit. FIG. 4 is a circuit diagram showing the main device when used. FIG. 4 is a timing chart showing waveforms of various parts in the sub device of FIGS. 3 and 1. ME...Main device, SE...Sub device, OP...
・・Operation amplifier, cp, ~CPs・・Comparator, CT
...Kawanta, SEL ...Selector, Q1
~Qs...Transistor, R, R1~Rs
...Resistor, Rvl, Rvl ...Potentiometer, 81~8m ...Switch, 8YN
...Synchronization signal. Patent applicant Tadashi Totsuka Male agent Masaki Yamakawa (and 1 other person) Figure 2 Figure 3 1 set! Figure 4

Claims (1)

[Claims] (1) The main device sends out an output current that shows periodic changes in the current stabilizing circuit, which is controlled by a periodic signal into which synchronization signals with different wave peak values are inserted, and the sub device outputs the output current of the output current. Quantifying synchronous changes in the output current using the synchronous signal as a reference, specifying addresses for a plurality of data according to the quantizing results, and quantizing the synchronous changes in the output current according to the data changes and in synchronization with the synchronous changes. A data transmission system characterized in that the output current is forcibly brought into a load state, and on the main device side, a change in the data is detected by a change in the control voltage of the current stabilizing circuit corresponding to the load state. (b) The main device sends out an output voltage that shows synchronous changes in a voltage stabilizing circuit controlled by a periodic signal in which synchronization signals of different peak values are inserted, and the sub device outputs the synchronization signal in the output voltage. A temporary change in the output voltage is determined based on the signal, and addresses for a plurality of data are specified according to the result of the calculation, and the change in the data is made nine times and synchronized with the synchronous change. 4911, forcibly setting the output voltage in a load state, and detecting a change in the previous P data on the main device side by a change in the control voltage of the voltage stabilizing circuit corresponding to the load state. method.