JPS5840923A - Analog-to-digital converter - Google Patents

Abstract

PURPOSE:To obtain an output of high accuracy, by compensating an error caused by the offset voltage of an amplifier, etc. and peculiar to a voltage balance type A/D converter. CONSTITUTION:An operational amplifier 2, a capacitor Cf, a comparator 3, a reference voltage generating circuit 12, a clock controlling circuit 13 which generates an output pulse P0, etc. form a V/f converting circuit which converts an analog input signal Vi into a pulse signal. This pulse signal is counted by a counter 16 and then delivered through an output circuit 17 containing a latching circuit. Thus an A/D converter is obtained. In this case, a switch S13 is previously closed to give zero voltage to an input. Then the offset pulse at that moment is measured to obtain an offset error, and the digital offset compensation coefficient corresponding to the offset error is stored in an offset counter 14. At the same time, a coefficient circuit 15 stores the full-scale compensation coefficient, and a preamplifier 11 compensates an offset through a voltage generating circuit 18. An output of high accuracy is obtained by compensation given through the circuits 14 and 15.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge-balanced A/D converter, and particularly to an A/D converter that does not require external components and has a structure suitable for LSI integration.

FIG. 1 is a block diagram showing an example of a conventional charge-balanced A/D converter. In Figure 1, 1 is a buffer amplifier, 2 is an operational amplifier, 3 is a comparator, 4 is a clock generation circuit that generates clock pulses, 5 is a control circuit that controls the operation of analog switches, 6 is a counter, and 7 is a latch circuit. .

R,, R,2 is a resistor, Ct is a capacitor, Sl, S2
is an analog switch, Vil and VB2 are reference power supplies.

The operation of the above configuration will be explained using the time chart shown in FIG. In FIG. 1, the resistance at,
R,, an integrating circuit is formed by the capacitor Ct and the operational amplifier 2, and the input voltage vI is integrated to obtain the next voltage V as the output voltage of the operational amplifier 2. occurs.

FIG. 2(a) shows the clock pulse CP which is the output of the clock generating circuit 4, and (b) shows the output voltage of the integrator ■o1←→ shows the output voltage of the comparator 3. Control circuit 5
is generally the rising time of the clock pulse CP, t
If the output voltage of the comparator 3 is negative at =i, the analog switch is controlled so that the analog edge S1 of the negative reference voltage source VRI is turned ON for the clock pulse width Ton. If the output voltage of the comparator 3 is positive, the analog switch s2 of the positive reference power supply VR2 is similarly turned on. Time 1=1. -,. 1=1. +, the integrator output voltage V. is expressed as follows.

In Fig. 2) and (e) are analog switches 81 and 81 respectively.
The control pulse for turning on +82 is shown. This control pulse is an output pulse P 01 p P 01! from the control circuit 5 to the counter 6. become. During the A/D conversion time T0, which includes N clock pulses, the output pulse P
. IePO2 is N respectively. 1+NO2 is included, the balance of charges injected into the integrating circuit during the conversion time T is as follows. That is, the charges injected from the input voltage V+ during the conversion time T6 are kept in a balanced state by the No. 1 negative reference charge injection and the No. 2 positive reference charge injection. From equation (3), N=NOI Since NO2 is proportional to the input voltage V+, the output pulse P. 1゜PO2 to counter 6
This output N is latched by the latch circuit 7,
A/D conversion output.

FIG. 3 shows the current waveform that provides the reference charge injected through resistor R2. From time j-1, 1=j
The reference charge qrj injected during j+1 is as follows.

The causes of errors included in the output values in the conventional example described above are as follows. The first is an error in the offset voltage of the buffer amplifier 1 and the operational amplifier 2, and the second is an error in the reference voltage q. The latter factor can be further subdivided into: The first is the error in the ratio R2/R of resistors R1 and R2. Since A/D conversion is performed under the condition of balance between the charges injected through both resistors, an error in this ratio becomes an output error. This error includes initial setting errors and errors due to temperature fluctuations, etc.

The second is analog switch S1. The on-resistances r and a of S2 give an error to the magnitude of the reference charge q1. Since this on-resistance varies depending on voltage and temperature, eventually r1
The condition 111<R2 must be satisfied. The third is analog switch Sl, S.

The transient phenomenon during on and off, that is, the reference charge q1, is (4
) is the integral value of the current shown in FIG. 3, so the rise and fall characteristics of this current become a cause of error.

For the same reason, analog switch S1. The variation in the on-time Tom of St becomes an error. This is the fourth factor. Fifth, there is charge injected through the gate from the control circuit of analog switch S+, 8*. This is called analog switch spike noise. In order to reduce these errors, a resistor and a capacitor are usually attached externally to an IC (integrated circuit) as components, and a variable resistor is added to the resistor for fine adjustment.

As mentioned above, there are many error factors within the IC, and it is extremely difficult to achieve an accuracy of 12 bits or more, and furthermore, it is impossible to attach external components to the outside.

An object of the present invention is to eliminate the drawbacks of the prior art described above, and to provide an A/D converter that can obtain highly accurate output by compensating for errors caused by offset voltages of amplifiers specific to charge-balanced A/D converters. It is on offer.

For this reason, the present invention provides a V/f conversion circuit using an integrating circuit that converts an analog input signal into a pulse signal, a counter that counts the pulse signals of the V/f conversion circuit, and a count value of this counter that is input to the analog input signal. an output circuit that outputs a digital value corresponding to the signal; a means for providing a reference voltage for detecting the offset amount of the V/f conversion circuit;
The offset compensating means counts pulse signals corresponding to the offset amount of the f conversion circuit and stores them as digital signals.

Next, the present invention will be explained in detail with reference to figures showing examples.

FIG. 4 is a configuration diagram showing an embodiment of the present invention. In FIG. 4, the same reference numerals as in FIG. 1 indicate the same components. Fourth
In the figure, 11 is a preamplifier that amplifies the input voltage VI;
S11~StS are analog switches, CI, e CI2
．． C@Cbl, Cb2 is a capacitor, 20~2
2 is a buffer amplifier; 13 is a drive signal P8R% output pulse P of the analog switch 816 from the output voltage of the comparator 3 and the clock pulse CP;

14 is an offset counter that counts offset pulses; 15 is a coefficient circuit that multiplies the output pulse P of the offset counter 14 by a coefficient; 1;
6 is a counter that counts the output pulses P of the coefficient circuit 16; 18 is a compensation voltage generation circuit that generates an offset compensation voltage for the preamplifier 11; and 12 is a reference voltage generation circuit.

FIG. 5 is a configuration diagram showing one embodiment of the offset counter 14. 30 is a latch circuit, 31 is a presettable counter that can preset the output of the latch circuit 30, 32
is a flip-flop, and 33 is an AND gate.

FIG. 6 is a block diagram showing an embodiment of the coefficient circuit 15 shown in FIG. 4. 32, 34 are adder circuits, and 33.degree. and 35 are registers for storing the addition results.

FIG. 7 is a block diagram showing an embodiment of the coefficient setting circuit 17 shown in FIG. 4. 40 is a complement generation circuit that generates its complement;
42 is an adder circuit, 43 is a register, 41 is a latch circuit,
44 is a memory circuit.

FIG. 8 shows the D/D included in the compensation voltage generation circuit 18 of FIG.
FIG. 2 is a configuration diagram showing an example of an A conversion circuit. 61,5
2 is a buffer amplifier, 53.54 is an operational amplifier, 851
-866 is an analog switch, and Cat~C54 is a capacitor.

FIG. 9 is a configuration diagram showing one embodiment of the preamplifier 11 in FIG. 4, where 61 and 62 are operational amplifiers, R6 is a resistor, and C61
is a capacitor, and S and 1 are analog switches.

The operation in the above configuration will be explained next. In the present invention,
It has three types of conversion cycles: In FIG. 4, the first conversion is an offset correction cycle in which the switch StS is turned on and the zero voltage is A/D converted.
The third is a measurement cycle in which the switch S,1 is turned on and the input voltage v1 is A/D converted, and the third is a full scale correction cycle in which the switch 8111 is turned on and the full scale reference voltage VF is A/D converted. First, the A/D conversion operation will be explained in detail by taking a measurement cycle as an example. Conversion time T.

is selected to be one cycle of the commercial power supply, that is, 1150 seconds or 1/60 seconds, in order to improve noise resistance. Input voltage vI
is amplified by the preamplifier 11 and becomes vII.

The switch 814 is first turned on to the a side and the capacitor CIl is turned on.
Charge it to the vth point. At this time, the charge accumulated in the capacitor is qI-011v (the capacitance of the capacitor is expressed by its sign). Next, the switch 814 is turned on to the b side,
This charge is discharged. If the gain of operational amplifier 2 is large enough, the potential at point A will be zero, and the following capacitor CI,
is completely discharged.

The operational amplifier 2 and the correductor Cf constitute an integrating circuit, and the charge q1 discharged from the capacitor C11 is accumulated in the capacitor Ct. Similarly, the bias charge q is converted from the reference voltage VB by the switch S11 and the capacitor Cb1.
b: Cb, Vil are injected into the integrating circuit. These switches S□4*81? repeats this operation at a constant period Tap in synchronization with the clock pulse CP. Therefore,
The output voltage V+t of the integrating circuit is ΔV+t= (q quantum qb) for each Tap time.
...(5) Change by t. FIG. 10 is a time chart showing the operation of the integrating circuit, where (a) is a clock pulse and (b) is a clock pulse.

(→ indicates the signal voltage that turns on the switch S14+st7 to the b side, and (b) indicates the output voltage Vat of the integrating circuit.) indicates the output voltage Va of the comparator 3, and when the integrating circuit output voltage Vat becomes negative outputs a positive voltage. At the rise of the clock pulse CP, the clock control circuit 13 outputs an on-pulse Psi to the switch 816 and outputs an output pulse P0 to the offset counter 4 if the comparator output voltage Va is positive.

The switch Sta is normally turned on to the a side, and the capacitor C1 is charged to the reference voltage -Vm. When the on-pulse PsB arrives, it is discharged to the b side. The amount of charge q discharged at this time is q, = vIl, c, -----・-・
(6), this is the reference charge that is input to be balanced with the input charges Qt and the IA charge qb.

On-pulse PIIR is shown in FIG.

If the number of clock pulses CP within the conversion time T is No, and the number of on-pulses PIIB is Nu, then the total amount of charge accumulated in the capacitor Ct within the conversion time T is: No (Q I + qb ) + NRqr = 0
(7) That is, the number N of output pulses P
g is as follows (8) and is proportional to the input voltage V+t=AVI.

FIG. 11 shows the integrating circuit output voltage waveforms for three types of input voltages. The lock pulse CP1 (b) in the figure (a) is the waveform of the integrated voltage V+t when Vt=O, and Vie changes mainly due to the bias charge Qr.

In the same figure (→ is 1/2 full scale voltage, that is, V+ = 1/
2VF (waveform at 0, qt = 1 /2 Q r
This indicates that the reference charge qr is injected approximately once every two clock pulses CP.

In the same figure) is the waveform when the full-scale voltage V I = V r is input, and q (= q), indicating that the reference charge is injected into the clock pulse CP almost every time. .

FIG. 12 shows ideal conversion characteristics targeted by this embodiment. The horizontal axis is the input voltage vI, and the vertical axis is the number n of output Noculus Po.
It is. When input voltage v1 = 0, output pulse number n =
Nb, and this is called the](Ias・(Russ number).

Nb=2b......(9) is satisfied. When input voltage V+ = VFO, output coupling number n
= N r to satisfy Ny = Nc + Nb . . . QI N c = 2.

The above is mainly the operation f6 of the analog section in the embodiment of FIG. Capacitor C+12 is a co/capacitor for switching power supply frequency 50/60H2, and when switch 81B is turned on at 60H1, capacitor C+1. Use Ct2 in parallel. Capacitor Cb2 is a bias charge capacitor used when handling bipolar input voltage, and in the case of bipolar voltage, the input charge Qz when V I = 1 / 2 V F of unipolar input is
A bipolar bias charge Qbb equal to capacitor C
Supplied from b2. Switch sea is for supplying this bipolar bias charge qbb.

Next, the operation of each conversion cycle will be explained using the case of unipolar input as an example.

First, switch S13 is turned on, zero voltage is input, and an offset correction cycle is performed. The above explanation,
By the conversion operation, the zero voltage for time T1 is A/D converted.

The output pulse P0 of the clock control circuit 13 should originally be only a bias pulse due to the bias charge qbK, but
Offset voltage of preamplifier 1-1, offset voltage of operational amplifier 2 that constitutes the integrating circuit, analog switch S
The influence of the spike nozzle etc. of I4.8□, ie, the influence of all error factors resulting in offset error appears. The output at this time is
The offset counter 14 and the coefficient circuit 15 are directly counted by the output counter 16.The counted value is a number Nha that differs from the bias pulse number Nb by the offset error Nog.The offset error N.8 is If it is sufficiently small, for example Nog<1/2Nb, the digital offset correction coefficient Th, a = Nb- is latched by the latch circuit 30 in the offset counter 14. If the offset error Nos is Nos>1/2N
Case b will be described later. This completes the offset correction cycle.

Next, the operation of the full scale correction cycle will be explained. Prior to starting the conversion operation, the digital offset correction amount Ned in the latch circuit 30 is loaded into the presettable counter 31 in the offset counter 14, and the flip-flop 32 is reset. switch S1
Turn on □ and input the full-scale reference voltage VF to start the conversion operation. Output of clock control circuit 13]
Kurus Po is AND gate 3 in the offset counter
3, and is input only to the presettable counter 31. The greasy counter 31 decrements its contents by 1 each time an output pulse P arrives. After counting Naa output pulses P, the presettable counter 31 outputs an underflow pulse Pd, and the flip-flop 32 is set. As a result, the AND gate 33 outputs the output pulse P to the coefficient circuit 15 as an effective pulse P. The coefficient circuit 15 is composed of two sets of adders as shown in FIG. Configure.

The first adder performs gain correction. The gain correction method will be explained with reference to FIG. 13, which shows actual conversion characteristics. 1st
The vertical axis in FIG. 3 indicates the number of effective pulses P. There are various factors that cause gain errors. The first term on the right side of equation (8) shows this, and for example, the gain error of the preamplifier 11, the error of the reference voltage VR, the capacitance ratio C+1/Cr, and the switch 816 are proportional to the output pulse P. Since it is driven, spike noise that enters from here also causes gain errors. In this way, due to the influence of all the factors that result in gain errors, the actual conversion characteristic becomes as shown by the solid line, as opposed to the ideal conversion characteristic shown by the dashed line in FIG. That is, when the full-scale reference voltage Vr is input, the number of effective pulses P is actually N with respect to the true value Nc. Therefore, the true value Nc is equal to the effective pulse P, and the next gain correction coefficient is 1.
Find it by counting the products multiplied by . N-=N
c+ΔN.However, in order to obtain this gain correction coefficient, division is required, which complicates the circuit. Therefore, the gain correction coefficient is set to 1 using the following approximate equation, and adaptive control is performed.

ΔN.

K, Yu1-□ ......0 noc Nc satisfies < 2 C as shown in formula 01, and the gain correction coefficient of 1 means that the decimal point shift and complement are applied to Ns. You can easily find it by taking Therefore, the coefficient set in the current full scale and scale correction cycle is
ti, the effective pulse P in the coefficient circuit of FIG.
, starts the adder circuit 32 and registers the register 33 every time .
1 is added to the contents of and the gain correction coefficient, and this result is stored in the register 33. At this time, if the carry above the decimal point is extracted as an output pulse, this pulse becomes the effective pulse P
, multiplied by Ktl. The second adder is for performing non-linear correction, and for the sake of simplicity, if we assume that the non-linear correction coefficient Kj=1, the carry becomes the conversion pulse P0 which is the output of the coefficient circuit 15. Conversion period T
, this conversion pulse P.

Suppose that when counting, a count value N,j~NC751 is obtained. This means that the gain correction coefficient KgJ used at this time is Ktl
It means that it was niyo. Therefore, from 0 to the error Δ of the correction coefficient at this time, the next correction coefficient KK, etc., is set to KtJ,, =Kt, -Δ, etc.
... Find it as a→. This calculation is performed by the coefficient setting circuit 17 shown in FIG. The detailed configuration is as shown in FIG. Once the count values N and S of the conversion nodal P of the full-scale correction cycle are determined, (1-Koh formula calculation is completed by only moving the decimal point. This result is input to the complement generation circuit 40 in FIG. 7. -Kg, is added to the current correction coefficient KgJ in the register 43 in the adder circuit 42, and the result is stored in the register 43.The contents of the register 43 at this time are updated. gain correction coefficient Kt
It is J□.

Digital offset correction coefficient D determined as above
1111% A third cycle, a measurement cycle, is executed using 1 as the gain correction coefficient. In this cycle, the switch Stt is turned on to take in the input voltage vI and perform A/D conversion. The operation at this time is as explained above. In addition to gain correction, a non-linear correction method required for thermocouples and the like will be explained here. FIG. 14 is a diagram showing the non-linear conversion characteristic. When the input voltage v1 is input, if the linear conversion characteristic is shown by the dashed line, NI' can be found, but the actual desired conversion value is Nl. Therefore, this non-linear correction is
This is performed using the second adder of the coefficient circuit shown in the figure and the coefficient setting circuit shown in FIG. Charge-balanced A/D converters are originally intended for input voltages that change slowly. Therefore, it is assumed that there is not much difference between the output value Nr1.1 of the previous measurement cycle and the current output value N13. The nonlinear correction coefficient Kj is calculated as follows for the output coefficient value N1: K x + = N t / N t '
. . . As C51, the entire span is equally divided and stored in the storage circuit 44 using broken line approximation. Therefore, the count value NB-1 from the previous measurement cycle is latched in the latch circuit 41, and the output of this latch circuit is read out from the memory circuit as an address input to the memory circuit 44 as a non-linear correction coefficient Kzt, and inputted to the adder circuit 34. do.

The adder circuit 34 adds the contents of the register 35 and the nonlinear correction coefficient KjI each time a carry from the first adder circuit 32 arrives, and stores the result in the register 35. The carry from the adder circuit 34 becomes the output (P).The coefficients that can be handled by this counting circuit are numbers less than 1.Therefore, in the case of an upwardly convex conversion curve as shown in FIG. It cannot be straightened as it is. Therefore, in such a case, assume the conversion characteristic shown by the two-dot chain line below the entire range of this conversion curve, and adjust the gain correction performed by the first adder as shown in Figure 15. N,', and non-linear correction is performed from this temporary conversion straight line to the actual conversion characteristic, N+, N+' in Figure 15.
This is performed using the non-linear correction coefficient Kz+=Nt/Nt'.

The three types of conversion cycles mentioned above, namely the offset correction full scale OC1 measurement cycle M1 and the full scale correction cycle FC, are actually executed in the distribution shown in FIG.

Next, when dealing with a very small input signal level, the input voltage Vt and the offset voltage of the preamplifier 11 will be of similar magnitude, and there is a risk that the dynamic range will be significantly narrowed if only the digital offset correction described above is used. In such a case, counter 1 during the offset correction cycle
The offset error N included in the count value Nb due to 6. 8
You can tell the symptoms by seeing it get bigger. In such a case, two methods will be described below in which offset compensation is performed in an analog manner by generating an offset compensation voltage by the compensation voltage generation circuit 18 and inputting it to the preamplifier 11.

An example of the D/A converter of the compensation voltage generating circuit 18 is shown in the eighth example.
Shown in the figure. Now, as the analog offset compensation amount, D
*aj is assumed to be set.

Do @ J is a bit binary number Doaj=ak-1'2 +ak-2'2 +"・
・+a2・2”-1-a, ・2+aO・・・・・・・・・
・(This can be expressed as 161. In Fig. 8, an analog compensation voltage V, which corresponds to this binary number, is generated. First, depending on the polarity of D o a J, if it is positive, 851 is turned on for a certain period of time, and the capacitor Charge C61 with vRK. Capacitor 7 Cas t C52 (D capacitance cst = cst. Next, when switch SSS is temporarily turned on, 1/2 of the charge of capacitor C51 is transferred to capacitor C62, and ■.
River=1/2VB=V-st=V-52. Therefore(
When ak-, which is the MSB of the le formula, = l, switch ss
When s is temporarily turned on, all the charges accumulated in capacitor CWt are transferred to C63. At this time, when the operational amplifier 53 is output, switch 8114 is temporarily turned on and capacitor C62 is output.
discards all accumulated charge. Next, when the switch 85B is turned on again, 1/2 of the charge accumulated in the capacitor C6 is transferred to the capacitor CS2 again. As in the previous case, this time either the switch SSS or 8B4 is turned on depending on the value of the coefficient ak, , in equation (16). By successively redistributing the charge accumulated in the capacitor C51 in this manner and repeating this process several times, the output voltage V.6' of the operational amplifier 53 can be obtained as +a,.Z+aO) -°aη. After this conversion is completed, the switch ss6 is temporarily turned on to hold this voltage on the capacitor C54K, and the output voltage of the operational amplifier 54 becomes ■. . Let be the offset compensation voltage.

An embodiment of the preamplifier 11 is shown in FIG. FIG. 9 is called a duty ratio amplifier, and the gain is the ratio of the on time of the switch 861 to the a side to the b side on time α = Tb, -
/ Has characteristics determined only by T-0. Offset compensation voltage V is applied to the positive phase input of the operational amplifier 62 of this amplifier.
Suppose you input oe.

Vo. 1 digit is ΔV, -= (VB/2) ・(C1+2/C5
+1)・・・・・・・・・(I group. Let the change in the output count value due to the change in this Δ■.8 be N −”, i N b. If reproducibility is ensured, this relationship is It doesn't have to be accurate.

Now, in a certain measurement cycle, the analog offset correction coefficient is calculated. aj- digital offset correction coefficient Deu
-x. Next, as a result of executing the offset correction cycle, offset pulses Nb,j are counted, and Nom5 = Nb*I Nb > 1/4 Nb
Assume that it has become. The next measurement cycle and full-scale correction cycle uses the digital offset correction coefficient Do
Conversion is performed by changing only aj to d1=Nb, j. In the next offset correction cycle, 1/J N b included in the digital offset correction coefficient Do a 1 is transferred to the analog offset correction coefficient Do oa, and
The offset correction cycle is executed as ``a1yus''D o a H.As a result, the offset pulse N when the analog offset correction coefficient D oaj+1 is
b5j++ is counted, so that in the next measurement cycle and full-scale correction cycle, the updated analog offset correction coefficient ILaJ+h digital offset correction coefficient Da a j+ + =Nb a j□ is used to perform the conversion.

FIG. 17 is a flowchart showing an offset compensation method that summarizes the above explanation. First, initial values Ded, HDo, of digital and analog correction coefficients for offset correction determined at the time of design or testing. After setting (too), clear flag F (105
). The above is the initialization process, and thereafter, '' is the normal process that is repeated every conversion cycle. First, the analog correction coefficient is adjusted within the range of ±1 depending on the state of flag F, and then flag F is reset (110 to 130). After that, the offset counter 14 (and coefficient circuit 15) is formed with a path circuit (135), zero voltage is input (140), and A/D conversion is performed for offset correction (145).
).

Nba, which is the output of this A/D conversion, includes ｵ(Iasｳｮｮｮｮｮｮｮ) and offset error Nag. There are also factors that cause errors in the circuit centered around Cb1.

However, all of these errors result in an offset error Nos. ) Offset error Nos and offset analog correction 1 digit output conversion value N, 1 (in this example, N
, , = 1/4Nb), and the offset error No.
If s is -Noa or less, flag F=1, if it is Noa or more, F=2, l Nos l (If No-, set F'=O (155 to 170). This will be used for the next This means that the analog offset adjustment amount for the conversion cycle has been preset.The current offset digital correction coefficient D a a is the upper offset count value N b
After applying the input signal voltage VI (175, 180), the input signal voltage vI is A/D converted using the offset counter (175), the offset counter (14), and the coefficient circuit (15). The above is one cycle of A/D conversion consisting of offset correction and measurement cycles. In the next conversion cycle, after adjusting the analog offset correction according to the state of flag F that was preset this time,
A digital offset correction coefficient corresponding to this analog offset correction amount is set and a measurement cycle begins. In this way, the amount of digital offset compensation is determined in correspondence with the amount of analog offset compensation for each conversion cycle, so the relative relationship between the two does not need to be accurate; for example, when generating a compensation voltage for analog offset compensation. Offsets of the circuit (FIG. 4, 18), nonlinearity of input/output characteristics, long-term drifts, etc. do not impede the present correction method at all.

FIG. 18 is a flowchart showing a full scale correction method. Full-scale correction coefficient K determined at the time of design or testing as initialization processing.

to the initial value of . (200). After the offset correction (205) described above is performed as normal processing, A/D conversion (210) of the measurement cycle is performed. After that, the full scale correction cycle starts, and if the switch 812 in FIG. 4 is turned on and the full scale reference voltage VF is applied (215), this full scale reference voltage VF is
D conversion is performed (220). From the output value N at this time, the correction amount Δ of 1 is calculated as 1 (225), and the full scale correction coefficient for the next conversion cycle is determined (230).
)N to end the full scale correction cycle.

Although the above description is for the case of Unipolar 2 inputs (unipolar signals), it is possible to similarly correct the case of Bibo length inputs (bipolar inputs).

However, in the case of unipolar input, offset correction could be performed regardless of the gain correction coefficient of 1, but in the case of bipolar input, there is mutual interference. FIG. 19 is an A/D conversion characteristic diagram showing an example of a correction method in the case of bipolar input, and corresponds to FIG. 12 described earlier. The horizontal axis is the long voltage, which varies within a range of VF (full-scale voltage), and offset correction is performed using the zero voltage in the center, and full-scale correction is performed using the +'VF voltage. The same figure (a) shows the ideal conversion characteristic, when the -VF large input, the number of output pulses P, matches the number of bias pulses Nb, and when the voltage is zero, the full scale correction coefficient is The output conversion pulse P is the bipolar bias pulse N b b a'), +
When Vp is input, the output value becomes N8. Here, the method of offset correction and full-scale correction will be explained for the case where the actual conversion characteristic is as shown in FIG. Conversion characteristics (
In the case of →, as a result of M positive due to the zero force, an error ΔNbbs1 with respect to the true biholer high frequency number N b b a is obtained. If the coefficient of the coefficient circuit is 1, this ΔNbb・1 If the above-mentioned offset compensation is performed, the conversion characteristic should be translated in parallel to the same figure (c), but since the offset is the result of multiplying the coefficient by 91 in the coefficient circuit, the result of offset compensation is ΔN bbal
/Kyo (translated in parallel to the same figure), it is not completely compensated for. If the above-mentioned full scale correction is performed in this state, the full scale output error ΔN will occur. 1 is compensated and changes to the characteristic shown in the same figure). This completes one cycle of offset correction and full-scale correction, but as a result, the initial bipolar offset error ΔNb is ΔNbba2
It has been reduced. Therefore, by repeating the above correction cycle, both errors become infinitely small and the objectives of both compensations are achieved.

As explained in detail above, in the present invention, offset errors and gain errors occurring during conversion are accurately compensated for by digital or analog means. Therefore, MOS (MetalQxide Sem1c
High precision can be obtained even when integrated on a semiconductor with poor analog performance, and precision can be ensured even when the capacitance value of a capacitor is reduced. As a result, no external parts are required and L'f
It becomes possible to realize a cA/D converter, and an extremely large effect can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an example of a conventional converter, FIGS. 2 and 3 are time charts for explaining the operation of FIG. 1,
Figure 4 is a configuration diagram showing one embodiment of the present invention, Figures 5 and 6.
7, 8, and 9 are partial configuration diagrams of FIG. 4, FIGS. 10 and 11 are time charts explaining the operation of the circuit in FIG. 4, and FIGS. 12, 13, Figure 14, Figure 15,
FIG. 19 is a diagram showing A/D conversion characteristics for detailed explanation of the present invention, FIG. 16 is a diagram showing a conversion cycle, and FIG.
FIG. 18 is a flowchart showing an offset compensation method.
The figure is a flowchart showing a full-scale compensation method. 2... operational amplifier, 3... comparator, 4...
Clock generation circuit, 7... Latch circuit, 11... Preamplifier, 12... Reference voltage generation circuit, 13... Clock control circuit, 14... Offset counter, 15
...Coefficient circuit, 16...Output counter, 17...
Coefficient setting circuit, 18 - Compensation voltage generation circuit, 20-2
3...Buffer amplifier. 10th 4th Ego 2[:l 謬 3 口 50th 33rd 60th <=1 k'L th 70th 8th 9th calm 10th... Moku 160 17th Prisoner 180 Mei 19th Prisoner-VF OtVF

Claims (1)

[Claims] 1. A V/f conversion circuit using an integrating circuit that converts an analog input signal into a pulse signal, a counter that counts the pulse signal of this V/f conversion circuit, and this color/recount value corresponds to the analog input signal. an output circuit that outputs a digital value, a means for applying a reference voltage to detect the offset amount of the V/f conversion circuit, and a pulse signal corresponding to the offset amount of the V/f conversion circuit that is counted and stored as a digital signal. An A/D converter characterized in that it is also configured with offset compensation means.