JPS5840706B2 - Electronic scanning ultrasonic deflection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultrasonic deflection device for electronically scanning an ultrasonic beam.

Conventionally, the deflection of an ultrasound beam has been done by applying a time difference between each transducer (hereinafter referred to as "element") of a plurality of (N pieces, N is an integer) ultrasonic transducers (transducers) arranged in an array. A method of deflecting an ultrasound beam by giving a
(See x' 68, P, 153~)C Fig. 1 is a diagram showing the main part configuration of the above-mentioned conventional ultrasonic deflection device.

In the figure, 1, 2, 3, songs...N is the element number, 13 is the adder, 14 is the output terminal, is
[1s-i, 1s-2,...15-(N-1)
”] is a variable delay circuit, 16C16-2゜16-3,・
. . . l6-N) is a compensation delay circuit.

An adder 13 sequentially adds the delay times of (N-1) variable delay circuits 15 inserted between adjacent elements,
The ultrasonic beam is deflected by giving equivalently different delay times to each element (hereinafter referred to as the "differential method").
It is structured as follows.

This conventional differential method has a problem in that control is complicated and the device is therefore complicated.

In order to simplify the above control, the inventors of the present application previously filed Japanese Patent Application No. 50-135082 (% Publication No. 56-42293).
We proposed a control method using the quantized difference method as "ultrasonic transducer control method and device".

The principle of this method is that when the deflection angle θ is made to have directivity, the ideal delay time between adjacent elements is τθ, this τθ is quantized with a delay time τ0, and the quantized delay time given to the element l is In τi, [ ] represents rounding down to the decimal point.

Next, the difference value τi+1-τ1 (i=0.1, 2..., N-
1) (hereinafter referred to as a quantized difference value) and provides it to the variable delay circuit.

The most suitable form of this quantized difference method is to divide the quantized difference value by τθ.

Quantized difference code (all 0.
It is represented by one signal.

This is a method of controlling the delay time by storing this in the memory.

For wave reception control, the quantized difference code is used as a tap terminal selection signal of the variable delay circuit.

In addition. The angle range of τθ>τ0 will be described in the embodiments of the present invention.

The quantized difference method has a simpler circuit configuration than the conventional difference method, and is therefore particularly effective as a received wave deflection method.

However, this quantized difference method is different from the conventional difference method (Figure 1).
Similarly, since this method sequentially adds the delay times between adjacent elements, it has the following drawbacks in principle.

That is, first, one variable delay circuit 15 [15-1°15-2
, . . . 15-(N-1)') for each delay time is multiplied to the (N-1) power (N is the number of elements), resulting in deterioration in the performance of the received wave deflection system.

For example, if one variable delay circuit has an amplitude reduction of, for example, a factor of 5, the amplitude decreases to (0,95)16×100=44 factors when N=16.

This apparently means that each received signal is weighted and added, but when the weight is 100 to about 70, it does not affect the directivity of the reception method, but when it is less than 70%, half of the main beam is The resolution is degraded to increase the value range.

Second, as in the ordinary differential method, the fixed delay times of the variable delay means button and the adder are sequentially added, so in order to obtain a deflection angle in the zero direction, the compensation delay circuits 16-2, 16-3,
...16-N is required.

The compensation delay time CTi (i=2 * 3 m...
...N) where tl: Fixed delay time of the variable delay circuit t2: Fixed delay time of the adder.

The reason why the coefficient of t2 is (i 2) is that the connected adder is not included and is the delay time of the adder in the preceding stage.

That is, CTi only needs to correct the delay time before the adder.

For example, when t1=5 ns, i2=Ions, and the number of elements N=30, the maximum compensation delay time is CT
3o=425 nS.

Therefore, in order to configure a receiving circuit using the quantized difference method, a compensating delay circuit having a relatively large amount of delay is required.

Taking these points into consideration, the present invention utilizes the quantized difference method more effectively, and the delay time based on the quantized difference value is applied to multiple receiver circuits arranged in parallel. The purpose is to apply control and improve the characteristics of the received wave deflection device.

The present invention will be explained below using the drawings.

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.

In the figures, the same reference numerals as those mentioned above indicate the same or equivalent parts.

11 is a compensation amplifier, and 18 is a variable delay circuit for phasing.

To simplify the explanation, the number of elements N is assumed to be an even number, and the number of parallel columns is assumed to be two.

As you can see from the figure, the present invention c′ introvert device odd number 0
"'to.

(M pieces) and 7 pieces (M pieces) of even-numbered Niremen form a group, and a variable delay circuit 15 (first variable delay means) is interposed between adjacent elements belonging to each group. They are connected in cascade, and the outputs of each of the above groups are connected in parallel with a variable delay circuit 18 (second variable delay means) for phasing interposed therebetween, and the terminal outputs of each group are added after phasing. It is something.

Then, the variable delay circuit (15-
1, 15-3, ...) and the variable delay circuit of the other group of elements (15-2, 15-4, ...)
are controlled by the same quantized difference code.

16-3 to 16-N are compensation delay circuits, and 16-1
and 16(i+1) (i=3 to (N-1)) have the same delay time, and the delay time of 16-N may be the same as in the conventional system (FIG. 1).

Reference numeral 18 denotes another variable delay circuit (for phasing), which controls the delay time τ at the deflection angle θ to be τ=−sinθ (2)'■, so that d: the transducer spacing.

According to such a configuration, the addition outputs of - (M) variable delay circuits (15-1, 15-3, . . . ),
- (M) variable delay circuits (15-2.

15-4, . . . ) are phase-matched by the variable delay circuit 18 and output.

Therefore, there is an advantage that the amplitude fluctuation, which was conventionally raised to the power of (N-1), is reduced to the power of (N-1)/L (where L=2) in this embodiment.

FIG. 3 shows an example of the variable delay circuit 15 (first variable delay means) shown in FIG.

The memory 29 stores the aforementioned quantized difference code for each deflection angle.

Then, the oscillation pulses of the oscillator 26 are counted by a counter 28, and a quantized difference code corresponding to a predetermined angle is read out according to the contents thereof, and becomes a delay time control signal for each variable delay circuit.

The variable delay circuit 15 shown in FIG. 2 is composed of an 8-tap LC delay line 23 with a maximum delay time of, for example, 400 ns, a switching circuit 24 having 8 impedance matching resistors 21 and 22, and a shift register 25. .

With the above configuration, a quantized difference code corresponding to a predetermined angle is preset in the shift register 25 without being changed.

After this, set the serial input terminal RI to O and τθ/
The clock pulse of τ0 (rounded down to the nearest whole number) is connected to terminal C.
Add to P.

Regarding this τθ/τ0, it is sufficient to supply the contents of the counter 28 with a predetermined bit or more to the counter 27, and input the serial output of the counter 27 to the terminal CP.

The switching circuit 24 is controlled by each output of the shift register 25 obtained in this way.

By adopting such a configuration, 15-1 in Figure 2
and 15-2, 15-3 and 15-4,...15
-(N-1) and 15-N can each be controlled by the same quantization difference code (same control signal).

FIG. 4 is an example of the variable delay circuit 18 (second variable delay means) shown in FIG.
LC delay line with 10 taps of ns, 33-2 is an LC delay line with 3 taps with a maximum delay time of, for example, 150 ns, 3
4-1 and 34-2 are respectively 10 and 4 switching circuits, 31-1゜31-2.32-1 and 32-2
Impedance matching resistors, 35-1 and 35-2 are binary to decimal converters (BCD to Decimal decoders), 36-1 and 36-2 are BCD counters,
37 is a signal input terminal, 38 is a signal output terminal, 39 is BC
The input terminal 40 of the D counter 36-1 is a reset terminal.

If such a configuration is adopted, the BCD counter 36-
After resetting 1.36-2 with the control signal input from terminal 40, the BCD counter is incremented by the control signal input from terminal 39, and the binary-decimal converter (BCD
to Decimal decoder) 35-1.35-2
decimal conversion is performed, and one gate for each of the switching circuits 34-1 and 34-2 is turned on.

The signal input from the terminal 37 becomes negative in amplitude by the matching resistor 31-1, and after being delayed by =5 ns step by the variable delay circuit 33-1, it passes through the switching circuit 34-1 and is sent to the next stage matching resistor 31-1. Enter 2.

Similarly, the input signal of the matching resistor 31-2 has a negative amplitude and is outputted to the output terminal 38 via the switching circuit 34-2 after being delayed by =50 ns steps by the variable delay circuit 33-2.

Here, the amplitude becomes negative, but it can be corrected by placing a quadruple amplifier afterwards.

In this way, a delay time of 40 steps is possible depending on the control signal.

After dividing into , it is sufficient to add them by phase matching.

In this example, the variable delay time between every single element was controlled, but LXM elements (L,
M is an integer) among the elements L-1 ('L=3.4
,5. It is clear that it is effective to control M discrete elements using the same quantized difference code and then add them by phase matching.

At this time, the output of each of the L groups controlled by the same quantization difference code is C
2) Since there is a delay equal to the delay time of equation 1, there is a differential method shown in FIG. 5a as a phase matching method.

That is, 50-1 to 50-ri are L groups controlled by the same quantization difference code.

51-1 to 5l-(L-1) are variable delay circuits which are controlled by one control signal so as to have the above-mentioned delay time τ.

52 is an adder, and 53 is an output terminal. It is also obvious that control may be performed in parallel as shown in FIG.

Here, 54-1 to 54-(L-1) are variable delay circuits, 5
5 is an adder.

In this case, the delay time τ for phase matching. Each of them needs to be constructed using, for example, the circuit shown in FIG.

As explained above, in the deflection device of the present invention, the elements (N) are arranged in parallel in groups (L), and the quantized difference method is effectively applied, thereby reducing the delay time of the variable delay circuit in the conventional manner. It is possible to reduce the result obtained by multiplying the amplitude fluctuation by (N-1) to (N-1)/L.

Also, the delay time of the compensation delay circuit is 1/1/1 compared to the conventional method.
Since it becomes L, the frequency characteristics of the delay circuit can be improved and costs can be reduced.

Furthermore, there is an advantage that the control signals when controlling the variable delay circuit using the quantized differential code are simplified by the parallel (ie, 1/L).

Further, there is an advantage that the labor for circuit adjustment is greatly reduced.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the main part configuration of a conventional ultrasonic deflection device, Figure 2
The figure is an explanatory diagram of the main part configuration of the electronic scanning ultrasonic deflection device of the present invention, FIGS. 3 and 4 are explanatory diagrams of the configuration of the first and second variable delay circuits according to the present invention, respectively, and FIG. FIG. 2 is an explanatory diagram of a method for adjusting the phase of each grouped output according to the present invention, in which a shows a differential method and b shows a parallel method. 1.2,3. ...N...Element number, 11...Compensation amplifier, 13...
・Adder, 14...Output terminal, 15[15-1
,15-2,...15-(N-1))...
...Variable delay circuit, 16 [16-2, 16-3,...
...16-N] ... Compensation delay circuit, 18.
...Variable delay circuit.

Claims (1)

[Claims] 1. In order to give an array type ultrasonic transducer consisting of LXM (L and M are positive integers of 2 or more) elements arranged in an array a directivity of a predetermined deflection angle, the elements are given a predetermined delay time. When giving and excitation or receiving,
In an electronic scanning ultrasonic deflection device, the delay time of the element is controlled by a quantized difference value obtained by calculating the difference in quantized delay time between adjacent elements between all the elements, and the LXM elements are controlled by (L- 1) Select M pieces at intervals and divide them into L groups, and compensate the fixed delay time with a fourth variable delay means controlled by the quantized difference value within the group between adjacent elements in each group. After phasing the M received signals, a second variable delay means for phasing the respective outputs of each group is interposed and connected in parallel. Shi, L
An electronic scanning ultrasonic deflection device characterized in that it is configured to phase all received signals of XM elements.