JPS5839338A - Logical circuit with two-way element - Google Patents

Abstract

PURPOSE:To separate respective logical circuits from a full-logical circuit, and to improve the resolution of a fault by providing a two-way element with a returning function to every external signal terminal, and allowing the elements to function in returning mode for a test of the assembly of the logical circuits. CONSTITUTION:On one substrate of a package wherein a logical scanning circuit for logical circuits 40 and 41, etc., is incorporated, two-way communication type system terminals 91-94, one-way communication type system terminals 90 and 95, a shift input terminal 96, a shift output terminal 97, etc., are provided. A 4-bit number supplied externally to the terminals 91-94 is accumulated by an accumulator 10 through two-way elements 21-24, and the accumulation result is sent out to the terminals 91-94 through register circuits 34-37. A starting signal is supplied externally from the terminal 90 to the accumulator 10, and a carry signal from the accumulator 10 is sent out from the terminal 95. During a test of the assembly of the logical circuits, the two-way elements 21-24 are used as returning-mode function elements by an external signal to separate each logical circuit from a full-logical circuit.

Description

[Detailed description of the invention] The present invention relates to a logic circuit with bidirectional elements.

In particular, the present invention relates to a logic circuit with a bidirectional element, in which individual testing of each logic circuit may be performed under an aggregate state of a plurality of logic circuits.

Such an aggregate of multiple logic circuits is, for example, a logic circuit package in which a logic circuit is housed in an integrated circuit case and multiple integrated logic circuits are mounted on a circuit board, or a logic circuit in which a logic circuit is expanded on a circuit board. A logic device is a logic device in which a plurality of logic circuit packages are mounted in a housing or the like.

In such an aggregate state of multiple logic circuits, even if you try to test or diagnose one logic circuit, the logic circuits are connected to each other by the external word terminals of each logic circuit. However, due to the influence of other logic circuits, individual testing and diagnosis of logic circuits is not easy.

It was tested using the following test method without having a configuration designed to facilitate individual testing, especially under aggregate conditions. There is.

One of the test methods is to use online test pattern data (for example, a test program) that is different from test pattern data (for example, logic circuit package pattern data) using a logic circuit offline tester.

A child program (Te5t Program, etc.) is created in advance and tested individually under an aggregate condition. In such testing methods, the resolution of failures is limited to logic circuits at most, test data for analyzing the inside of logic circuits cannot be obtained, the test time is relatively long, and pattern data for online testing is required. It has many disadvantages, including the cost of production.

Another test method is to take a logic circuit out of the assembly and test it with a logic circuit off-line tester. In this test method, as the number of input/output terminals has increased significantly in recent years due to high integration, it is not easy to attach and detach logic circuits to the assembly, and it is difficult to install an offline tester in a short time. If it cannot be procured, the turnaround time from testing to repair will be longer, and on the other hand, there is a drawback that it is necessary to increase the number of offline testing machines to enable short-term procurement.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a logic circuit which can obtain an effect comparable to that of an individual test of logic circuits using an offline tester under an aggregate condition of a plurality of logic circuits.

The circuit of the present invention is a logic circuit with a built-in scanning path for testing, which is provided in a one-to-one correspondence with an external signal terminal, and has one outer terminal and two inner terminals connected to each terminal, and has a bidirectional folding function. The present invention is characterized in that it includes a bidirectional element and a terminal for externally supplying a return instruction signal to all of the bidirectional elements with a return function.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment has a 4-bit accumulator 10, 4 input register circuits 30 to 33, and 4 output register circuits 3.
4 to 37, bidirectional elements 20.25 and register circuits 39.38 added to each of the unidirectional communication type system terminals 90 and 95, and each of the bidirectional communication type system terminals 91 to 94. This is a logic circuit composed of bidirectional elements 21 to 24 and AND circuits 40 and 41 added to the logic circuit. Here, a unidirectional communication system terminal refers to a system terminal that is used only for either an input signal or an output signal during normal operation of this logic circuit, and a bidirectional communication system terminal refers to a system terminal that is used for both input and output signals. Refers to the system terminal used for In the figure, a dotted line starting from the shift input terminal 96 and connecting ten register circuits 30 to 39 in series to the shift output terminal 97 indicates a scan path. The portion where the scan path overlaps the signal line for normal operation is shown by a solid line.

FIG. 2 is a detailed circuit diagram of the register circuits 30 to 39 shown in FIG.
, 43N, OR circuit 6N and flip-flop 7N
It consists of N indicates a number from O to 9 corresponding to the first digit of the register circuits 30 to 39. Reference symbol 9
8N' is a clock obtained by ANDing 98' and the package designation signal 99' in FIG.
N' indicates a signal supplied to the register circuit corresponding to each of the mode designation signals 9, but is not shown in FIG. 1 to avoid complicating the circuit. This register circuit selects whether the function signal F or the shift signal S is clocked 98 in response to whether the mode designation signal 9AN/ is logic 101 or 81m.
N' is set in the shift flip-flop 7N.

FIG. 3 is a detailed circuit diagram of the bidirectional elements 20 to 25 shown in FIG. 1, including two AND circuits 44M.

45M, exclusive OR circuit 8M, threshold level converter 10
M and a reader 11M.

M refers to a number from θ to 5 corresponding to the first digit of the bidirectional elements 20 to 25. Reference symbol 9BM' indicates that the folding instruction signal 9B' in FIG. 1 is supplied to the corresponding bidirectional element. The two inner terminals 14M and 15M are connected to the output terminal 13N of the aforementioned core logic circuit or added register circuit 38, 39, and the outer terminal 16M is connected to the system terminals 90-95 shown in FIG.

This bidirectional element is an improved version of a commercially available three-value logic type bidirectional element (separate patent pending) consisting of two AND circuits 44M, 45M, a threshold level converter 10M, and a reader 11M. Its operating principle is as follows.

When the return instruction signal 9BM' is logic els, in response to whether the logic value of the inner terminal 14M is 101 or 111, the threshold level converter 10MFi sets -0, 9 volts and -0, 3 volts as the thresholds, respectively, to the interpreter 11M. supply to. If the logic value of the inner terminal 14M is 101, then the logic value of the inner terminal 14M of another logic circuit package to which the outer terminal 16M is connected via the system terminal is 101 or 11.
1, the potential of the outer terminal 16M becomes 0 volts or -0, 6 volts, respectively, but since both are higher potential than the threshold value -0, 9 volts in this case, the reader 11M detects the inner terminal 14M. The logical value °0°, which is the same as the logical value of , is output to the inner terminal 15M. Also, the logic value of the inner terminal 14M is 1
11, the outer terminal 16M is connected to the outer terminal 16 in response to whether the logic value at the inner terminal 14M of the other logic circuit package connected via the system terminal is IQI or 111.
The potential of M is -0.6 volts or -1.2 volts, respectively, but since both are lower than the threshold value of -0.3 volts in this case, the logic is the same as the logic value of the reader 10MFi inner terminal 14M. Outputs the value "1m" to the inner terminal 15M.

That is, in either case, the present bidirectional element becomes unrelated to the external signal and returns its own input signal as it is as an output signal.

When the return instruction signal 9BM/ is logic 101, the exclusive OR circuit 8M does not invert the logic value of the internal information terminal 14M, so it has no relation to the logic value of the internal terminal 14M in the pixel element, and the external terminal 16M is It operates to output the logic value of the inner terminal 14M of another logic circuit package connected thereto to the inner terminal 15M in the pixel element. In other words, the same element correctly performs transmission and reception at the same time, resulting in bidirectional communication.

Now, as shown in FIG. 1, the original function of the logic circuit is to accumulate the 4-bit number supplied from the outside via the bidirectional communication type system terminals 91 to 94 using the accumulator 10, and to obtain the result. The cumulative number to be written is written to two-way communication system terminals 91 to 9.
4. Sending the carry signal to the outside via the unidirectional communication type system terminal 95. Another unidirectional communication type system terminal 90 is used to externally supply a starting signal for the accumulation to the accumulator 10, and a flip-flop 7N is an input/output terminal for the accumulator 10 in the above-mentioned accumulation process. Functions as a register.

By adding circuits such as bidirectional elements 20 to 25 to the core logic circuit having such original functions, a logic circuit configured as shown in Fig. 1 was developed on a single circuit board. Multiple logic circuit packages are mounted in a housing, and each system terminal is interconnected between each logic circuit package.
Consider the case where individual logic circuit packages are tested in a state where one logic device is configured. In this situation, during the production process and during product shipping and maintenance, when a logic device makes an error, an auxiliary device that constitutes the same information processing device together with the logic device and has multiple uses, such as a service processor (hereinafter referred to as a service processor) This is a case where the above-mentioned logic circuit package is tested and fault-diagnosed using , SP). The procedure is described below.

■SvP sets the return instruction signal 9-B' to logic "I",
Signal isolation of each logic package from all other logic circuit packages. '8VP designates the logic circuit package to be tested by the package designation signal 99', and prepares to operate so that only the designated logic circuit package receives the signal 98'.

(2) In SvP, the mode designation signal 9A' is set to logic 111, and each register circuit 30 to 39 prepares to operate in the shift mode, that is, to set the shift signal S to 7 ripflops and 7n.

(2) The 8VP supplies pattern data from the shift input terminal 96 to each register circuit 30 to 39 and the accumulator 10 through the scan canvas while adding clocks and signals 98'.

■8VP sets mode designation signal 9A' to logic @O'KL.

Each of the register circuits 30 to 39 then prepares to operate in the normal operation mode, that is, to set the function signal F to the flip-flop 7NK.

(2) For SvP, one black and one 98' are added, and the test results of the core logic circuit are set in 7s, pflo, and p7N, respectively.

■ Return to shift mode again (same as ■).

(2) In SvP, the logic circuit package designated by the package designation signal 99' reads the test data stored in each FRI, BUFLO, and P7N from the shift output terminal 97 while applying the clock 98'.

(2) 8VP compares the test data with correct data determined in advance.

[Phase] SvP returns to step ① again, and steps ① to ① are repeated as many times as necessary.

@svp indicates whether the logic circuit package designated by the package designation signal 99' is correct or not and the location of the failure based on the results up to step 0.

@svp returns to step ① and moves on to testing the next logic circuit package.

As described above, the present invention includes a bidirectional element with a folding function for each external signal terminal, and the external terminal is connected to the external signal terminal, and the bidirectional element is By employing a configuration that functions in the loopback mode, each logic circuit can be separated from all other logic circuits in terms of signals, so the first effect is that the resolution of failures is improved.

The second effect of the present invention is that the test time can be shortened due to the same reason as the first effect.

The third effect of the present invention is that pattern data created by an offline testing machine can be reused, thereby reducing pattern data creation costs.

In addition, compared to other conventional methods in which an offline testing machine is procured for testing under an aggregate state of logic circuits, and the logic circuit under test is taken out from the assembly and tested using the offline testing machine, the present invention The first effect is that there is no need to procure offline testing equipment. 8VP mentioned above
etc. have purposes other than testing logic circuits.

Next, the second effect is that the increased number of input/output terminals due to the increased density of logic circuits eliminates the need for the difficult work of attaching and detaching from the assembly.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the present invention, and FIGS. 2 and 3 show partial details of the embodiment shown in FIG. 1, respectively. In the figure, 10...accumulator, 20-25...
...Bidirectional element, 30-39...Register circuit, 40°41.42N, 43N, 44M, 45
M: AND circuit, 5N: NOT circuit, 6N: OR circuit, 7N: Free, rough 0. 8M...Exclusive OR circuit, 9
0.95...Unidirectional communication type system terminal, 91~
94...Bidirectional communication type system terminal, 96...
...Shift input terminal, 97-...Shift output terminal, 98', 98N'...Clock, 99/...
---Package designation signal, 9A', 9AN'・
...Mode designation signal, 9B', 9BM'...
...Return instruction signal, IOM...Threshold level converter, 11M...Reader, 13N...Output terminal, 14M, 15M...Inner terminal, 16M...
...Outer terminal, F...Function signal, S...
...Shift signal.

Claims (2)

[Claims] (1) In a logic circuit with a built-in scanning path for testing, a bidirectional element with a folding function is provided in one-to-one correspondence with external signal terminals and has one outer terminal and two inner terminals connected to each terminal. A logic circuit with a bidirectional element, comprising a terminal for externally supplying a return instruction signal to all of the bidirectional elements with a return function. (2) 1 bit corresponding to each unused inner terminal of the bidirectional element with folding function provided in the unidirectional communication type external signal terminal among the external signal terminals. A memory element for storing information is provided in advance, and the memory element is incorporated into the test scanning path.
1) Logic circuit with bidirectional element described in item 1).