JPS5839123A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPS5839123A JPS5839123A JP56137436A JP13743681A JPS5839123A JP S5839123 A JPS5839123 A JP S5839123A JP 56137436 A JP56137436 A JP 56137436A JP 13743681 A JP13743681 A JP 13743681A JP S5839123 A JPS5839123 A JP S5839123A
- Authority
- JP
- Japan
- Prior art keywords
- output signal
- down counter
- phase
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Abstract
Description
【発明の詳細な説明】
本元９Ｉ４はＰ Ｌ Ｌ （Ｐｈａｓｅ １ｏｃｋｅｄ
１ｏｏｐ）回路に関する。[Detailed description of the invention] The original 9I4 is PLL (Phase 1ocked
1oop) circuit.
従来のｌ”ｌ、Ｌ（ロ）路線、纂ｌ、纂２図に示す如き
構成に成っていて電圧制御型発振擬（ＶＣＯ）はアナロ
グ電圧で制御さｎてい念。上記アナログ電圧は位相比較
回路１−２の出力信号をローパスフィルター１−３ｔ−
通す事により位相誤差電圧に変換し、上記位相誤差電圧
で第２図に示すバリキャップ（Ｖａｒｉａｂｌｅ Ｃａ
ｐａｃｉｔａｎｃｅ）２−６ ｆ：制御していた。バリ
キャップ２−６１−制御する位相誤差電圧がアナログ電
圧でめる為、ノイズに弱い欠点があった。Conventional l"l, L (b) lines, the configuration is as shown in Figures 1 and 2, and the voltage-controlled oscillator (VCO) is controlled by an analog voltage.The above analog voltage is used for phase comparison. The output signal of circuit 1-2 is passed through a low-pass filter 1-3t-
The phase error voltage is converted to a phase error voltage by passing through the variable cap as shown in Fig. 2.
pacitance) 2-6 f: Controlled. Varicap 2-61 - Since the phase error voltage to be controlled is determined by an analog voltage, it has the disadvantage of being susceptible to noise.
本姥明は従来の欠点ｔ−鑑み、ノイズに対して影曽を受
けに（？ＰＬＬ回路を提供する事を目的とするものであ
る。In view of the drawbacks of the conventional circuit, Akira Motoba's purpose is to provide a PLL circuit that is immune to noise.
即ちプログラマブルディバイダーの出力信号と。That is, the output signal of the programmable divider.
基準周波数とを位相比較した出力信号でアップダウンカ
ウンターのアップカウントモード又はダウンカウントそ
−ドを設定する手段と前記位相比較した出力信号で前記
アップダウンカウンターのりｐツク信号を発生せしめる
手段と前記アップダウンカウンターの出力信号により複
数個の静電容量を切換える手段とを具備し、前記静電−
にでＶα」を構成した事を特徴とするものである。means for setting the up-count mode or down-count mode of the up-down counter using the output signal whose phase is compared with a reference frequency; means for generating the up-down counter's output signal from the output signal whose phase has been compared; and the up-down counter's output signal. means for switching a plurality of capacitances according to the output signal of the down counter,
It is characterized by the fact that it is composed of "Vα".
本発明によｎば、従来の如きアナログ電圧で■Ｃ０１−
制御するのではなく、ｗ電容菫會ディジタル的に変化さ
せるものである為、ノイズに対して強いＰＬＬ回路が得
ら扛る。According to the present invention, ■C01-
Since the capacitance is changed digitally instead of being controlled, a PLL circuit that is resistant to noise can be obtained.
次に実施例を用いて詳細に説明する。第３図は本発明の
一夾施例であり位相比較回路部３−２の出力信号でアッ
プダウンカウンター３−９を制御し、さらにアップダウ
ンカウンター３−９の出力信号でディジタルＶＵＯ３−
１０を制御する。位相比較回路部３−２の具体例を第４
図にボす。第４図に於いて位相比較回路４−２の出力信
号ＩＵ。Next, a detailed explanation will be given using examples. FIG. 3 shows one embodiment of the present invention, in which an up/down counter 3-9 is controlled by the output signal of the phase comparison circuit section 3-2, and a digital VUO 3-9 is controlled by the output signal of the up/down counter 3-9.
Control 10. A specific example of the phase comparator circuit section 3-2 is shown in the fourth section.
Draw on the diagram. In FIG. 4, the output signal IU of the phase comparison circuit 4-2.
Ｌ）ｌは一率周波に！ｉ、ｆ、 に対し、プログラマ
ブルディバイダーの出力ｆｒが進めば、信号ＩＵ−は。L) l is one rate frequency! If the output fr of the programmable divider advances with respect to i, f, then the signal IU-.
１１ルベル、信号°Ｄ″は、パルス波形が出力さｒＬ、
逆に、上記ｆｒ に対し、上記ｆｒ が遅ｎるとｌ
Ｔ ｌ信号はパルス波形が出力さｎｌ ′Ｌ１１信号は
１１″レベルと成る。11 level, the signal °D'' is a pulse waveform output rL,
Conversely, with respect to the above fr, if the above fr is slow n, then l
The Tl signal has a pulse waveform, and the nl'L11 signal has an 11'' level.
上記＋０１ 、ＩＤｒ信号からアンドゲート４−１１に
より、クロ、り信号ＩＣＫ＝ｉ作り、さらにり四ツク信
号″ＣＫＩで位相比較回路４−２のＪ Ｖ ｌ信号を１
ビツトデータフリツプ７０ツブ４−１２に絖み込ませ、
’ＵＰ／ＤＷ＋信号を発生させル＠ ’ ｆｙ ｔ
ｆ ｒ＊ Ｕ ＊ Ｄ ｔ ＣＫ ＊ ＵＰ／ＬＩＷ’
Ｏ各信４の関係を第６図に示す。第６図に於騒て、＃
Ａ−の領域はプログラマブルディバイダーの出力ｆｖが
、基準周波数ｆｒに対し、遅ｎた状態がら、ｆｒに一致
するまでの状態を示すものであり、１Ｂ′の領域は、ｆ
ｖ が、ｆ、に一致した状態から、ｆｒよりｆｖの位相
が進′む状態を示している。第６図に於いて、従来の方
式では゛Ｕ、Ｄ′信号でチャージポンプを制御し、チャ
ージポンプの出方信号をローパスフィルターでアナログ
電圧に変換していた０本発明は、第５．６図に示すｔｃ
Ｋ、ＵＰ／ＬＩＷ＋信号で第５図に示すアップダウンカ
ウンター５−９を制御するものである。第５図に於いて
。The AND gate 4-11 generates a black signal ICK=i from the above +01 and IDr signal, and furthermore, the JV l signal of the phase comparison circuit 4-2 is set to 1 using the four clock signal "CKI".
Insert it into the bit data flip 70 tab 4-12,
'Generate UP/DW+ signal @' fy t
f r* U * D t CK * UP/LIW'
The relationship between the O signals 4 is shown in FIG. Figure 6 caused an uproar, #
The area A- shows the state in which the output fv of the programmable divider is delayed with respect to the reference frequency fr until it matches fr, and the area 1B' shows the state where the output fv of the programmable divider matches the reference frequency fr.
This shows a state in which the phase of fv leads fr from a state in which v coincides with f. In Fig. 6, in the conventional system, the charge pump was controlled by the 'U and D' signals, and the output signal of the charge pump was converted into an analog voltage by a low-pass filter. tc shown in the figure
The up/down counter 5-9 shown in FIG. 5 is controlled by the K and UP/LIW+ signals. In Figure 5.
アップダウンカウンター５−９の出方は、静電容量切換
えトランジスター５−１３〜５−１３””’のゲートに
入力さｎてぃて、アップダウンカウンター５−９の出方
に応じて静電容量’ｉ切換えるものである。本実施例で
は、１２ビツトのアップダウンカウンターを用いて−る
為、静電容量の組合せは２１″通り、即ち４０９６通り
ある。又、本実施例では、アップダウンカウンター５−
９、静電容量切換えトランジスタ５−１３〜５ １３
ｂ及び静電容量５−１４〜５−１４ ””’ は同
−半導体集積回路上に構成している為上記静電容量は半
導体基板と拡散層から成る接合容ｆ’ｅ用いている。即
ち、拡散層の面積で１個々の静電容量の大きさを制御し
ている。静電容量５−１４が０．１２ＰＩ１１であり、
アップダウンカウンター５−９の出力ＱＭ（２≦Ｍ≦１
２二Ｍは整数）で制御さｎる静電容量は５−１４の２Ｍ
倍の容量値と成っている。The output of the up-down counter 5-9 is input to the gates of the capacitance switching transistors 5-13 to 5-13""', and the output of the up-down counter 5-9 is input to the gates of the capacitance switching transistors 5-13 to 5-13''. The capacity 'i' is switched. In this embodiment, since a 12-bit up/down counter is used, there are 21" combinations of capacitance, that is, 4096. Also, in this embodiment, the up/down counter 5-
9. Capacitance switching transistor 5-13 to 5 13
Since capacitances 5-14 to 5-14 ``''' are constructed on the same semiconductor integrated circuit, the above-mentioned capacitance uses a junction volume f'e consisting of a semiconductor substrate and a diffusion layer. That is, the size of each capacitance is controlled by the area of the diffusion layer. The capacitance 5-14 is 0.12PI11,
Output QM of up/down counter 5-9 (2≦M≦1
(22M is an integer) n capacitance is 5-14 2M
It has twice the capacity value.
従って、本発明による上記構成に基づくと基準周波数ｆ
、に対しプログラマブルディバイダーの出力ｆｖが遅ｎ
ていると、アップダウンカウンター５−９に一アップカ
ウンターそ−ドに設定し。Therefore, based on the above configuration according to the present invention, the reference frequency f
, the output fv of the programmable divider is slow n
If so, set the up-down counter 5-9 to one up counter.
（＝［ＪＰ／ｌ）Ｗｔ 信号がｌｌＪレベル状ｕ’）−
ｆｖがｆｒに一致するまでアップダウンカウンター５−
９は、アップカウントを続ける。即ち、靜電答黛ヲディ
ジタル的に増加させ、ｆｖとｆｒ が一致するまでＶＣ
Ｏの発振周波数を減少させる（第６図の＋Ａ＋領域）。(=[JP/l)Wt signal is at llJ level u')-
Up-down counter 5- until fv matches fr
9 continues counting up. In other words, digitally increase the response rate and increase VC until fv and fr match.
Decrease the oscillation frequency of O (+A+ region in FIG. 6).
同、ＶＣＯの発振周波数ｆ。ｕｔ１Ａ はｆ。ｕｔ”（”ＣＶ） の関係がめる。ここに。Similarly, the oscillation frequency f of the VCO. ut1A is f. ut" ("CV)" relationship. Here.
ｒ ｌ、 ｓは１例えば第２図に示すＶＣＵのコイル２
−７に相当するものでおゐ。ｆｖがｆｒ と一致する
と、アップダウンカウンター５−９は停止する。r l, s are 1. For example, coil 2 of the VCU shown in FIG.
It's equivalent to -7. When fv matches fr, the up/down counter 5-9 stops.
又、逆に、ｆｖがｆｒ より位相が進むと、アップダ
ウンカウンター５−９は、ダウンカウントモードに設定
さ３． （ｆＬＪＰ／１）Ｗｔ 信号は一θ゛レベ
ル状態）アップダウンカウンター！５−９はダウンカウ
ントを絖は静電容量をディジタル的に減少させ、ｆｖと
ｆｒが一致するまでＶＣＯの発振周波数を高める。Conversely, when fv leads fr in phase, the up/down counter 5-9 is set to down count mode.3. (fLJP/1) Wt signal is at 1θ゛ level) Up-down counter! 5-9 is a down-counter that digitally reduces the capacitance and increases the oscillation frequency of the VCO until fv and fr match.
又、従来の方式では、静電容量として、バリキャップを
用いていた為＊ ａｇ ７図に示す如＜、 Ｖｌ；０の
発振周波数ｆ。ｕｔと、ＶＣＯの制御電圧との関係がＩ
ＩＬ？ｍ的に出来ない欠点が６うた。第２−の実施例に
よｎ ｉｔ’ ｈ静電容量５−１３〜５−１３’°°°
′の値￥調整する事により、第８図に示す如くｆ。ｕｔ
とアップダウンカウンターのカウント値の間に。In addition, in the conventional system, since a varicap was used as the capacitance, *ag As shown in Figure 7, the oscillation frequency f of Vl; 0. The relationship between ut and the VCO control voltage is I
IL? There are 6 songs that can't be done. According to the second embodiment, capacitance 5-13 to 5-13'°°°
By adjusting the value of ', f as shown in Figure 8. ut
and the count value of the up-down counter.
直線的な関係が得らｎる。A linear relationship is obtained.
第１図は従来のＰＬＬ回路のブロック図を示し。
第２図は従来０ＶｃＵの一例を示し、誦３図は本釦明に
よるＰＬＬ回路のブロック図を示し、第４図は本実施例
の位相比較回路部を示し、第５図は本′！Ａ′ｍ例の■
ＣＯ制御回路部を示し、第６図は各種信号の関係を示し
％第７図は従来の方式のｆ。ｕｔ−Ｖの関係を示し、第
８図は第２０実施例による’ｏｕｔ−カウント櫨の関係
を示すものである。
ここに＊ ｌ−１ｔ ３−１・旧・・プログラマブルデ
ィバイダー、１２ｓ３−２・旧・・位相比較回路部。
１−３・・・・・・ローパスフィルター、１−４・・・
・・・Ｖ−Ｃ（Ｊ、２−５・・・・・・抵抗、２−６・
・・・・・バリキャップ、２−７・・・・・・コイル、
２−８−・・°°°コンデ／？−，３９ｙ５ ９・・・
・・・アップダクンカクンメー、３−１０ ・−１・”
Ｖ Ｃ（Ｊ、 ４−２−−−−−−位相比較器、４−
１１・・・・・・アンドゲニ）ｂ ４−１２・・・・
・ザータ７リップ７０ツブ、５−１３〜５−１３””’
°旧・・静電容量切換えトランジスタ、５−１４〜５−
１４”＠１拳り・・・静電容量
である。
第 １ 凶
躬 ２ 凹
−ｑ
−Ａ、、−７３−ｍ−÷
躬 ６図
第７図
カランＦ４Ｉ 掬う・ ８ 図FIG. 1 shows a block diagram of a conventional PLL circuit. Figure 2 shows an example of the conventional 0VcU, Figure 3 shows a block diagram of the PLL circuit according to Akira Honka, Figure 4 shows the phase comparator circuit section of this embodiment, and Figure 5 shows Hon'! A'm example ■
The CO control circuit section is shown, FIG. 6 shows the relationship between various signals, and FIG. 7 shows the f of the conventional system. The relationship between ut and V is shown, and FIG. 8 shows the relationship between 'out and count according to the 20th embodiment. Here *l-1t 3-1: old programmable divider, 12s3-2: old: phase comparator circuit section. 1-3...Low pass filter, 1-4...
...V-C(J, 2-5...Resistance, 2-6.
...Varicap, 2-7...Coil,
2-8-...°°°conde/? -,39y5 9...
...Updakunkakunmee, 3-10 ・-1・”
V C (J, 4-2-------Phase comparator, 4-
11...andogeni) b 4-12...
・Zata 7 lip 70 tube, 5-13 ~ 5-13""'
° Old... Capacitance switching transistor, 5-14 ~ 5-
14"@1 fist...It is capacitance. 1st error 2 concave -q -A,, -73-m-÷ 6 figure 7 figure F4I scoop 8 figure
Claims (1)
とを位相比較した出力信号で、アップダウンカウンター
のアップカウントモード又はダウンカウントモードｔ−
設斌する手段と、前記位相比−した出力信号で、前にア
ップダウンカウンターのクロック信号ｔ−ｍ生せしめる
手段と、前記アップダウンカウンターの出力１１号によ
り板数１−の靜電容菫を切換える手段とを具備し、前記
靜１ｇ’４Ｍで尭振器を構成したことｔ特徴とするＰＬ
ＬＶｊＵ略。An output signal obtained by comparing the phase of the output No. 1d of the programmable divider and the reference frequency.
means for generating a clock signal t-m of an up-down counter using the phase-ratio output signal, and switching a board number 1- of the 1- board clock signal t-m by the output No. 11 of the up-down counter. A PL characterized in that the vibration shaker is comprised of the above-mentioned quietness 1g'4M.
LVjU abbreviation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56137436A JPS5839123A (en) | 1981-09-01 | 1981-09-01 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56137436A JPS5839123A (en) | 1981-09-01 | 1981-09-01 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5839123A true JPS5839123A (en) | 1983-03-07 |
Family
ID=15198573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56137436A Pending JPS5839123A (en) | 1981-09-01 | 1981-09-01 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5839123A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0476585A2 (en) * | 1990-09-18 | 1992-03-25 | Fujitsu Limited | Reference delay generator and electronic device using the same |
-
1981
- 1981-09-01 JP JP56137436A patent/JPS5839123A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0476585A2 (en) * | 1990-09-18 | 1992-03-25 | Fujitsu Limited | Reference delay generator and electronic device using the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5144156A (en) | Phase synchronizing circuit with feedback to control charge pump | |
| US4546330A (en) | Phase-locked loop circuit | |
| US5694089A (en) | Fast frequency switching synthesizer | |
| US4587496A (en) | Fast acquisition phase-lock loop | |
| JP3094977B2 (en) | PLL circuit | |
| JP2985489B2 (en) | Phase locked loop | |
| SE516301C2 (en) | N-fractional frequency synthesis with residual error correction | |
| US6674824B1 (en) | Method and circuitry for controlling a phase-locked loop by analog and digital signals | |
| US5534821A (en) | Charge pump circuits for PLL frequency synthesizer | |
| US7750747B2 (en) | Clock selection circuit and synthesizer | |
| US5420543A (en) | Method and apparatus for determining a constant gain of a variable oscillator | |
| US6529084B1 (en) | Interleaved feedforward VCO and PLL | |
| JP2773703B2 (en) | PLL circuit | |
| JPS5839123A (en) | Pll circuit | |
| JP2000165234A (en) | Pll circuit | |
| JPH09223960A (en) | Phase synchronizer | |
| JP3081718B2 (en) | PLL circuit | |
| KR100235370B1 (en) | Phase synchronizing circuit with feedback to control charge pump | |
| JP2885662B2 (en) | PLL circuit | |
| JP2911269B2 (en) | PLL frequency synthesizer | |
| JP3244162B2 (en) | PLL circuit | |
| JPH02113726A (en) | Pll circuit | |
| JP3070076B2 (en) | Phase-locked oscillation circuit | |
| JP2001203570A (en) | Pll circuit and semiconductor integrated circuit | |
| JP2745787B2 (en) | PLL frequency synthesizer |