JPS5839039U

JPS5839039U - Vapor deposition jig for semiconductor devices

Info

Publication number: JPS5839039U
Application number: JP13441381U
Authority: JP
Inventors: 大館　光雄
Original assignee: 三菱電機株式会社
Priority date: 1981-09-09
Filing date: 1981-09-09
Publication date: 1983-03-14

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は半導体素子を示す斜視図、第２図は縦来例によ
る蒸着治具の分解斜視図、第３図は腕を浮き上げたマス
ク治具の斜視図、第４図ａ、　　ｂはこの考案の一実施
例を示すもので、第４図ａはマスク治具の展開斜視図、
第４図すは加工仕上後のマスク治具の斜視図である。図中、５はサイリスタ素子、６′はマスク治具、６’　
ａは遊離マスク、６’　ｂは腕、６’　ｃは外周マスク
、６’　ｄはかさ、７は保持具である。なお、図中の同
一符号は同一または相当部分を示す。Fig. 1 is a perspective view showing a semiconductor element, Fig. 2 is an exploded perspective view of a conventional vapor deposition jig, Fig. 3 is a perspective view of a mask jig with arms raised, and Figs. 4a and b are One embodiment of this invention is shown, and FIG. 4a is an exploded perspective view of the mask jig;
FIG. 4 is a perspective view of the mask jig after processing and finishing. In the figure, 5 is a thyristor element, 6' is a mask jig, and 6'
a is a free mask, 6' b is an arm, 6' c is a peripheral mask, 6' d is an umbrella, and 7 is a holder. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

In order to form a metal film on at least one main surface of a semiconductor element by vapor deposition or the like, a mask jig includes an outer circumferential mask, a free mask inside the mask jig, and a plurality of arms, and a mask jig having an opening. A vapor deposition jig comprising a holder for inserting and holding the semiconductor element in contact with the tool, the mask jig including a free mask and a peripheral mask divided into a plurality of parts,
1. A vapor deposition jig for a semiconductor element, comprising an arm joining the free mask and each divided portion of the outer peripheral mask, and each arm is provided with a relief part for preventing contact with the semiconductor element.