JPS5838887A - Alarm clock - Google Patents

Abstract

PURPOSE:To make the restarted alarm sound louder successively from the initial small sound pressure level by resetting to the original conditions the memory circuit of alarm sound pressure level and so on through an alarm set switch. CONSTITUTION:Alarm sound generating circuits 5-7 are successively selected through D type flip flops FF1 and FF2 of which the state of memory changes successively by the output of a counter 10 after a specified time has elapsed, and alarm sound of which the sound pressure level becomes thereby louder by and by is generated as the time passes when the alarm time comes. Those flip flops FF1 and FF2 and the counter 10 are reset and return to their original position when an alarm select switch 9 is turned on. Accordingly if the alarm sound is stopped before the alarm sound does not reach the highest sound pressure, alarm sound which becomes louder from the lowest sound pressure is generated when the same alarm time arrives next day, for instance, if the switch 9 is operated.

Description

Detailed Description of the Invention The present invention relates to an alarm clock, and its purpose is to stop the alarm operation during the alarm operation, and then when the alarm operation is set again, the alarm operation will start from the beginning. We provide an Aji-6 clock that can be used.

The present invention will be explained below with reference to Examples. FIG. 1 shows a circuit diagram of one embodiment, in which the circuit shown is an oscillation circuit using a crystal oscillator X as a reference oscillator, and for example, this oscillation circuit 11) outputs an oscillation frequency signal of 32 KHz. This output is 1
~4th stage frequency divider circuit 12).

6th to 11th stage frequency divider circuit 1: 11. The frequency is divided by the 12th to 15th stage frequency divider circuits (4), respectively, and the final stage generates a lHz zero signal, and also an alarm sound signal generation circuit to be described later. (6) to (7) are input as frequency signals for audio signals. Alarm sound signal generation circuit fil~(7)
modulates the off-duty period of an 8 Hz frequency signal with off-duty and off-duty of 1=1 with an appropriate frequency signal to create alarm sound signals, and the alarm sound signal generation circuit (6) has an on-duty ga o, os
It is modulated with a frequency signal of 256H2 of o6msec, and the alarm sound signal generation circuit (the on-duty of the button is 0.224
512H in sea! The alarm sound signal generation circuit (7) is modulated with the frequency signal of 0, and the J duty is 0.
．． It is modulated with a 2048Hz frequency signal of 244m5ea. That is, alarm sound generation circuit (6), +e+, +
In the order of t+, the sound pressure, bell, and frequency are raised. (8) is an alarm switch, and this alarm switch (8) is linked to a reference mechanism of a clock mechanism (not shown), and when the current time coincides with a preset alarm setting time, t: JL, constant. time (e.g. 60 minutes)
It is designed to turn off after oscillating.

(9) is an arm set switch, and this alarm set switch (9) is a switch for setting the alarm sound and floating. When this alarm set switch (9) is turned off, D type Furi Sozufu 0tsuzuF
It is designed to set FI%FFg and counters respectively. The FFm is of a type that operates at the falling edge of a pulse. 00) is, for example, 64
It is a counter that counts seconds, and the frequency divider circuit (4) counts the 51 Hz zero clock signal 64 through the gate (IT), and the alarm tone generation period is set by this counter signal. A is a logic circuit for performing switching settings of the alarm signal generating circuits (6) to (7) together with the above-mentioned type of FFt and FFs. The selected Q3) is for setting the alarm mode to auto or manual.
When setting the alarm mode selection switch 0 to the manual side, the alarm sound signal is transmitted through the alarm mode selection circuit 0 and the logic circuit (l) to the alarm sound signal generation circuit. (5) ~ (7i
(b) (o) (c
It is possible to select and set using the contact point l)! @(l) is a snooze switch for a snooze set, and this snooze switch (15) is designed to mechanically interlock the alarm switch (8). It returns the IK alarm switch 9+81 to its original state after, for example, 5 minutes have elapsed since it was turned off and turned on.Also, when this snooze switch 051Fi is turned on, the gate (11) glue t is turned off through the chatter link prevention circuit at. To end: lyca H“
Input a signal to close Ill, and input a #H" signal to the counter (1α glue set terminal) to reset the counter +io+. α power is the Sa input circuit, This 8-value input circuit αη is
When the L'' signal is input, the output also becomes #L#, and t vDD/
! Since the input b and output are "■", each output signal is input to the chatter link prevention circuit (gate through I81t- +11), and if it is an L" signal output, the gate (+11 is closed, If the 'H' signal is output, the gate (works like opening a river). )?t+o, the transisister Tr is driven through the output buffer (Inc.), and this drive causes the sounding element η exclusively for the speaker to sound.

Next, the operation of the alarm clock of the present invention will be explained. First, if you want to set an alarm, that is, a wake-up, turn on the arm set switch (91) and operate the reference mechanism of the clock mechanism (not shown) to set the desired wake-up time.Now, set the alarm. When the switch (?) is turned on, a D-shaped frizz
The ILII signal is input to the FFs and FFs glue set terminals, and each FF1. FFm beam is set. And these outputs Q^ and QB are 〃L“
held at the level.

At the same time, the K"L" signal is input to the 8-value input circuit (17), but since the output is also at the "L" level, the "L" signal is input to the gate (Il), and the counter (Il) receives the "L" signal.
The counter (10) does not operate because the 1 Hz zero clock signal is input to the counter (10). Now, when the alarm set time comes, the alarm switch (81) is turned on, and the voltage of Vvo/2 is input to the 8-value input circuit (1), and its output is set to the #H'' level.Therefore, the gate (11) It opens when the H" signal is input, and the l Hz zero-count signal is input to the counter (lO), and the counter (lO) performs a counting operation.
3, each of the input terminals MU-A is at "H" level, and it is possible to receive the output of QA%QB of D-type flip-flops FFx and FFt through the 0-thick ml path (12). state. At this time, if the alarm mode selection switch is set to the auto side ■, the alarm mode selection circuit 0
The input terminals of the gates N4 to N9 of the logic circuit α are set to H" level by each output of the logic circuit α, and therefore, at this time, each of the flip-flops FFt, FF
The outputs QA and QB of t are "L" level.) The input terminal B1 of N+ becomes "I (LL level. As a result, the output of N1 is Jf L LL)
L, the first stage alarm sound signal generation circuit (6
), and the alarm sound signal shown in FIG. 2(a) is transmitted to Nantes Gate N!・The signal is input to the base of the transisister Tr through the output buffer and the sound pressure is low, and a low-frequency alarm sound is emitted through the movement of the sounding body. Counter output changes from “L//level” to “H1”
/ level, and the gate output of NOR gate NR1 becomes I.
I L II and Sui, therefore Ishibatae! through D
The clock terminal of the flip FFs of the mold is set to “H”.
A double signal is input. Therefore, the output QAa becomes "H" level, and as a result, the input terminal B1 of (side game) N+ becomes "L".
"At the same time, the input terminal B of the Nant gate N! becomes Hg L, the bell. Therefore, the output of the first stage alarm sound signal generation circuit (art) stops, and as shown in Fig. 2(b) ) The alarm sound signal from the second-stage alarm sound signal generation circuit (6) is input to the reed section (II), and the alarm sound with a higher frequency is output to the sounding body along with a stone with a slightly higher sound pressure level. The sound will be emitted from cutting.And this sound is 64
If it continues for seconds, the output of the counter (10) will be “H” Gibel et al. #L
“Switch to level, and D-type fritz float FF1
, FF outputs QA and QB are at 4"L" level, #H
As a result, the input terminal B! of the Nand gate N2 reaches the "L u level," and the input terminal B3 of the Nand gate N3 becomes the "■" level. As a result, the output of the Nant gate N3 becomes "L" level. The 75-m sound signal generation circuit (7) in the eighth stage operates, and the alarm sound signal shown in Fig. 2 (C) is input to the assist section (19) (-1 sounding body movement) when the sound pressure is the highest and the bell is turned off. A high-pitched and high-frequency alarm sound will be emitted. Here, the output QB of the D-type flip-flop FF1 is connected to the input terminal of the NRs, so when the output Qs becomes "H" level, the output of the flip-flop FF1 is It is held at the "L" level and the QB small output of the flip FFt is held at the "■" level, and from then on, even if the output of the 9 link (10) changes, the alarm sound signal generation circuit (7 ), the alarm sound continues to be emitted by the alarm sound signal. Then, the alarm sound is emitted when the alarm set switch (9) is turned off or the alarm switch (8) is turned off, and the output of the 8-value input circuit 0η becomes the "L" level.
Each side game) output from N+ to tooth is set to the "H" level and continues until it reaches □. By the way, when the alarm set switch (9) is turned off during the alarm operation, the input level of the 8-value input circuit Q7) is set to the highest level, and its output is set to the "LII level", and all outputs from the gate to the corresponding output are set to "H". It is fixed at the level and stops the alarm sound generation from then on.On the other hand, when the alarm set switch (9) is turned off, an "H" level output is input to the counter Therefore, if the Aji-Yaseto switch (9) is turned on again while the alarm switch (8) is turned on,
The output of the 8-value input circuit 07) becomes "H// level and the game) (Ill opens, the counter (lO) starts reading from the beginning, and flips to FF!
, FFm is reset and each output QA is reset as described above.
, QB becomes "L" level, and the alarm operation restarts from the generation of the alarm sound by the alarm sound signal of the alarm sound signal generation circuit (5). Of course, the alarm sound of the first sound pressure level is emitted at the first alarm level on the next day, and the sounding time is maintained for a predetermined time.

By the way, the above-mentioned alarm sound signal generation circuit (5) or (6)
) while the alarm sound is being generated by the alarm sound signal.
When the set switch (16) is turned on, the alarm switch (8) is turned off in conjunction with this turning on.

At this time, an ``H'' signal is input to the glue set terminal of the game 10 through the chattering prevention circuit (16).
) (When Ill is closed, the counter 1101 is set. At the same time, it is an 8-person Noah game) NR+
An H" level signal is input to FF+, and the states of the outputs QA%QB of FFt are switched.

This operation will be explained along the time charts of FIGS. 8(a) to 8(C).

Now, as shown in Fig. 8(a), the alarm switch (8) is turned on, and the alarm sound is emitted by the number from the alarm sound signal generation circuit (5) with the lowest sound pressure and bell (for example, 40 dB). In the middle of the ringing ((]) in Figure 8(c)), the snooze switch was turned on at the timing shown in Figure 8(b), and the alarm switch (81 is activated in conjunction). Even when the gate (the river is closed and the counter (10) is reset at the same time, the alarm switch (8) is turned on and the snooze switch 06) is turned on and released, the off state is maintained for 5 minutes by a mechanical means that can be linked with an appropriate clock mechanism. Therefore, the output of the 8-value input circuit 07) is at the IIL level, so the output of the Nant gates N1 to Nm is It is fixed at H# level, and during that time, none of the alarm sound signal generation circuits (5) to (71) operate and the generation of the alarm sound is stopped.

Then, after 75 minutes have elapsed, the alarm switch (8) is turned on, and the output of the 8-value input circuit aη becomes "H// level. Therefore, the gate (■) opens and each input terminal of the Nant gate tooth to N3 is turned on. becomes “H” level.

Therefore, when the aforementioned snooze switch 051 is turned on, the outputs of FFI, FFI, QA, QB
are at the "HN" and 'L' levels, respectively, so the output of N2 of the Nantes gates Nt-Ns of the logic circuit Q appears at the "L" level, and as a result, the second-stage alarm sound signal generation circuit ( 6) is activated, the alarm sound signal is input to the actuator (I9), and an alarm sound with a sound pressure level (for example, 60 dB) is emitted as shown in (0) of Fig. 8. become.

Next, when the snooze switch is turned on again as shown at 0 in FIG. 8(b) while this 5-anime sound is being produced, the flip-flop FF1. FFm output QA
, QB are respectively inverted and become "L" and "H" levels.Then, the counter (io) is set in the same manner as described above, and after the alarm switch (8) has been off for 5 minutes, the counter (IO) is turned off. At the same time as the counting operation starts, the output of the Nant gate Ns becomes "L" level, and 8
The alarm sound signal from the 75th stage sound signal generation circuit (7) is input to the foot part (19), and the sound pressure is as shown in Fig. 8 (Q) (C), and the bell is the highest (for example, 100 dB). An alarm will sound.

When the snooze switch (15) is turned on, as shown in 09 in Figure 8(b), the riff [1' Suzu FF]
m's "■" level output QB causes y agate NRt
One input becomes “H” level, Noah game) NRt
Since the output of QA and QB is fixed at the level #:[, II, the subsequent flip is 70% J-5FFt, FFm, and the output of QA and QB is fixed, so the output will be 8 again after a 5-minute pause period. Alarm sound signal generation circuit for the second stage ()
9. From then on, every time the snooze switch is turned on and a snooze set is performed, the alarm tone will sound at the highest frequency and at the highest frequency after a 6-minute pause period. This is manifested in the sound pressure and the sound of a bell alarm.

In this way, for each snooze set, the alarm sound changes from the lowest to the lowest, with a higher frequency and higher sound pressure, and finally the alarm sound with the highest frequency and higher sound pressure. , it is possible to give the sleeper the pleasure of slumber and lead him to wakefulness slowly and physiologically.

The circuit in Figure 1 shows the clock mechanism, and the appropriate steps are indicated in the table. A so-called quartz watch or the like is used, which uses the output pressure of the L@U path to drive a 13-rush motor to move the hands.

Further, the levels of the output terminals OI-04 of the alarm mode selection circuit Oa at each time are set as follows according to the values of RI, R1, and R3. That is, (a) When the alarm mode selection switch 03 is turned on at the 'ffj point, the inverter is activated.

The inputs of ~I6 become H'% 'H'S'H', and as a result, the outputs of output terminals O1~04 are 'L I, 'L'
, 'H#, 1H#. (b) When the alarm shade selection switch (13) is turned on, the ishiverter 1 is connected to the contact point.
, ~I6 inputs become ゝH', 1L', 'L',
As a result, the output terminal is 0. The output of ~04 is 'L', '
H', 'H', 'L'. In addition, when the alarm mode selection switch (13) is turned on to the (c) contact, each input of ishiverters I4 to 16 becomes 'L I, 'H'%.
'H' and the output of output terminal O,~04 is 'H'%
'L', 'H'H' is pointed.'When the alarm t-do selection switch's Q3 is put into the [d) contact, each input of the Isif S-tata I6~. 'L', 'L
', 'L', and the outputs of the output terminals O1-04 remain at 'H'% 'H', 'L'% EastL. The result is 0! It is possible to control the output of the settering circuit (LA) and set the output corresponding to each of the seven codes, thereby selectively fixing the sound pressure level and frequency of a specific alarm sound.Furthermore, the settering prevention circuit (IL (18) is used to prevent chattering of mechanical contacts, and is a general type in which the input tuning fork is activated at the rising and falling edges of the signal.Also, L is a run for the snooze display. .

The present invention includes a plurality of alarm sound signal generation circuits that generate alarm sound signals having different sound pressure levels, and when the current time reaches the alarm setting time, the alarm sound signal generation circuits are switched from one with a lower sound pressure level to one with a higher sound pressure level. Since it is equipped with a switching memory means that switches sequentially at regular intervals, it is possible to switch the pre-alarm sound from a small sound to a progressively louder sound, thereby making it possible to wake up the sleeper without shocking him or her. In addition, a reset circuit is formed that resets the alarm operation time count contents and switching setting contents of the switching storage means to the initial state by returning and closing the alarm station switch which sets the alarm operation when turned on. Even when the alarm operation sound is stopped in the middle and then restarted, the alarm sound can be started from the first small sound of the alarm sound, and moreover, the sounding time is such that the alarm operation stop point does not stop. However, it is only available for a set amount of time,
In addition, even when the alarm is activated the next day, it always starts from the first alarm sound and does not restart from the point where the alarm operation stopped, so the alarm can be set by gradually increasing the volume of the alarm. Effect 7: The effect of the above is reliably obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2(a) to (
c) is a waveform diagram of the alarm sound signal of each alarm sound signal generation circuit, FIGS. The sword is the alarm sound signal generation circuit, the 0 value is the counter, (12 is the 0ji1tsuklrl path, (191 is the alarm 1tswitch 1)
Sochi, F"F,, FF, is fritz]O"')'j. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] IFJ A plurality of alarm sound signal generation circuits that generate alarm sound signals each having a different sound pressure level, and when the current time reaches the alarm setting time, the alarm sound signal generation circuits are switched from the one with the lowest sound pressure level to the one with the highest sound pressure level for a certain period of time. Alarm 1 is equipped with a switching storage means that sequentially switches and operates, and sets the alarm operation when turned on! An alarm clock comprising a short circuit which sets alarm operation time count contents and switching setting contents of a switching storage means to an initial state by returning and turning on a switch.