JPS5838794B2 - Onteihiyoujisouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In music education, it is important to accurately teach the pitch (frequency) of vocalizations.

The present invention relates to a pitch display device used in such cases. For example, as shown in FIG. 1, pitch names rA, B, C, etc. are displayed as a pitch table on the screen 10 of a monitor receiver.
Character 11 of ``...'' and floor name ``Do, Shi, Mi, ・
``...'' characters 12 are displayed horizontally in two lines, vertical lines 14 are displayed at semitone intervals, and when the user speaks into the microphone, the vertical axis The pitch of the audio is displayed as a bar graph using the time axis as the time axis.

Hereinafter, an example of the present invention will be described with reference to the drawings.

Figure 2 is a system diagram showing the overall configuration, and the voice of the speaker is
The microphone 1 generates an audio signal, this audio signal is supplied to the filter circuit 100 to extract the fundamental wave component of the audio signal, and this fundamental wave component is supplied to the detection circuit 200 to detect its frequency (frequency discrimination). This detection signal is supplied to the conversion circuit 300.

This conversion circuit 300 converts the detection signal from the previous stage into an information signal indicating which octave of the absolute scale the pitch of the fundamental wave component is included in, and which pitch within that octave.

The information signal indicating the pitch and the information signal indicating the octave are sent to the memory circuit 400 and the video signal forming circuit 50.
0 to the monitor receiver 2.

In this case, the memory circuit 400 stores the information signal up to the present time, and supplies this to the next stage together with the information signal at the present time to display the pitch up to that point as shown in FIG. It is.

Furthermore, the receiver 2 is mounted and horizontally deflected in the same way as a normal television receiver, and therefore the memory circuit 40
The storage signal (information signal) from 0 is converted into a video signal for display on the receiver 2 in the forming circuit 500.

Next, let's explain each circuit in detail.

FIG. 3 is a system diagram of a filter circuit 100 that extracts the fundamental wave component of an audio signal.

In this figure, 101 is a tracking filter, 10
2 is an amplifier, 103 is a rectifier circuit, and this tracking filter 101 has a low-pass cutoff characteristic as shown in FIG. In other words, when the output of the amplifier 102 is large, the cutoff frequency f.

is low, and when the output of the amplifier 102 is small, the cutoff frequency f.

is controlled to be high. Therefore, the fundamental frequency component of the input signal is extracted at a predetermined level to the output side of the amplifier 102, and the harmonic components are blocked by the filter 101.
Since the output level of 02 becomes smaller, the cutoff frequency of filter 101 becomes higher and the frequency of the fundamental wave becomes lower.
Since the output level of amplifier 102 increases, the cutoff frequency of filter 101 decreases, and from amplifier 102,
The fundamental wave component of the human input signal is always extracted at a constant level.

FIG. 5 is a circuit example showing a specific connection diagram of the filter portions of the filter 101, amplifier 102, and rectifier circuit 103 shown in FIG.
Capacitor 114°115, field effect transistor 11
6 and 117 constitute a low-pass filter 101, and the operational amplifier 121 constitutes an amplifier 102 whose gain is determined by resistors 122 and 123.

Then, the output signal of the operational amplifier 121 is transmitted to the diode 13.
1, is supplied to the gates of field effect transistors 116 and 117 through a rectifier circuit 103 consisting of a resistor 132 and a capacitor 133.
The impedance value between the source and drain of filters 16 and 117 is changed, and the cutoff frequency of filter 101 is controlled.

By the way, the fundamental wave component extracted in this way has a phase difference with respect to the original signal because a change in phase occurs in the vicinity of the cutoff frequency of the filter 101 when the width of the fundamental wave component varies.

Therefore, in order to remove this phase difference, a logic circuit 105 is provided as shown in FIG.

This logic circuit 105 consists of a JK flip-flop circuit 1 having a clock terminal that is triggered by the falling edge of an input signal and a clear terminal that is reset by an input voltage of 'O゛°.
06, 107, the potential of "1" is always supplied to the J terminal, and the potential of "0" is always supplied to the K terminal, and the negative output terminal of the flip-flop circuit 101 is connected to the resistor 171. A delay circuit 17 of about 20On8 consisting of a capacitor 172
0 to the clear terminal of the flip-flop circuit 106, and the positive output terminal of the flip-flop circuit 106 is connected to the clear terminal of the flip-flop circuit 107.

Furthermore, the output signal of the amplifier 102 is transmitted to the waveform shaping circuit 10
4 to the clock terminal of the flip-flop circuit 106, and the output signal of the microphone 1 is supplied to the amplifier 108.
, the multi-by-break 10 through the waveform shaping circuit 109
7 trigger terminal.

Therefore, when an audio signal Sa as shown in FIG. 6A is obtained from the microphone 1, output signals Sb as shown in FIG. 6B are extracted from the amplifier 102, and these are A' and B, respectively. When the waveform is shaped as shown in FIG. 6 and supplied to the logic circuit 105, a signal Sc as shown in FIG. 6C is obtained.

That is, first, at the falling edge of the waveform-shaped signal Sb', the Noritub flop circuit 106 is inverted, and the clearing of the Noritsu Frog circuit 107 is released, and then at the falling edge of the waveform-shaped signal Sa', the Noritub flop circuit 106 is inverted, and the Noritsu flop circuit 107 is cleared at the falling edge of the waveform-shaped signal Sa'. 107 is inverted and the signal Sc falls, which causes 2
After 0 Ons, the flip-flop circuit 106 is cleared, and its output immediately clears the flip-flop circuit 107.
is cleared, and the signal Sc falls and returns to the original state.

In this way, in this filter circuit 100, a pulse signal having the same frequency and phase as the fundamental wave of the input signal is extracted.

Next, FIG. 7 is a system diagram of the frequency detection circuit 200 and the conversion circuit 300 that converts the frequency into two information signals of a scale and an octave.

In the figure, 201 is a counter, and the signal from the filter 100 described above is supplied to this counter 207, and the number of cycles of the input signal is counted.

On the other hand, 201 is, for example, a 320kHz oscillator, and this oscillation pulse is supplied to the 1/8 frequency division 1 circuit 202,
A 0 kHz clock pulse is generated and is supplied to the counter 205 through the selection circuit 204 .

In addition, as described later, the content of the counter 205 is "512".
When the value exceeds 0, the selection circuit 204 is switched to a position opposite to that shown in the figure, and the clock pulse whose frequency has been divided by 1/2 by the frequency dividing circuit 203 is supplied to the counter 205.

Furthermore, the contents of the counter 207 are supplied to the decoder 708, and the contents of the counter 207 are "2n", that is, "1.
2, 4, and 8'', a pulse signal is taken out and this pulse signal is supplied to the gate circuit 209.

Further, the output signal of "256 j" and the output signal of "512" of the counter 205 are supplied to the OR circuit 211, and the gate circuit 209 is turned on by this OR output while the content of the counter 205 is "256" or more. be done.

This gate output is then supplied to a monostable multivibrator 210 with an extremely short inversion time, e.g. Frequency divider circuit 2 through circuit 214
02 to counters 205 and 207, clearing these circuits.

Further, 213 is a flip-flop circuit, and this circuit 213 is set by a signal taken out through a decoder (AND circuit) 212 when the content of the counter 205 becomes 1'-528J, and is set by a signal from the filter 100. will be reset.

Then, during the period when this flip-flop circuit 213 is set, an output signal of "1" is supplied to the OR circuit 214, and during this period, the frequency dividing circuit 202, the counter 205,
207 is cleared.

Furthermore, when the content of the counter 207 becomes "9", the output signal is taken out from the decoder 208, this signal is supplied to the OR circuit 214, and the frequency dividing circuit 202 and the counter 20
5,207 is cleared.

Therefore, when a pulse signal is supplied from the filter 100, the flip-flop circuit 213 is reset, the clear state of the frequency divider circuit 202 and the counters 205, 207 is released, and counting is started.

When the content of the counter 205 exceeds "256", the gate circuit 209 is made conductive through the OR circuit 211, and when the content of the counter 207 becomes "2n" in this state, the multi-bye break 210 is activated by the output of the decoder 208. Triggered, followed by multi-bye break 21
5 is triggered, and this output pulse causes the frequency divider circuit 20
2. Counters 205 and 207 are cleared.

Thereafter, the count is restarted from "0" again, and this operation is repeated.

In this way, the counter 205 detects the time corresponding to 2n cycles of the input signal, and the counter 207 detects the time corresponding to 2n cycles of the input signal.
The number of cycles of the input signal required for the above-mentioned detection is detected. In this case, if the value detected by the counter 205 is rxJ, the frequency corresponding to this rxJ is the number of cycles required for the detection. The values are different depending on the number of cycles: 1 cycle, 2 cycles, 4 cycles, and 8 cycles.

However, in this case, if the time is constant and the number of periods in between is doubled, the frequency is doubled.

On the other hand, when the frequency of the fundamental wave of a signal is doubled, the pitch becomes one octave higher.

Therefore, when the above-mentioned rxJ is an arbitrary number, the corresponding frequencies are 2n times larger than each other, that is, they are intervals of the same note name in different octaves, and the counter 205 is detected.

In this case, the pitch name is detected by dividing one octave into 256J parts and detecting each part as a position signal.

The partial counter 207 detects the number of periods of the input signal, and thereby detects which octave the input signal is included.

In addition, in this device, when the content of the counter 205 is "512", the lowest frequency detected is the lowest frequency detected by the counter 207.
The frequency in this case is 1, and the highest frequency is when the content of the counter 205 is ``1''.
256'', the counter 207 counts ``8'', and the frequency in this case is: This is within the frequency range of the fundamental wave of the voice (80Hz to 10Hz).
00Hz).

Therefore, the content of the counter 205 becomes "256",
Before the gate 209 becomes conductive, the counter 201
If the content becomes "8", that is, if the counter 201 counts "9", this clearly means that a sound other than a human voice or a harmonic has been erroneously detected.

Therefore, in the above-mentioned device, the contents of the counter 207 are "
9'', the decoder 208 detects this, clears the frequency dividing circuit 202 and counters 205 and 207, and repeats the detection.

Further, in the case of normal detection, the input signal always has a period of 2n while the contents of the counter 205 change from "256" to J512J.

However, human speech usually has frequency fluctuations (vibrato) of about ±3%.

Therefore, for example, the pulse of the 2n-1th period is detected by the counter 20.
If the content of counter 205 is about to reach 1256J, the 2nth cycle pulse may not occur until the content of counter 205 reaches l'-512J due to the above-mentioned vibrato.

For this reason, in the above-mentioned device, the content of the counter 205 exceeds "512" and r161 (as described later, in this case, the selection circuit 204 is switched to the output side of the frequency divider 203, so it becomes "32"). ” i.e. about 6 of 512
%), the count continues without being cleared.

However, if the content of the counter 205 exceeds "528", the input signal is considered non-periodic or unstable and cannot be measured, and this is detected by the AND circuit 212 and the flip-flop circuit 213 is set. By doing so, the frequency dividing circuit 202 and counters 205 and 207 are cleared.

In this case, even if the input signal is no longer supplied, the counter 205 is not cleared and counts up to J528J, and the flip-flop circuit 213 is set.
The next input signal is supplied to the flip-flop circuit 21.
3 is reset, the frequency divider circuit 202 and the counter 2
05.207 remains in the clear state.

Note that in normal detection, the content of the counter 205 is "25".
6J to J512J is detected as one octave, but as mentioned above, the contents of the counter 205 are l-51.
If it exceeds 2J, the range from 512J to 1024J corresponds to one octave.

In other words, the width of change in frequency corresponding to one clock pulse becomes 1/2. Therefore, in the above-mentioned device, when the content of the counter 205 exceeds "512", the selection circuit 204 is switched. , the clock pulses supplied to the counter 205 are frequency-divided by 1/2.

The contents of the lower eight digits of the counter 205 thus obtained are supplied to the register 301.

Furthermore, the contents of the counter 207 are supplied to the encoder 303 through the selection circuit 302, and the output signal of the encoder 303 is supplied to the register 304.

Further, the output signal of the multi-by-break 210 described above is supplied to the registers 301 and 304 as a write pulse.

Also, while the flip-flop circuit 213 is set, its output signal is used as a clear signal to the register 300.
．． 304.

In this case, in the selection circuit 302, the counter 20
The output signals for each digit of ``1, 2, 4, and 8'' of 7 are supplied to one switching contact of the changeover switches 311 to 314, and the output signals of ``24 and 8'' are supplied to the lower digit, respectively. It is supplied to the other switching contacts of the switches 311 to 313, and the other switching contact of the switch 314 is grounded.

Therefore, when each switch 311 to 314 is switched to the position shown in the figure, the contents of the counter 207 are supplied as is to the encoder 303, and when they are switched to the opposite position as shown in the figure, the contents of the counter 207 are supplied to the encoder 303 as is. The signal is halved and supplied to the encoder 303.

Furthermore, this selection circuit 304 selects l'-5 of the counter 205.
Therefore, during the period when the content of the counter 205 is from 1'-512J to "528", the content of the counter 207 is halved and the output signal of the encoder 303 is controlled by the output signal of 12J.
supplied to

The output signal register 3 of this encoder 303
In this case, as described above, writing to the register 304 is performed when the content of the counter 207 is "2n", so the content of the counter 207 when writing to the register 304 is r2nj(n =0・1
・2 or 3), the value of n at this time is binarized by the encoder 303 and supplied to the register 304.

In this case, the contents of the counter 205 are "512 to "5.
28'', the counter 205
This means that twice the original count is being performed, so
At this time, the contents of the counter 207 are halved by the selection circuit 303 and then supplied to the register 304.

In this way, one octave from the counter 205 is 256
The divided pitch name data and the octave data from the counter 207 are written to the registers 301 and 304. According to this circuit, the octave data and the pitch data are obtained by measuring 2n cycles of the input signal. are taken out separately.

Also, since measurements are always performed by counting 256 pulses or more, when the frequency is high and the period is short, the period required for measurement automatically increases, and the average value is taken out, so the clock pulse for detection Errors due to timing are reduced.

Furthermore, the output signal of the flip-flop circuit 213 causes
I cleared registers 301 and 304, so
When there is no input signal and there is no sound, the register 301
, 304, unnecessary signals are not extracted.

Furthermore, FIG. 8 is a system diagram of an example of the memory circuit 400.

In this figure, 401 is a read-only memory, which contains pitch data obtained by dividing one octave into 256 from the register 301, ■ pitch name data obtained by dividing the octave into 12 parts for each semitone, and 16 parts within each semitone. In this case, the error data is converted into
The 8-bit input signal is 1 from (oooo) to (1011)
The data is converted into two types of 4-bit pitch name data and 4-bit binary coded error data.

The 8-bit output signal from the read-only memory 401 and the 2-bit octave data from the register 304 are held in the register 450 according to the output signal from the monomulti 215, and are supplied to the random access memory 402.

Further, the output signal of the flip-flop circuit 213 is supplied to the reset terminal of the register 450 through the OR circuit 451, and its value is reset to "0" when there is no signal.

On the other hand, 403 is a synchronous board, 404 is a counter, and 403 is a synchronous board.
The vertical synchronization signal from 03 is supplied to the reset terminal of the counter 404, the horizontal synchronization signal is supplied to the counting terminal,
This counter 404 obtains a signal that increases by 1 in units of horizontal periods for each vertical period.

This signal is supplied to the address terminal of random access memory 402.

Furthermore, 405 is a variable frequency oscillator, for example, 20Hz.
A pulse signal is formed.

This pulse signal is then supplied to a counter 407 through a gate circuit 406, and the counter 407 receives two pulse signals.
A sequentially increasing signal is obtained with a pulse signal of 0 Hz.

The signal from this counter 407 and the counter 40 described above
4 is supplied to a comparison circuit 408, and when they match, an output signal is supplied to an AND circuit 409.

Also, the horizontal synchronization signal from the synchronization board 403 is output to the AND circuit 4.
09, and this AND output is sent to the random access memory 4 as a write pulse through an OR circuit 410.
It is supplied to the write control terminal of 02.

Therefore, normally the contents of the random access memory 402 are sequentially read out every horizontal period, and this reading is repeated every vertical period.

On the other hand, when the contents of the counters 404 and 407 match, a signal is taken out from the comparison circuit 408, and this match signal is 1
A signal is taken out from the AND circuit 409 during the horizontal synchronization signal period, that is, the horizontal blanking period, and this signal is supplied to the random access memory 402 as a write pulse through the 47 circuit 410. The contents of the registers 301 and 304, that is, the data obtained by detecting the pitch of the input signal, are written to addresses determined by the contents of the counters 404 to 407 of the random access memory 402.

Further, each time the contents of the counter 407 increase by one, the addresses written to the random access memory 402 are sequentially moved.

In this case, as will be described later, for example, the 16 horizontal periods at the top of the screen are used as the display area for note names and scale names, so 16 is set on the counter 407 to prevent data from being written to this area. Preset.

Further, the output signal of the counter 407 is supplied to the decoder 411, and when the number of horizontal scanning lines used for display on the display surface of the display device described later reaches, for example, 240, the signal is taken out from the decoder 411, and the enable signal of the counter 407 is output. is supplied to the terminal to prevent the counter 407 from counting any further.

Further, the output pulse of the filter 100 described above is supplied to a retriggerable monostable multivibrator 412, and the output signal of this multivibrator 412 controls the gate circuit 406. During the period when the multivibrator 412 is inverted, the gate circuit 406 is made conductive.

Therefore, if there is no input signal for more than the inversion time of the multivibrator 412, for example 1 second, the gate circuit 406 becomes non-conductive, the counter 407 stops counting, and writing to the random access memory 402 is no longer performed. .

Furthermore, when the input signal is supplied again, the multi-bye break 412 is inverted, the gate circuit 406 becomes conductive, the counter 407 restarts counting, and writing to the random access memory 402 is performed again. However, in this case, the contents of the counter 407 at the time when writing is restarted have been counted up by the number corresponding to the inversion time of the Multi-Piebrae 24120 since the last time the signal was supplied, and during this time Data of "0" is written in each address of the random access memory 402 because there is no input signal.

Further, a start signal from the display control circuit 600 is supplied to the reset terminal of the register 450 and the preset terminal of the counter 407 through the OR circuit 451, and is also supplied to the random access memory 402 through the OR circuit 410.
is supplied to the write control terminal of.

Therefore, while the counter 404 counts one vertical period,
If this restart signal continues to be supplied, "0" is written to each address of the random access memory 402, all data is erased, and data can be written again from address 16 given by the value of the counter 404.

In addition, in the above example, the oscillation frequency of the oscillator 405 is set to 20H.
z, the contents of the registers 301 and 304 at that time, that is, data regarding the pitch of the input signal, are written to the random access memory 402 20 times per second.
By changing the number of times of writing, the time interval for detecting the pitch of the input signal can be changed by changing the number of times of writing.

In this way, data from registers 301 and 304 is stored in random access memory 402 through register 450. In this circuit, when there is no input signal, the output signal of oscillator 405 is cut off and the counter Since the contents of 407 do not change, "0" data when there is no input signal is repeatedly written to the same address, which prevents unnecessary use of many addresses with such useless data. There is no.

Moreover, in this case, even if there is no input signal, counting continues while the multi-bye break 412 is inverted, so data of "0" is written to the address specified by the counter 407 during this period. This interval becomes blank, and the part where the input signal is interrupted is clearly shown.

Further, in the above-described circuit, by changing the oscillation frequency of the oscillator 405, the time interval for writing the pitch of the input signal can be arbitrarily changed.

Furthermore, FIG. 9 is a system diagram of a signal forming circuit 500 that forms a video signal to be displayed on the television receiver 2 from data stored in the random access memory 402.

In this circuit, reference numeral 501 is a comparison circuit, and data signals sequentially read out from the above-mentioned random access memory 402 in a horizontal period are supplied to one input terminal of this comparison circuit 501.

Further, 502 is a counter, which is composed of, for example, 10 bits, of which the lower 4 pits are hexadecimal binary counters 521. The next 4 bits are (0000) to (1
011)'s hexadecimal counter 522, the upper two bits are 4
Each of the counters is configured as a decimal binary counter 523, and these are connected in series.

Further, 503 is a variable frequency oscillator, and this oscillator 503
At this time, a clock pulse of, for example, 7.68 MHz, whose phase is locked by the horizontal synchronization signal from the synchronization board 403, is formed.

Then, this clock pulse is supplied to the counter 502, and this counter 502 is preset to an initial value with a horizontal periodic signal, and in this counter 502,
For example, if the horizontal effective scanning period of the picture tube 2 is 50 μS,
A horizontal position signal is generated by dividing this into 384 parts.

Note that the lower 4 bits of this position signal are binary codes, and the next 4 bits are 12 (oooo) to (1011).
The upper 2 bits of the decimal code are binary code.

This is a signal in the same format as the data signal from the random access memory 402 described above, with the lower 4 bits corresponding to error data, the next 4 bits corresponding to pitch name data for each semitone, and the upper 2 bits corresponding to octave data. .

This position signal is supplied to the other input terminal of comparison circuit 501 and compared with the data signal from random access memory 402, and the signal is extracted when the data signal is thicker or when they match.

This signal is supplied to an adder circuit 504, where it is combined with blanking pulses, synchronization pulses, etc. from the synchronization board 403, and this combined signal is supplied to the monitor receiver 2.

In this way, the color of the scanning line is changed from the scanning start position of the horizontal scanning line on the screen 10 until the data signal and the position signal match.

However, in this case, the unit of the position signal is a value obtained by dividing the scan into 384, and when the count of the counter 523 above the counter 502 exceeds 2, the color of the scanning line changes over the entire interval, and the display is no longer possible. I won't be able to do it.

In contrast, the data signal from random access memory 402 can take on that value until the upper two bits become 4.

Therefore, in the above-described circuit, the display can be shifted by presetting a predetermined value in the counter 502.

That is, 505 is an up/down counter for setting a preset value, for example, 3Hz from an oscillator 506.
clock pulses are supplied to the up input terminal and down input terminal of the counter 505 through the gate circuits 507 and 508, and the gate circuit 507 or 508 is arbitrarily made conductive by the control signal from the display control circuit 600, so that the counter A desired value is set in 505.

When the counter 502 is reset, this value is preset in the counter 502.

Note that this counter 505 has a hexadecimal counter 552 and a quaternary counter 553 connected in series, and preset values corresponding to the counters 522 and 523 of the counter 502 are respectively formed.

Therefore, when a clock pulse from the oscillator 503 is supplied to the preset counter 502, the data signal and position signal will match in the comparator circuit 501 earlier by the preset value, and the display will change as a whole. Shifted toward the scanning start position.

Note that when one clock pulse from the oscillator 506 is supplied to the up input terminal of the counter 505, the content of the hexadecimal counter 552 of the counter 505 is increased by Ill.

Therefore, when the contents of this counter 505 are preset in the counter 502, the display is shifted by one semitone toward the scanning start position.

Furthermore, when 12 clock pulses are supplied to the up input terminal of the counter 505, the contents of the quaternary counter 553 of the counter 505 are incremented by "1", and the display is shifted by one octa toward the scanning start position side. .

Furthermore, in this circuit, the oscillation frequency of the oscillator 503 is varied by a signal from the display control circuit 600.

By doing this, for example, when the frequency of the oscillator 5030 becomes high, the count of the counter 502 becomes faster, and the time until the signals match in the comparison circuit 501 becomes shorter.

On the other hand, since the scanning speed of the horizontal scanning line is constant,
The part where the scanning line changes color on the screen 10 becomes shorter,
As a result, the display content is reduced, and the display range can be expanded by displaying two or more octaves, for example.

Similarly, by lowering the frequency of the oscillator 503, the display is enlarged and minute changes can be made clearer.

Below, the note names "A, B, C" will be displayed on the screen 10 of the receiver 2.
・・・・・・・ and the floor name “Do, Shi, Mi...
The configuration for displaying ``...'' will be described below.

In this case, note names and scale names are displayed in two rows over 16 horizontal scanning periods at the top of the screen.
Furthermore, pitch names correspond to frequencies, and for example, when the display is shifted as described above, the letters are also shifted at the same time, while pitch names can be freely moved by transposition, modulation, etc.

Therefore, in this circuit, a counter 512 and an up/down counter 513 are provided.

Further, gate circuits 514 and 51 controlled by the display control circuit 600 in the same manner as the gate circuits 507 and 508 described above.
5 is provided, the clock pulse from the oscillator 506 is taken out through gate circuits 514 and 515, and the taken out clock pulse and the gate circuits 507 and 50 are provided.
8 is supplied to the counter 513 through OR circuits 516 and 517.
The contents of the counter 512 are preset in the counter 512.

However, the lower 4 bits of the counter 531 of the counter 512 are preset to (0000).

Therefore, in this counter 513, the gate circuit 50
7. When 508 is made conductive and display data is shifted, this counter 513 also counts, the preset value for counter 512 is changed, and gate circuits 514 and 515 are made conductive. In this case, only the counter 513 counts independently, and only the preset value for the counter 512 is changed.

The counter 513 is a hexadecimal counter and supplies a preset value to the hexadecimal counter 532 of the counter 512.

The contents of the hexadecimal counter 532 of this counter 512,
The contents of the hexadecimal counter 522 of the counter 502 are selected by the selection circuit 509 and supplied to the character selection terminal of the character generator 5100.

This character generator 510 configures characters with dots in a matrix of, for example, 8 rows and 8 columns, and generates pitch names such as rA, B, C, etc. by a signal supplied to a character selection terminal.
・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・・
A character signal of ``...-'' is formed, and this character signal is
The lower 3 of the horizontal period count output from the counter 404
The signals of bits 0 to 7 are repeatedly taken out in order for one horizontal scan.

Note that when the same signal as the 4-bit pitch name data when the sound "A" is recorded in the random access memory 402 in this circuit is supplied from the counter 522 of the counter 502 to the character generator 510, the sound "A" is ”
The character signal of is extracted, and hereafter rBJ, "C" ---
・−・・− character signals are extracted.

Furthermore, in this circuit, the character signals are decimal binary signals for both pitch names and scale names.

Therefore, the character generator 510 is controlled at the same time as the selection circuit 509 is switched, and the counter 50
When two or more signals are supplied, a character signal of a note name is formed, and when a signal from the counter 512 is supplied, a character signal of a scale name is formed.

The control of the character generator 510 and the switching of the selection circuit 509 are performed by the horizontal cycle counter 40.
4, that is, the contents of the counter 404 are supplied to the decoder 518, and the decoded output is supplied to the selection circuit 509 and the character generator 510. During the first 8 horizontal scanning periods, the contents of the counter 502 are supplied to the character generator 510. The contents of the counter 512 are supplied to the character generator 510 during eight horizontal scanning periods from 9 to 16 to form a character signal of the pitch name.

Note that, from this character signal, one horizontal scan of each character is extracted in parallel.

Therefore, this parallel signal is loaded into the shift register 511 by a pulse signal for each semitone from the decoder 519, and this shift register 511 is driven by a horizontal position signal from the oscillator 503, so that the signal is taken out serially in the horizontal scanning direction. make it possible to do so.

Furthermore, 520 is a gate circuit, and a decoder 518
A control signal from the control circuit 10 makes the screen 10 conductive only during the first 16 horizontal scanning periods.

A signal from the shift register 511 is then supplied to the adder circuit 504 through this gate circuit 520.

In this way, note names and scale names are displayed in two lines in the range of 16 horizontal scanning lines at the top of the screen 10, but according to this circuit, gate circuits 507 and 508 are rendered conductive. , when the display of data on screen 10 is shifted, the letters of note names and scale names are also shifted at the same time.

Furthermore, when the gate circuits 514 and 515 are rendered conductive, only the characters of the scale name move, and for example, when transposition, modulation, etc. are performed, the scale name can be displayed in accordance with the tone. .

Furthermore, a pulse signal for each semitone from the decoder 519 is supplied to the adding circuit 504.

Therefore, a vertical line is formed on the screen 10 to indicate the position of each semitone.

Furthermore, when the oscillation frequency of the oscillator 503 is changed as described above, the counting speed of the counter 502 and the counting speed of the counter 512 can also be changed. The letters and vertical lines between semitones are also enlarged or reduced at the same time.

In this way, in the device of the present invention, an interval with vertical lines attached at semitone intervals is displayed on the television screen 10 along with letters of the note name and scale name, and the interval of the user's voice is displayed here in the form of a bar graph. Therefore, if the pitch is off, this can be seen visually, and even if the user changes the pitch and pronounces it at the correct pitch, the length of the bar graph will change according to the change in pitch. However, this makes it very easy to vocalize at the correct pitch, and can be used to great effect in music education.

Furthermore, according to the present invention, a tracking filter is used as a filter circuit when extracting the fundamental frequency component, and the cutoff frequency is changed using the output signal as a control signal, so that the fundamental frequency component is always extracted at a constant level. In addition, the output signal of the filter and the input signal are compared, and the telegram crossing point of the input signal immediately after the telegram crossing point of the output signal is extracted, so there is no phase shift between the input signal and the output signal, and the signal is accurate. The fundamental wave can be extracted.

In addition, when detecting the frequency value, the time for 2n cycles of the input signal is detected, and the number of cycles (2n) of the input signal required for detection is measured, and from this number of cycles, the input signal is In addition to detecting which octave it belongs to, we also detect which pitch within that octave from the above-mentioned time, so the octave data and pitch data of the input signal are extracted separately, making subsequent processing easier. Become.

In addition, the storage circuit repeatedly counts the horizontal synchronization signal and uses it as an address signal, for example, 2
Since the oscillation signals of the 0Hz oscillator are counted and writing is performed when they match, data is written on the screen in order from the upper scanning line at intervals of, for example, 1/20 seconds, and furthermore, Since the oscillation frequency of this oscillator can be changed arbitrarily, the data writing interval can be changed arbitrarily.

Furthermore, a gate circuit is provided on the output side of the oscillator, and this gate circuit is made non-conductive when there is no input signal, so the write address does not change when there is no input signal, and the random access memory Addresses are not wasted.

Furthermore, since this control signal is taken out through a monostable multivibrator, when the input signal disappears, "0" data is recorded for a predetermined period, making the break in the input signal clear.

Furthermore, according to the present invention, pitches are displayed, and characters for pitch names and scale names are displayed, and when the display range is moved, the display of these characters also moves at the same time, making it easier to read the display. becomes easier.

Furthermore, since only the letters of the scale name can be moved separately, it is possible to cope with modulation or transposition.

Furthermore, since the displayed content can be enlarged or reduced, it is convenient for displaying a wider range or for reading minute changes.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of pitch display according to the present invention, Fig. 2 is a system diagram showing the overall configuration, Fig. 3 is a system diagram of a filter circuit, and Figs. 4 and 6 are for explanation. Figure, 5th
The figure is a connection diagram of an example of a tracking filter, Figure 7 is a system diagram of an example of a frequency detection circuit, Figure 8 is a system diagram of an example of a storage circuit, and Figure 9 is a system diagram of an example of a video signal forming circuit. . 1 is a microphone, 100 is a filter, 200 is a frequency detection circuit, 300 is a conversion circuit, 400 is a storage circuit, 50
0 is a video signal forming circuit, 600 is a control circuit, and 2 is a monitor receiver.

Claims (1)

[Claims] 1. A filter that extracts the fundamental wave of a human signal, a counter that detects the frequency of this fundamental wave, a conversion circuit that converts this frequency into octave data and pitch data, a storage circuit that stores these data, and Based on the data (data display signal and a video signal forming circuit that forms a pitch display signal that displays the letters of the note name or scale name and the pitch position for each semitone), the pitch is displayed on the screen of the monitor receiver. Projecting an interval table consisting of letters of note names or scale names based on the signal and pitch position display for each semitone, displaying a display based on the data display signal in the interval table, and in the video signal forming circuit. , a high frequency clock pulse associated with the horizontal synchronization signal of the monitor receiver is used to read out the memory circuit and form the pitch display signal; A pitch display device that enlarges and reduces each display on the screen.