JP3134408B2 - Frequency detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency detecting circuit for a display device capable of receiving video signals having a plurality of different synchronizing signal frequencies, detecting the respective synchronizing signal frequencies, and outputting the detection result. About.

[0002]

2. Description of the Related Art In recent years, with the diversification of application programs for personal computers, display devices having various resolutions have been required.
For this reason, there has been an increasing demand for a multi-mode display device that can switch and use a display having a plurality of resolutions with one display device.

In such a multi-mode display device, a frequency detection circuit for switching a plurality of resolutions is used.

A conventional frequency detecting circuit will be described below with reference to the drawings. In FIG. 2, a frequency / voltage conversion circuit 16 for outputting a voltage corresponding to the frequency of the horizontal synchronization signal input to the horizontal synchronization signal input terminal 19,
A first comparison circuit 17 and a second comparison circuit 18 for comparing the voltage converted by the frequency / voltage conversion circuit 16 with the reference voltage, and first, second, third, and , A fourth reference voltage 20, 21, 22, 23, and an adjusted circuit 15 for switching a circuit constant for each frequency of the input synchronization signal, and resistors 11 and 12 of the adjusted circuit 15 for switching for each frequency. It has transistors 13 and 14 for switching the resistance of the circuit to be adjusted 15 according to the output state of the first comparison circuit 17 and the second comparison circuit 18.

The operation of the frequency detection circuit configured as described above will be described below. First, the frequency / voltage conversion circuit 16 converts the voltage into a voltage corresponding to the frequency of the horizontal synchronization signal input from the horizontal synchronization signal input terminal 19. The converted voltage is supplied to a first comparison circuit 17 and a second comparison circuit 18.

[0006] The first comparison circuit 17 compares the converted voltage with the first reference voltage 20 and the second reference voltage 21 to determine the range between the first reference voltage 20 and the second reference voltage 21. If it is, a match signal is output and the transistor 14 is turned on. When the transistor 14 turns on,
The resistor 12 is used as a circuit constant of the circuit to be adjusted 15.

Similarly, the second comparison circuit 18 compares the converted voltage with the third reference voltage 22 and the fourth reference voltage 23, and compares the third reference voltage 22 with the fourth reference voltage. If the voltage is within the range of the voltage 23, a match signal is output,
The transistor 13 is turned on. When the transistor 13 is turned on, the resistor 11 is used as a circuit constant of the circuit 15 to be adjusted.

Here, if the first reference voltage 20, the second reference voltage 21, the third reference voltage 22, and the fourth reference voltage 23 are set to be different voltages, the horizontal The circuit constant of the circuit to be adjusted 15 can be switched between the resistor 11 and the resistor 12 according to the frequency of the horizontal synchronization signal input from the synchronization signal input terminal 19.

In the above example, the switching of two different horizontal synchronizing signal frequencies is described. However, when switching of two or more numbers is necessary, the comparison circuit, the reference voltage, the transistor, and the resistance of the circuit constant are used. By preparing as many as necessary for each, it is possible to respond.

In the above example, the switching is performed according to the frequency of the horizontal synchronizing signal. However, if it is necessary to perform the switching also according to the frequency of the vertical synchronizing signal, the same circuit as described above is configured for the vertical synchronizing signal. This can be achieved by:

[0011]

However, in the above-described conventional configuration, since an analog circuit is used for the frequency / voltage conversion circuit and the comparison circuit, it is necessary to take into account drift due to temperature, circuit variation, and the like. In addition, there is a problem that it is difficult to determine the frequency when the frequencies are close to each other. Further, if the corresponding frequency is increased or the horizontal frequency and the vertical frequency are determined, the comparison circuit becomes complicated and the circuit scale becomes large.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a frequency detecting circuit capable of changing a corresponding frequency by highly accurate frequency detection and rewriting of numerical data.

[0013]

In order to achieve the above object, a frequency detecting circuit according to the present invention generates a reference clock signal by an oscillation circuit using a crystal oscillator, and the reference clock signal is generated by a first counter circuit. A vertical frequency detection circuit that counts a signal in synchronization with the vertical synchronization signal, and detects a vertical synchronization frequency by temporarily storing a value of a first counter circuit in a first latch circuit every time a vertical synchronization signal is input; The number of horizontal synchronizing signals is counted by the second counter circuit, and when the number reaches a certain number, the number is output to the second latch circuit, and the value of the first counter circuit is temporarily stored in the second latch circuit. Then, a horizontal frequency detection circuit for detecting a horizontal synchronization frequency, and a vertical synchronization frequency and a horizontal synchronization frequency temporarily stored in the first latch circuit and the second latch circuit are input. Compared to the frequency information stored in the memory circuit, and constitutes by a comparison circuit for outputting a frequency detection information in accordance with the output information stored the result in the memory circuit.

[0014]

According to the present invention, the counter circuit counts the periods of the horizontal synchronizing signal and the vertical synchronizing signal on the basis of the clock signal output from the oscillation circuit having high oscillation accuracy, thereby achieving high accuracy. Frequency detection can be realized.

The detection of the horizontal synchronizing frequency is performed by counting a fixed number of periods by a second counter circuit.
Frequency detection accuracy can be further increased.

Further, by storing the comparison information of the frequency in the comparison circuit and the output result corresponding to the comparison information in the storage circuit, a programmable comparison circuit that can be changed according to the use situation can be realized. .

[0017]

An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, a vertical synchronizing signal input terminal 9 and a horizontal synchronizing signal input terminal 10 are provided, and an oscillation circuit 1 for generating a reference clock signal includes a crystal oscillator 2
Is used. As input a reference clock signal outputted from the oscillation circuit 1, a first counter circuit 3 that counts in synchronization with the vertical <br/> straight synchronizing signal inputted from the vertical synchronization signal input terminal 9, a vertical synchronizing signal input terminal 9 A first latch circuit 4 for latching the contents of the first counter circuit 3 with a vertical synchronization signal input from the second counter, and a second counter for counting and outputting a fixed number of horizontal synchronization signals input from a horizontal synchronization signal input terminal 10 Circuit 5, a second latch circuit 6, which latches the contents of the first counter circuit 3 by the output from the second counter circuit 5, a first latch circuit 4, and a second latch circuit 6. Compare the latched content with the frequency information,
A comparison circuit 7 for outputting output information corresponding to the result;
A storage circuit 8 for storing frequency information and output information used in the comparison circuit 7; and an adjusted circuit 15 for switching a circuit constant for each frequency of an input synchronization signal.
And the resistors 11 and 12 of the circuit to be adjusted 15 that can be switched for each frequency, and the transistors 13 and 14 for switching the resistance of the circuit to be adjusted 15 according to the output state of the comparison circuit 7.

The operation of the frequency detection circuit configured as described above will be described with reference to FIG.

First, the oscillation circuit 1 oscillates at the oscillation frequency specified by the crystal oscillator 2 and sends the reference clock signal to the first
To the counter circuit 3 of FIG. The first counter circuit 3 is reset by the vertical synchronization signal input from the vertical synchronization signal input terminal 9 and counts the reference clock signal generated by the oscillation circuit 1.

The first latch circuit 4 latches the contents of the first counter circuit 3 according to a vertical synchronization signal input from a vertical synchronization signal input terminal 9.

Here, the content latched by the first latch circuit 4 is that the first counter circuit 3 latches the count number immediately before being reset by the vertical synchronizing signal and reset by the next vertical synchronizing signal. , The period of the vertical synchronization signal is counted by the reference clock signal. This value is used as the detected value of the vertical synchronization frequency.

Next, the second counter circuit 5 is reset by the vertical synchronizing signal input from the vertical synchronizing signal input terminal 9, counts the horizontal synchronizing signal input from the horizontal synchronizing signal input terminal 10, and counts a certain number of times. After counting, it is output to the second latch circuit 6. The second latch circuit 6 receiving the output from the second counter circuit 5 latches the contents of the first counter circuit 3.

Here, the content latched by the second latch circuit 6 is the number of counts from when the first counter circuit 3 is reset by the vertical synchronizing signal to the horizontal synchronizing signal after a certain number of generations from the vertical synchronizing signal. Latch. Therefore, the value is a value obtained by counting the period of the horizontal synchronization signal for a fixed number of times by the reference clock signal. This value is used as the detected value of the horizontal synchronization frequency.

On the other hand, the storage circuit 8 stores a plurality of frequency range information and an output state of the comparison circuit 7 corresponding to the frequency range information.

In the comparison circuit 7, the detected value of the vertical synchronization frequency of the first latch circuit 4, the detected value of the horizontal synchronization frequency of the second latch circuit 6, and the plurality of frequencies stored in the storage circuit 8 The comparison is sequentially performed with the range information, and an output state corresponding to the comparison result stored in the storage circuit 8 is output.

If the frequency of the vertical and horizontal synchronizing signals detected as described above matches the state stored in the storage circuit 8, the signal output from the comparison circuit 7
Either the transistor 13 or the transistor 14 is turned on. When the transistor 13 is turned on, the resistor 11 is used as a circuit constant of the circuit to be adjusted 15, and when the transistor 14 is turned on, the resistor 12 is used as a circuit constant of the circuit to be adjusted 15.

Here, if the output state of the comparison circuit 7 is stored such that the transistors 13 and 14 are turned on and off according to the frequency state stored in the storage circuit 8, a vertical synchronization signal input The circuit constant of the circuit to be adjusted 15 can be switched between the resistor 11 and the resistor 12 depending on the frequency of the synchronization signal input from the terminal 9 and the horizontal synchronization signal input terminal 10.

In the above example, the switching of the two horizontal synchronizing signal frequencies is described. However, when switching of a greater number is necessary, the frequency information stored in the storage circuit 8 is stored in the storage circuit 8.
In addition, it can be dealt with by increasing the data of the output information and by increasing the number of output signals from the comparison circuit.

In the above example, the comparison is made with both the vertical synchronization frequency and the horizontal synchronization frequency. However, if either one is sufficient, the data of the frequency information stored in the storage circuit 8 is changed. That can be dealt with.

In the above example, the crystal oscillator 2 is used for the oscillation circuit 1. However, in a usage example where the accuracy of frequency detection is not strict, a ceramic oscillator or an LC oscillation circuit is used instead of the crystal oscillation circuit. Or the like may be used.

[0032]

As is clear from the above embodiments, according to the present invention, highly accurate frequency detection can be realized, and even a video signal of a close frequency can be accurately determined. Further, by changing data in the storage circuit, it is possible to realize an excellent frequency detection circuit capable of supporting various types of display devices without adding or changing circuit elements.

[Brief description of the drawings]

FIG. 1 is a block diagram of a frequency detection circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional frequency detection circuit.

[Explanation of symbols]

 Reference Signs List 1 oscillation circuit 2 crystal oscillator 3 first counter circuit 4 first latch circuit 5 second counter circuit 6 second latch circuit 7 comparison circuit 8 storage circuit 9 vertical synchronization signal input terminal 10 horizontal synchronization signal input terminal 15 Adjusted circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ identification code FI H04N 5/46 H04N 5/46 (58) Investigated field (Int.Cl. ⁷ , DB name) G09G 5/12 G09G 1/16 G09G 5/18 H04N 3/27 H04N 5/04 H04N 5/46

Claims (1)

(57) [Claims] 1. A frequency detecting circuit for a display device capable of inputting video signals having a plurality of different synchronizing signal frequencies and displaying corresponding to each of the synchronizing signals, comprising: a crystal oscillation circuit; A first counter circuit for counting a reference clock signal generated from the circuit in synchronization with a vertical synchronization signal; and a first latch circuit for temporarily storing a value of the first counter circuit for each input of the vertical synchronization signal. The configured vertical frequency detection circuit, the horizontal synchronization signal as a clock input, the vertical synchronization signal as a reset input, the number of the horizontal synchronization signal after the reset was released by the vertical synchronization signal was counted, and a constant value was obtained. A second counter circuit that is output at the time and an output from the second counter circuit to temporarily store a value of the first counter circuit. A horizontal frequency detection circuit including a second latch circuit, the first latch circuit,
The vertical synchronization frequency detection value and the horizontal synchronization frequency detection value temporarily stored in the second latch circuit are input, compared with the frequency information stored in the storage circuit, and the result is stored in the storage circuit. A comparison circuit including means for outputting frequency detection information in accordance with the output information.