JPS5836177A - Controller for inverter - Google Patents

Controller for inverter

Info

Publication number
JPS5836177A
JPS5836177A JP56134609A JP13460981A JPS5836177A JP S5836177 A JPS5836177 A JP S5836177A JP 56134609 A JP56134609 A JP 56134609A JP 13460981 A JP13460981 A JP 13460981A JP S5836177 A JPS5836177 A JP S5836177A
Authority
JP
Japan
Prior art keywords
output
circuit
signal
transistor
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56134609A
Other languages
Japanese (ja)
Inventor
Hiroyuki Masuda
博之 増田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56134609A priority Critical patent/JPS5836177A/en
Publication of JPS5836177A publication Critical patent/JPS5836177A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Abstract

PURPOSE:To obtain an output voltage waveform which has less content of non- theoretical harmonic by employing signal which is obtained by comparing a triangular wave signal with a waveform signal biased to a sinusoidal wave. CONSTITUTION:A pulse width modulation type inverter 4 which has a main circuit connected with a plurality of arms of a pair of switching elements 5a, 5b, 6a, 6b is formed between positive and negative DC buses. The first comparator 38 which compares a sine wave signal S10 with a triangular wave signal S2, the second comparator 3a which compares a waveform signal S11 biased to a sine wave with the signal S2, and AND circuit 40 and NOR circuit 41 which respectively receive the outputs of the first and second comparators are provided, and the outputs of the circuits 40, 41 are respectively applied as firing signals to a pair of switching elements 5a, 5b forming the arms of the main circuit.

Description

【発明の詳細な説明】 本軸嘴はインバータ1v11御装置に関し1時にパルス
1m ?、lI: K11l  (PWM)  型 c
VcIF(conetant  voltage  c
onstani frequcinay)  インバー
タに適用して好mZ%のである。
[Detailed description of the invention] This shaft beak has a pulse of 1 m at 1 o'clock regarding an inverter 1v11 control device. , lI: K11l (PWM) type c
VcIF (conetant voltage c
(onstani frequency) It is suitable for application to inverters with mZ%.

従来こ0種のインバータとして41図の主回路(1)と
、扇2図の1IlI#回路(2)電用い九ものがめった
0w41図におい1、+8)は直流゛蝋謔、(4)は単
相トランジスタ1ンパータで、直滝電番源(組の正及び
貝母−p及び)Il′14に谷アームを構成する一対の
スイッチ系子としてのトランジスタ(5a)〜(hb)
と、焦効電力帰達用ダイオード(7a)〜(sb)とt
Mする。谷アームから導出された出力−χ及びIにはフ
ィルタ用リアクトル(9)とフィルタ用コンデンナ叫と
でなるフィルタ(ロ)k弁してjIL荷−と、出力゛電
圧検出装置(至)とが嶺銃響れている。
Conventionally, as for this type of inverter, the main circuit (1) in Figure 41 and the 1IlI# circuit (2) in Figure 2, which rarely uses electricity, are DC (1, +8), and (4) is Transistors (5a) to (hb) as a pair of switch elements constituting a valley arm in the direct voltage source (positive and motherboard -p and) Il'14 of a single-phase transistor 1 patterner.
, pyroelectric power return diodes (7a) to (sb) and t
M. The outputs -χ and I derived from the valley arm are connected to a filter (b) consisting of a filter reactor (9) and a filter condenser, and a filter (b) to a jIL load, and an output voltage detection device (to). Minegun is echoing.

これに対して#呻回路(2)は褐2図に示すように出力
電圧基準器間1に接続された出力′電圧コントロー、I
&/−の出力を三角tiL夷生回生回路与えると共に。
On the other hand, # circuit (2) is connected to the output 'voltage controller, I
The &/- output is given to the triangular tiL regeneration circuit.

この三角tiL発生回路端及び正弦波発生回路−に対し
てインバータ出力8諷aτ決める亀氷i嘴を猛枕し、か
くして発tR器−の亀掘淘眞叙の正弦波値−11jJ3
11H角生回路四で得てコンパレータに)に−力の比較
人力として与えると共に、出力4圧羞114鐘副の出力
に相当する振幅tMする同じ周波数の三角波1d号E1
2に発生回紬肯で得てコンパレーターに開方の比較入力
として与える。
The inverter output 8aτ is strongly applied to the triangular tiL generating circuit end and the sine wave generating circuit, and thus the sine wave value of the sine wave of the generator tR is -11jJ3
11H Angle generator circuit 4) is given to the comparator as a force comparison human power, and a triangular wave 1d No. E1 of the same frequency with an amplitude tM corresponding to the output of the output 4 pressure 114 bell sub.
2, it is obtained from the occurrence times and given to the comparator as a comparison input for opening.

このコンパレーターの出力8sは谷トランジスタ(5す
〜(6bンにλ寸して点弧パルスPユ、〜P、bkイン
ターロック回路(27m)〜(28b)tヅrして与ん
・:I分配−線端に与えらtLo。
The output 8s of this comparator is given by the ignition pulse P, ~P, bk interlock circuit (27m) ~ (28b) with a width of λ to the valley transistor (5~6b): I distribution - tLo given to the line ends.

ここでインターロック回M(27a)〜(2ab)は累
6図に示す如く、谷分配パルスてA Li 10ゲート
(ムllrこ一刀の入力として与えると共に、遅倶回蹟
−τ通してムNDゲー) 1811に他力の人力として
与え、こi”L VC工#)遅延回−瞥の遅延時間分だ
け遅延した点弧パルスτ込出できるようになされてい−
b。
Here, the interlock circuits M(27a) to (2ab), as shown in Fig. The ignition pulse τ delayed by the delay time of the 1811 and the ignition pulse delayed by the delay time of the 1811 is designed to be able to be output.
b.

仄Vこ劇呻回鮎(2)の動作について説明丁り、・2お
上口#4(1)の創作は周知でめるO″′C説明τ省醋
する。
As explained about the action of 廄Vkogeki Ayu (2), the creation of ``2 Oueguchi #4 (1)'' is well known.

第2図において、出カー圧品早器(鴻の出力84及び出
力′−圧ラフイードバック16カ5が−f:九でれ出力
電圧コントローラーに与えられ、出力11!圧コントロ
一ラIAO出力毎号86&二三周波%生圓紬詞に[jl
i +Mされ、三角阪15号820波高値を酸化させて
出力′−圧を削−する、因みに三角lR15i号S2の
反高値が高くなれは出力電圧は低下し、低くなれば出力
電圧は増加する。しかし正弦荻発生回路四で発生する正
弦彼1!号81の成馬1厘は一足1区に保たれる。
In Fig. 2, the output 84 of the output voltage regulator (Kono's output 84 and the output '-pressure rough feedback 16 5 are given to the -f:9 output voltage controller, and the output 11! pressure controller IAO output every number. 86 & 23 Frequency% Ikuen Tsumugi [jl
i +M, oxidizes the peak value of Misumi Saka No. 15 820 and reduces the output '-pressure.Incidentally, if the anti-high value of Misumi Saka 15i S2 becomes high, the output voltage will decrease, and if it becomes low, the output voltage will increase. . However, the sine generated by the sine generation circuit 4 is 1! One adult horse of No. 81 is kept in one ward per foot.

しかるに正弦披見生回峰−及び三角波発生回路−は出力
胸a数に応じて定筐つ几周彼数を与える発S稽轡からの
(1v87に同期して義姉され、発生さn九正弦技g1
号S1及び三角彼備考82はコンパレータ轡に供輸され
る0例えば尭生盲n7を正弦波m号81がX相電圧に対
応する′tのであれば、コンパレータに)の出力85は
第1図のトランジスタ(5a)に対する理想点弧信号波
形となる。コ/パV−夕に)の出力85は分配器−に供
爾され、ここでトランジスタ(5りに対する理想点弧信
号から他のトランジスタに対する理想点弧信号が形成さ
れる。すなわち、トランジスタ(5b)に対する点弧個
号を作り、また逆位相にシフトしてトランジスタ(6a
)に対する点弧1g号を作夛、さらにこの逆位相備考を
反転してトランジスタ(6b)に対する点弧信号を作る
However, the sine wave generation circuit and the triangular wave generation circuit give a constant number of output waves according to the number of outputs from the S practice (synchronized with 1v87 and generated n9 sine technique). g1
No. S1 and the triangular hexagonal note 82 are supplied to the comparator 0. For example, if the sine wave m 81 corresponds to the X-phase voltage, the output 85 of the comparator is as shown in FIG. This is an ideal firing signal waveform for the transistor (5a). The output 85 of the transistor (5b) is fed to a distributor where the ideal firing signal for the other transistors is formed from the ideal firing signal for the transistor (5b). ) for the transistor (6a
), and further invert this anti-phase note to create a firing signal for transistor (6b).

ところが一般に電力用トランジスタはターンオフに数μ
城〜IIL10μ露の時間を要するため、この電力用ト
ランジスタを用いているli’11411)ランジスタ
(sats(6a)とMlilil)フンジスタ(5b
)、(6b)とが同時点弧して短M電眞が流れないLう
に、谷アームの一力のトランジスタがオフし7c倣−足
時閣(トランジスタのターンオフ11#閾の1.5〜2
ift)の仮に地方のトランジスタがオンするLうに点
弧18号τ与える必買がめ9、このタ1ミング&14金
ffiインターロック回路(271〜(28に+)にお
して点弧パルスの発生【遅延回路−の遅延時間分遅らせ
ることによって行なう。
However, power transistors generally have a turn-off time of a few microns.
Since it takes 10 μl of time to use this power transistor, the li'11411) transistor (sats (6a) and Mlilil) fungistor (5b
) and (6b) are fired at the same time and the short M current does not flow, the transistor with the most power in the valley arm is turned off, and 7c imitation - Ashikikaku (transistor turn-off 11# threshold 1.5 ~ 2
ift), the local transistor turns on and the ignition No. 18 τ is given. 9, this timing & 14-karat gold ffi interlock circuit (271 to (+ to 28)) generates the ignition pulse [delay This is done by delaying the signal by the delay time of the circuit.

しかるに正弦改備考B1と三角m信号82との比較を利
用してPWM@1号を得/)ため扇4図に示す工うな動
作をする。今X相電出に対する正弦阪として第4図ムに
示すものが用いられると、Y相電圧は逆位相となり、こ
れに対して三角aは1j11期の正弦波に対して複l!
個分発生する。な&v4鰍には1周期円に十〜数十の三
角波が生ずる工9に選定されているが凶ではsgBとし
て示している。
However, in order to obtain PWM @ No. 1 by using the comparison between the sine correction note B1 and the triangular m signal 82, the operation shown in Fig. 4 is performed. Now, if the sine slope shown in Figure 4 is used as the sine slope for the X-phase voltage, the Y-phase voltage will have an opposite phase, and on the other hand, the triangle a will be multiple l! for the 1j11 period sine wave.
Occurs separately. For na & v4 mackerel, it is selected as 9 in which ten to several dozen triangular waves are generated in one period circle, but in yaku, it is indicated as sgB.

かくすれば各トランジスタ(5&)〜(6b)に対する
理想点弧信号として畢4図B1〜B4に示すm号が発生
する。しかるにill上上インターロック回路(27m
)〜(281z) K !つて遅延されて点巌図示の↓
うに点弧がΔtだけ遅延し九点弧備考を生ずる。かくし
てインバータ(−)の出力端には第4図Cに訃い″[1
!111図示のような理想出力成形に対してインターロ
ックtglWt (27a)〜(28b)にLp点弧が
遅れ次点−図示の現実の演形が得られる。
In this way, the ideal firing signals for each transistor (5&) to (6b) are generated as shown in Fig. 4, B1 to B4. However, ill upper interlock circuit (27m
) ~ (281z) K! ↓
The firing is delayed by Δt, resulting in a nine-point firing note. Thus, at the output end of the inverter (-), as shown in FIG.
! 111, Lp ignition is delayed due to the interlock tglWt (27a) to (28b) with respect to the ideal output shaping as shown in FIG.

この孟うにP WM ill婢される averインバ
ーメO点弧偏点弧正号am号s1と三角波備考82との
比較に1って得る方法が採用される理由は、出力電圧t
N、影に含まれる低次高謂歇を低減し、小型の出力フィ
ルタでIfr定@[(例えば5−ン以下の電圧歪率を達
成することができるからである。因みにこの方法によれ
ば原理的に三角波数IMとじに場合、出力電圧高t14
tftの厳低久畝は11−1となり、Ml増せば厳低次
Ai、11波が高次となり、フィルタが小型になる・ ところがインターロックm [(27m)〜(28b)
 k用いる友め点弧備考P□1〜P、bL:D波形が乱
れるため、出力電圧波形が諷Ea彼形と異り、出力に低
仄(6択、5次、7仄・−・・・ンの非理随高調彼忙含
Mするという欠、4bMしていた。すなわち従来、2理
−′sb調彼のみに注目してフィルりを設Mtすれば、
フィルタは小さくなるがJW′I周技畝が^くなるため
、低次(5久、5次、7仄・・・・・〕の非理a尚両痰
が、IYi#幅されて歪率が増重、これに対して低次の
非理−高調波に注目、してフィルタr設針丁nぼ、フィ
ルタが大証になジ、こO―呻力式τ珠用し7c判点が失
われるという間jがりつだ。
The reason why the method of obtaining 1 is adopted for comparing the ignition deviation ignition positive sign am s1 and the triangular wave Note 82 is that the output voltage t
This is because it is possible to reduce the low-order harmonics included in the shadow, and to achieve an Ifr constant @[(for example, a voltage distortion rate of less than 5 -n) with a small output filter.Incidentally, according to this method, In principle, in the case of triangular wave number IM binding, the output voltage height t14
The strict low permanent ridge of tft becomes 11-1, and as Ml increases, the strict low order Ai becomes high order, and the 11th wave becomes high order, making the filter smaller. However, interlock m [(27m) to (28b)
Friendly ignition notes used P□1~P, bL: Because the D waveform is disordered, the output voltage waveform is different from Ea, and the output is low (6 selections, 5th order, 7th order...・In the absence of N's unreasonable harmonic high-key he busy-containing M, he was doing 4bM.In other words, conventionally, if you focused only on the 2-'sb-key he and set up the fill,
Although the filter becomes smaller, the JW'I circumference ridge becomes ^, so the low-order (5th order, 5th order, 7th order...) non-reasonable phlegm becomes IYi# width and the distortion rate increases. In contrast, focusing on the low-order irrational harmonics, the filter is set up, the filter is changed to OSE, and the 7c judgment is lost when the O-force type τ beads are used. That's a long time ago.

本発明は上述の従来のものの欠点tW去する次めにな石
九九もので、正弦阪偏考と三角tBl墳号との比較にL
つで得られる理想点弧11!号と、正弦直にバイアスτ
かけて得られる第2の成形15号と三角肢イd号とt比
較して得られる粥2の比較16カを利用して、F1!1
1トンンジスタとN[トランジスタのインターロックが
とれ、しかt点弧遅れにLる出力′1圧仮形の理論11
からのずれが少ない谷トランジスタに対する点弧信号t
”A生することがでさるp w M ml呻臘のCVC
Ir制婢鉄置を提装しエリとするものである。
The present invention eliminates the above-mentioned drawbacks of the conventional method, and is the next best thing to L.
Ideal ignition 11 obtained with! and the bias τ sinusoidally
F1!
Theory of 1-ton transistor and N [transistor interlock, but output '1' pressure hypothetical form 11 which goes low with t firing delay
The firing signal t for the valley transistor with less deviation from
``A student can do p w M ml groaning CVC
It is designed to provide an Ir system with iron equipment.

以下第2図との対応部分に同一符号を附してボすlI4
5図につ匹て本発明の一9IIr詳述するに、(55A
ン及びC55B)はそれぞれトランジスタ(5a)。
Below, parts corresponding to those in Figure 2 are given the same reference numerals and are marked lI4.
The present invention will be described in detail with reference to Fig. 5 (55A
and C55B) are transistors (5a), respectively.

(5り及び(6す5cbb>に対する点弧信号P  、
Pla     lb 及びP、、 I B、、 を発生する点弧1d号発生−
路で、それぞれ三角波発生回路−及び発振器−の出力8
2及びBe1t受ける。
Firing signal P for (5 and (6)5cbb>,
Ignition No. 1d generating Pla lb and P, , I B, , -
and the output 8 of the triangular wave generation circuit and oscillator, respectively.
2 and Belt received.

しかるに点弧信号発生1gl路(65ムノ及び(55幻
は同じ構成tもも、伺えば(55A)について詳細に示
すように、vJ6図ムにおいて実?m波形x1で示すよ
うに正弦[k発生する正弦tiL発生回路−と、点耐波
形x2で示すように正弦改形x1にバイアスtかけ九と
同様の改形を発生するM2技改形生回路−とt”lrL
、共に亀憑−切の出力87に同期し九出力奮発生するよ
うになされてiる。
However, as shown in detail for (55A), the ignition signal generation 1gl path (65 muno and (55 phantom) has the same configuration, if you ask (55A), in the vJ6 diagram, the sine [k generation A sine tiL generation circuit that generates a sine waveform x2, an M2 technique reform generation circuit that generates a modification similar to sine modification x1 multiplied by bias t and t''lrL.
, both of which are designed to generate nine outputs in synchronization with the output 87 of the Kamei-kiri.

正弦tlL発生回路丙の出力810は第1のコンパレー
タ1轡におiて三角波発生(ロ)略−の出力s2と比較
され、、 IW1様に礪2成形宛生回路4)の出力81
1は、142のコンパレータ1−′i4に分いて三周液
兄生Ig1間I槽・つ出力B2と比較される。I41及
び第2のコンパレータ両及び(轡の比較出力812及び
815UAND回路閣及びNOR回路汁l]に与えられ
、これにエジムND回路藺及びNOR四路田j刀)ら払
iに反転し罠パルス信号P□1及びP工、τ得る工うに
なされている。
The output 810 of the sine tlL generator circuit 2 is compared with the output s2 of the triangular wave generator (b) in the first comparator 1, and the output 81 of the 2nd generation circuit 4) is compared to IW1.
1 is divided into 142 comparators 1-'i4 and compared with three liquid outputs Ig1 and one output B2. I41 and the second comparator (comparison outputs 812 and 815 of the UAND circuit and the NOR circuit) are given to the outputs of the ND circuit and the NOR circuit, which invert the trap pulse. It is designed to obtain the signals P□1 and P, τ.

刀為くして思弧信号兄生回路(55幻のAND回路団及
びNO1回路田)の出力がそれぞれトランジスタ(5d
)及び(5b)に対する点弧信号P、a及びP□5とし
゛CC出出れ、また点弧備考発生回路C55B)・υ椰
Igl路、殉及びNOR回路間の出力がでれそれトラン
ジスタ(6a)及び(6b)に対する点弧1N−号P2
  及びP8゜とじて送出される。
The outputs of the thinking signal generation circuits (55 phantom AND circuit group and NO1 circuit field) are respectively transistors (5d
) and (5b), the ignition signals P, a, and P□5 are output from CC, and the output between the ignition note generation circuit C55B), υ, Igl, and NOR circuit is output from the transistor (6a). and ignition 1N- No. P2 for (6b)
and P8°.

ポ5図の/:s敢において得られた点弧1ぎ号仮形は次
の原理に基づいて形成される。今インバータ(4)から
44図Xに示すLうな理想出力電圧τ得ると丁7′L(
ブ、この理想出力菟圧忙得るため各トランジスタ(5a
)〜(6b)に与えるべき理想点弧信号波形としては第
4図D1〜D4で破1でボ丁工9なtのが必要でめる。
The ignition number pseudoform obtained at /:s in Figure 5 is formed based on the following principle. Now, if we obtain an ideal output voltage τ of L shown in Figure 44 from the inverter (4), then 7'L (
In order to obtain this ideal output voltage, each transistor (5a
) to (6b), the ideal ignition signal waveforms shown in Fig. 4 D1 to D4 are 1 and 9, respectively.

一、5側4図凡の理想出力電圧は12圏の時点tユ〜t
Allで成形が変化しているが、これらの時点は2図鍋
に分類て畠る。扇1の一合は、らるトランジスタの点弧
に同期して成形が変化する時点で、時点tze tgt
 ”@ ety* tgt t工よがこれに対応する。
The ideal output voltage for the 4th figure on the 1st and 5th sides is at the point t~t in the 12th area.
The molding changes in All, but these points are classified as 2-figure pots. The first match of fan 1 occurs at the time tze tgt when the shape changes in synchronization with the firing of the ru transistor.
”@ ety* tgt t-engineer corresponds to this.

例九ば階層 tよではトランジスタ(6b〕μ以前力・
ら点弧状總にaりり、この時点でトランジスタ(5a)
が点弧することに工9出力に電圧が発生している。
For example, in the ninth layer t and the transistor (6b) before μ,
At this point, the transistor (5a)
When the ignition occurs, voltage is generated at the output of the switch 9.

−2の一合は4Dるトランジスタの消弧に同期して、出
力成形が変化する時点で1時点1.、1.、1.、1.
-2 is synchronized with the extinction of the 4D transistor, and the output shaping changes at one time point 1. , 1. , 1. , 1.
.

t□。、t、がこ九に対応する。t□. , t, corresponds to Koku.

筐を別の一点力島らみればX相に接伏されたトランジス
タ(5’L(5b)の点弧1B゛号が変化する時点も□
If we look at the case from another point, we can see that the point at which the firing number 1B of the transistor connected to the X phase (5'L (5b) changes) is also □
.

t、、 t、、 t、、 1−1゜、t工□ と、Y相
に接続されたトランジスタ(6aJt(6b)の点弧1
5−号:が変化する時点1、、111.1. 、1.、
1.、1よ、とに2分することもできる。
t,, t,, t,, 1-1°, t □ and the firing 1 of the transistor (6aJt(6b)) connected to the Y phase.
No. 5-: Time point 1 when changes, 111.1. , 1. ,
1. , 1, and can also be divided into two.

この↓うに出力電圧波形の変化は正の′眠源母−F鶴の
トランジスタと負の141+源母−N圓のトランジスタ
の、オンオフが入れ洟V勺時点C必ジ、し〃1゛ムどち
らか一万のトランジスタのオン又Vエオフに同層jして
起ることが分かる。従って一力Qト2ノジスタのオンに
同期して出カーttj:、a形が塚化丁0賜合;・よ他
方のトランジスタのオン時点τ迩らぜル2“r【い(例
、t(ズt0゜ し、1戸も夷4:凶D1〜D4から、出カー間′1圧傭
41J E ) カ正(X<[r4単にして) QJ 
411 vc i・裏、トランジスタ(5a、) I 
(61))には(里;d点弧百号τ与え。
This change in the output voltage waveform is caused by the positive and negative transistors being turned on and off. It can be seen that this occurs in the same layer when 10,000 transistors are turned on or turned off. Therefore, in synchronization with the on of the first transistor Q and the second transistor, the output signal ttj:, the a type is turned on. (Zt0゜, one house is 4: From D1 to D4, the output car '1 pressure 41J E) Ka correct (X < [r4 simply) QJ
411 vc i, back, transistor (5a,) I
(61)) is given (ri; d firing 100th τ).

トランジスタ(sb)+(、’+a)には点弧を早のか
り消弧′tn+=ぜた点弧・Ti−11r与えればLい
。出力)諷r、tl’−f l>E ’h人の1合、は
、二の逆でろ・5゜こf’L ’ffi ′A ]1丁
6ytottζLユ416 図A K yx< f L
 ’) VC正弦波(Xl)と三AtRrR工τ比較し
て憎られm点弧18号812(,46図Bl)と旧弦改
にバイアスどンハ(・すて倚られる波形x2と三角彼T
RIと(比&L−C(4らrLる1M号5t5(,16
−82)のA埋・λ1発生すればよい6丁なVち両省の
AIJD@とれば、Fly)クンジスタに対する点弧1
6号P、J薦4図C1)が侍しれ、NOR’jとれはN
d)ランジスタに対する点IA佃号P工ゎ(−6図02
)が侍られる。
If the transistor (sb)+(,'+a) is turned on quickly and extinguished by 'tn+=staggered firing/Ti-11r, L is satisfied. Output) R, tl'-f l>E 'H's 1 go is the opposite of 2.
') Comparing the VC sine wave (Xl) and the three AtRrR engineering τ, the hated m firing No. 18 812 (, 46 fig.
RI and (ratio & L-C(4ra rLru 1M No.5t5(,16
-82) A-build/λ1 should be generated for 6 guns, V, AIJD @ of both ministries, Fly) ignition 1 for Kunjista
No. 6 P, J recommendation 4 figure C1) is served, NOR'j is N
d) Point IA P work for transistor (-6 Figure 02
) is attended.

ここでH42の波形x2について述べる。こV成形x2
μ正へ波X1にバイアスτかけて得られる。
Here, the waveform x2 of H42 will be described. This V molding x2
It is obtained by applying a bias τ to the positive μ wave X1.

バイアスは正弦’0IX1が正の時は正力回に、負のに
#は負力回にかげる。またバイアス鴛μ−建にしてt工
いしCCo時改形成形工及びXl、及びTRX及びx2
の対応する2爪闇の偏差は一足にはならないが一作土間
趙にはならないン、ま7CCれt−足V規則に従って菱
1ヒさせて%jい。
When the sine '0IX1 is positive, the bias is set to positive force, and when it is negative, # is set to negative force. In addition, the bias rod is μ-built, T-shaped, CCo time modification molding, Xl, and TRX and x2.
The deviation of the corresponding 2-claw darkness will not be one pair, but it will not be one-crop Doma Zhao, so let's make it 7 CC and 1 Hi according to the V rule.

j145図の点飄偏力釦生回1(55ム)に2いて、バ
イアスτかけられた1g−1811(#146図の波形
X2ンと三角波1g号82(扇6図ムの波形TR工)と
がコンパレーターで比IIRされて謝る図B1にボ丁工
″)にバイアスtかげられに偏力811が大さいとam
塊「1」となる比較出力812が得しれる。
1g-1811 (waveform X2 of figure #146 and triangular wave 1g No. 82 (waveform TR work of fan 6 figure)) with bias τ applied to the dot bias button regeneration 1 (55mm) in figure j145 If the bias force 811 is large due to the bias t shown in Figure B1, the bias force 811 is large.
A comparison output 812, which is a block "1", is obtained.

また正弦腋1g号811(側6図ムの成形X1)と三角
tiL侶号信号(麟6図ムog形TR工)とがコンパレ
ーターで比較されて第1−B2に示す工9に正弦IIL
II号1310が大aいとき1境「1」となる比較出力
815が侍られゐ。
In addition, the sine axillary 1g No. 811 (forming X1 of the side 6 figure) and the triangular tiL signal (the 6th figure of the arrow) are compared by a comparator, and the sine IIL is shown in the work 9 shown in No. 1-B2.
When No. II 1310 is large a, a comparison output 815 which becomes "1" at one boundary is observed.

従ってムND圓劾蘭刀為らは第6図C1にが丁如く、比
較出力812及びB15がパに鑓埋「1」とlΦAND
lij力が侍られ、これ力SトランジスタニリVc刈す
る点−偏力P□1として退出される。1にノア1u紬1
411からに第6図02にボ丁如く、比値出力812及
び815が共にFJd壇「0」のと&調理「1」となる
MOR出力が得られ、これがトランジスタ(5b)に対
する点弧信号P1つとして退出てれる。
Therefore, as shown in Figure 6 C1, the comparison output 812 and B15 are ``1'' and lΦAND.
The lij force is applied and is output as the bias force P□1 at the point where the force S transistor Niri Vc is cut. 1 Noah 1u Tsumugi 1
From 411, as shown in FIG. 6 02, a MOR output is obtained in which the ratio outputs 812 and 815 are both FJd "0" and "1", and this is the ignition signal P1 for the transistor (5b). You can leave as one.

+1’J昧に第5凶の点弧16号発生ロ路(55B) 
Vこ9いて、トランジスタ(61及び(6b)に対する
点弧信号P、、  &び’E2b2EfS出す′rLイ
5th ignition No. 16 occurred at +1'J (55B)
V9 generates firing signals P, &'E2b2EfS for transistors (61 and (6b)).

? a しかるに第6L!!JC1及びC2の点孤傷号Pよユ及
びPli) I Pil&及びP2bハ第4図D1〜D
4について上述し71:jうにパルスの立上!llτ遅
らぎ〃1つ立下りt早め7c波形になっており、仮って
44図1について上述し7c理想゛1圧匝形τもつ出力
・rインバータ(4)から得ることかでさる。
? a However, the 6th L! ! JC1 and C2's Pil & Pil & P2b Figure 4 D1-D
4 is mentioned above and 71:j rise of the sea urchin pulse! The waveform is 7c, with the falling edge t being one step earlier, and the output r being obtained from the output/r inverter (4) having the 7c ideal 1-indentation shape τ as described above with reference to FIG.

な2上述の実211F11?11では不免明τ早相のト
ランジスタインバータに適用し7c−合につい工戊明し
i’tが、相数は任意にTi短でさ、筐にインバータの
栴戚−目励式のものでめればトランジスタ以外の他のス
イッチ重子を便用するものであって工い。
2 In the above-mentioned example 211F11?11, it is applied to a transistor inverter with an unexplained τ fast phase. If it is an eye-excited type, it is convenient to use a switch element other than a transistor.

以上の1うに不角例によれは、三角tiLgi号と、正
弦tiLにバイアスtかけ友鵬2の波形偏力との比較に
1って得られる(1号を用いたことにLり1聞手411
11路に1って非理幽尚−4獣の宮(振が少ない出刃域
圧IjLY!fit得ることがでさ、従つτフィルタV
−J61小WVcし4447パ−fiK44mでI’b
The above 1-uniangle example can be obtained by comparing the triangular tiLgi and the waveform bias force of Yuho 2 with a bias t applied to the sine tiL. hand 411
1 in 11 is unreasonable - 4 beast palace (it is possible to get the blade area pressure IjLY!fit with less swing, so τ filter V
-J61 small WVc and 4447 par-fiK44m I'b
*

【図面の簡単な説明】[Brief explanation of drawings]

第1図は単相トランジスタcvcy  インバータの王
tgIw6髪示す砿絖図、爾2図は従来のP W M 
1ii11岬餉直を示すブロック図、第6図は第2図の
インターロック回路O評細を示す砿就図、44−μ第2
凶のPWMIlillii1表直の制作τ帆明するため
Q1dカwL形図、45図に不発明に依るPWM劇−表
置の一?ll示すブロック図、第6図μ部5凶の鯛作諷
塩O説明に供する慎号仮形凶でりゐ。 (1):主(9)路     t2) : 1itt制
御回路I8);区滝’K(IA (旬:半相トランジスタインバータ (5a)〜(6b) : )ランジスタ(7a)〜(8
b):ダイオード (9):リアクトル   叫:コンデンサ(剥:負荷 
     uIIll:鴫圧慣出麹隠飢:出力亀圧蕪早 1−二出力゛駐圧コントローラ 例、(刈:正弦波晃生回鮎 ・Jj:三角N兄生回w1  両二兄振−−〕:コンパ
レータ  −;:分配会 (27a)〜(28bJ :インターロックnra−:
迦姑圓鮎    四):ムIJDゲート(55A)、(
55B) : トランジスタ点弧1M号%生口路t’l
 *第20反形見生回鮎 I殉、轡:コンパレータ tfl:ANDt!111%       tl−幻 
:N0R1falJ16代理人 S 野 伯 − JI      Jl
Figure 1 is a wire diagram showing the king of single-phase transistor CVCY inverter TGIW6, and Figure 2 is a conventional PWM.
1ii11 A block diagram showing the configuration of the cape, FIG. 6 is a diagram showing the details of the interlock circuit shown in FIG.
The PWM play based on uninvention in Figure 45 - the PWM play based on uninvention in the Q1d Kaw L shape diagram to make the production of the evil PWM lillii 1 front table? The block diagram shown in FIG. (1): Main (9) path t2): 1itt control circuit I8); Kutaki'K (IA (season: half-phase transistor inverter (5a) ~ (6b): ) transistor (7a) ~ (8
b): Diode (9): Reactor Shout: Capacitor (Remove: Load
uIIll: Drop pressure adjustment: Output Tortoise pressure Kaburaya 1-2 output゛Parking pressure controller example, (Kari: Sine wave Kosei Kaiyu, Jj: Triangle N brother's life w1 Both two brothers vibration--): Comparator -;: Distribution meeting (27a) ~ (28bJ: Interlock nra-:
Kaguen Ayu 4): Mu IJD Gate (55A), (
55B): Transistor ignition 1M No. % Ikuchiro t'l
*The 20th anti-memory student Kai Ayu I martyred, 轡: Comparator tfl: ANDt! 111% tl-phantom
:N0R1falJ16 agent S No Haku - JI Jl

Claims (1)

【特許請求の範囲】[Claims] +f流正及び負母線間に一対のスイッチ系子でなる恒数
のアームを接続しに主1g1紬tMするパルス暢叢調製
インバータにおいて、正弦波信号で三角波tgvと比較
する第1の比較回路と、正弦波にバイアスtかけ7を波
形信号を三角波便号と比較する#!2の比1!Igl路
と、上記扇1及び第2の比較回路の出力tそf′L−t
′れ受けるムIJDl路及びMOR囲路とC有し、上記
AND回路及び上記N0RIIul路の出力を上記主!
27NL:D谷アームを傅成する一対のスイッチ系子に
点弧g1号としてそれぞれ与えることr:特徴とするイ
ンバータ!Ill 飾装it。
+f flow A first comparison circuit that compares a sine wave signal with a triangular wave tgv in a pulse flow adjustment inverter that mainly operates 1g1tM by connecting a constant arm consisting of a pair of switch system elements between the positive and negative busbars. , apply bias t to the sine wave and compare the waveform signal with the triangular wave symbol #! The ratio of 2 is 1! Igl path and the outputs tsof'L-t of the fan 1 and second comparison circuits.
' has an IJDl path and a MOR circuit that receive the signals, and the outputs of the AND circuit and the N0RIIul path are connected to the main!
27NL: Giving ignition g1 to each of the pair of switch elements forming the D valley arm. r: Characteristic inverter! Ill decoration it.
JP56134609A 1981-08-26 1981-08-26 Controller for inverter Pending JPS5836177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56134609A JPS5836177A (en) 1981-08-26 1981-08-26 Controller for inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56134609A JPS5836177A (en) 1981-08-26 1981-08-26 Controller for inverter

Publications (1)

Publication Number Publication Date
JPS5836177A true JPS5836177A (en) 1983-03-03

Family

ID=15132395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56134609A Pending JPS5836177A (en) 1981-08-26 1981-08-26 Controller for inverter

Country Status (1)

Country Link
JP (1) JPS5836177A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61109492A (en) * 1984-10-31 1986-05-27 Mitsubishi Electric Corp Controller of ac motor
US5099408A (en) * 1989-05-23 1992-03-24 Kasuga Denki Kabushiki Kaisha System for controlling a PWM inverter having delay time compensation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61109492A (en) * 1984-10-31 1986-05-27 Mitsubishi Electric Corp Controller of ac motor
US5099408A (en) * 1989-05-23 1992-03-24 Kasuga Denki Kabushiki Kaisha System for controlling a PWM inverter having delay time compensation

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