JPS583253B2 - multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a virtual memory multiprocessor system.

So-called microprocessors, which are manufactured using large-scale integrated circuit (LSI) technology, are conventional integrated circuit devices (IC).
It has a higher (price)/(performance) than processors assembled in ), and is widely used for various types of control and as a component of extremely small-scale computers (minicomputers).

However, due to manufacturing technology constraints, the functionality of microprocessors is limited to that of the central processing unit of a minicomputer.

Therefore, in order to realize a conventional medium-sized or larger general-purpose computer using this microprocessor, a so-called multiprocessor system is used in which a plurality of processors are combined to form a single system.

On the other hand, in recent years, virtual memory methods have become popular in single-processor or dual-processor systems with the aim of improving program compatibility, program compatibility, and main memory utilization. It has become well-established and its effectiveness is widely recognized.

In view of this situation, it must be considered that the introduction of a virtual memory method is a basic condition even in multiprocessor systems that use a large number of microprocessors.

Virtual memory is a system in which main memory and auxiliary memory are seemingly integrated, and when information requested by the processor has not been loaded into main memory, the system automatically transfers information from auxiliary memory. This is the method to do it.

This allows the program to treat and use the storage space of the auxiliary memory in the same manner as the internal memory, and is freed from the trouble of overlays.

The virtual memory method, which is an excellent method, has already been technically established and widely used in single-processor or dual-processor systems as described above, but it is used in systems with a larger number of processors. Regarding multiprocessor systems, there is no known technology that can be put to practical use yet.

This invention provides a new type of multiprocessor system that is easy to implement and extremely flexible for increasing or decreasing the number of processors. It is possible to easily realize a high-performance electronic computer system using virtual memory.

A distinctive feature of this invention is that it eliminates the need for a conventional operating system to manage the entire system.

This not only ensures system flexibility, but also eliminates the traditionally problematic problem of creating large operating system programs.

Another feature of the system of the present invention is that a plurality of processor groups and a storage system are logically separated, making the system configuration extremely clear.

This eliminates the problems of multiprocessor systems that were traditionally considered cumbersome to design.

The system of the present invention is based on the novel idea of including a bit in the instruction word format of each processor to specify whether it is a common storage area or a dedicated storage area.

By using such an instruction word format, the configuration of the virtual storage system can be simplified, and programs and data can be extremely easily shared between processors.

Next, the present invention will be explained in more detail using examples.

In the embodiment shown in FIG. 1, 1 is a virtual storage system, which is connected to each processor 31, 32, etc. through a common bus 2. In the embodiment shown in FIG.

The common bus 2 includes a bus arbiter 21, which manages how to grant the right to use the common bus to each processor.

This bus arbiter is known, for example, as described on pages 242 to 244 of the Journal of the Institute of Electronics and Communication Engineers Vol. 57-D, No. 4.

The main component of the virtual memory system 1 is a paged main memory 11 consisting of IC memory or core memory.
, a large-capacity auxiliary storage device 12 consisting of a magnetic drum or a magnetic disk, and a main storage device 1 that stores the referenced status and determines which page stores information that is least likely to be referenced in the near future. a main memory page reference status memory circuit (PRC) 13 that always knows whether the AT)
14, and a main memory relocation control circuit (MR
C) 15.

Reading or writing of information requested by each processor 31, 32, etc. by a logical address through the common bus 2 is converted into a physical address in the main storage device 11 by the AT 14 before being actually accessed.

If the page containing that logical address does not exist in the main memory 11 (page fault), the MRC 15
The page is transferred from the auxiliary storage device 12 to the main storage device 1.
1 and then accessed.

At this time, the PRC 13 specifies which page of the main storage device 11 to load.

As is clear from the above description, the virtual storage system 1 uses only the logical address requested from the common bus 2 as a clue, and is completely unaware of which processor issued the request.

Therefore, each processor must issue an address signal on this premise.

Therefore, the processors 31, 32, etc. have the following architectural features.

This will be explained next.

FIG. 2a is a diagram of the instruction word format of the processor.

In this figure, OP is the instruction code section, MD is the modification section, which specifies, for example, indirect address specification or absolute address specification.
Further, AD is an address designation section, which is basically the same as that of a conventional single child address type computer.

The novelty of the system of this embodiment is that the MD section is provided with a bit that specifies whether it is a common storage area or a dedicated storage area.

In FIG. 2a it is designated D/C.

Figure 2b shows the memory address register (M
FIG. 2 is an explanatory diagram of the configuration of AR.

The MAR is divided into two parts: a PN part indicating the processor number, and an ADR part indicating the logical address within the processor storage area.

The width (number of bits) of the ADR section is the same as the width of the instruction word shown in FIG.

In this processor, instruction fetching is the same as in a normal computer.

In other words, a signal from the control circuit in the processor indicating that the processing of the previous instruction has been completed causes the instruction counter IC in the processor to be incremented, its contents are transferred to the ADR section of the MAR, and the contents of this MAR are subsequently incremented. It is sent to the virtual memory system via the common bus 2.

Since the upper digit of MAR contains the processor number, it will not be confused with a logical address from another processor within the virtual storage system 2.

Next, the instruction word read from the virtual memory system 2 is sent to the memory data register MDR in the processor, and the instruction word is sent to the memory data register MDR in the processor.
Only the P portion is further sent to the instruction register IR.

Next, depending on the contents of the IR, if the instruction word requires an operand, the MD section of FIG. 2a is checked.

Here, if the D/C bit is 1, it means that the operand is in the dedicated storage area of that processor.

Therefore, at this time, a code unique to that processor is entered into the PN part, which is the upper bit of the MAR shown in FIG. 2b.

If the D/C bit is 0, it indicates that the operand is in a common storage area that can be used commonly by all processors in this system, and the PN part of the MAR has a unique memory area that indicates that it is a common area. The code can be entered.

Area specification of an instruction word (program) can also be performed to a common storage area using an area specification branch instruction.

Only by this command can the contents of the area designation code portion of the instruction counter IC, which has the same configuration as the MAR shown in FIG. 2b, be changed.

As is clear from the above description, in the system of this embodiment, each processor has its own storage space, and also has a common storage space that can be commonly accessed by all processors.

Thus, for example, if a reentrant compiler is placed in a common storage space, it can be used by any processor, resulting in extremely efficient use of storage.

The same can be said about data.

Also, as is clear from the above discussion, there is no need for a traditional operating system to manage the entire system;
Therefore, there are no problems associated with writing large-scale operating system programs.

Regarding system scale flexibility, the PN in Figure 2b
The number of processors can be increased or decreased within the limits imposed by the number of bits in the unit.

Furthermore, in the system of the present invention, the plurality of processor groups and the storage system are logically separated, and as a result, the system configuration is extremely clear and design is easy.

Although the embodiments have been described in detail above, it goes without saying that the present invention is not limited to these embodiments.

For example, in the above embodiment, the instruction word format of the processor is a single address format, but it can be easily applied to processors with other instruction formats such as a two-address format. , it is also easy to implement with a variable word length instruction format processor.

Additionally, when a page fault occurs in the form of a common bus, system performance may deteriorate because other processors are unable to use the common bus during the process. This can be easily avoided by adding a function that temporarily disconnects the processor from the bus.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the configuration of a system according to an embodiment of the present invention, in which 1 indicates a main storage device 11 and an auxiliary storage device 12.
, address conversion circuit 14 and main memory page reference status memory circuit 1
3 and a virtual memory system consisting of a main memory relocation control circuit 15; 2 a common bus including an arbiter 21;
1.32, etc. are processors. FIG. 2 is an explanatory diagram a showing the instruction word format of the processor in the embodiment of FIG. 1, and an explanatory diagram b showing the configuration of a program counter.

Claims (1)

[Claims] 1 A memory address that is in the instruction word format with a bit that specifies whether the logical address of the operand is a common storage area or a dedicated storage area, and that has a bit area that holds the processor number or code information of the common storage area that corresponds to this bit. A virtual memory system consisting of a plurality of processors having registers, a main memory device, an auxiliary memory device, and a memory management circuit consisting of an address conversion circuit, a main memory page reference status memory circuit, and a main memory relocation control circuit,
A multiprocessor system characterized by having a configuration in which they are connected by a single bus.