JPS5832297A - Control circuit for nonvolatile memory - Google Patents

Abstract

PURPOSE:To make circuit integration easy, by switching each state of writing erasing and reading of memory through different DC voltages. CONSTITUTION:A titled control circuit is provided with a circuit 2 detecting the value of a DC voltage VDD at a power supply terminal 1, a constant voltage power supply circuit 3, a circuit 4 generating a readout pulse of a low voltage for the readout of a memory M, a write/erase signal generating circuit 5, a circuit 6 generating a suitable high voltage to place the memory M into four states, and an output latch circuit 7. The voltage VDD is changed to tri-state values such as OV, -15V and -30V. When a data terminal 8 is used as an input terminal, and a levelof 1.0 of erase/write selection signals S (WR, ER) is applied to this terminal as input signal, and when the terminal 8 is used as an output terminal, a readout output of the memroy M can be obtained from the terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile memory control circuit suitable for use in a nonvolatile memory device, which is applicable to, for example, a last power memory, a last channel memory, etc. of a television receiver.

A last power message is a message provided especially in a remote control television receiver having an electronic tuning device, and which stores the on/off state of a power switch. The last channel memory is a memory that stores the last broadcast channel of a television receiver KB having an electronically tuned channel. If such a memory is installed in the television receiver, when trying to operate the television receiver with a timer, the television receiver can be kept in a cold operating state. obtain.

The purpose of this paper is to propose a fast control route for non-volatile memory suitable for IC implementation. .

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention will now be described in detail with reference to FIG. Figure 1 shows a 1-bit 1-chip IC storage device!
He praises non-volatile memory and its control circuit.

M in the upper right corner of FIG. 1 indicates non-volatile memory. The example is a P-channel type MN 08 (metal nitride oxide semiconductor) field effect transistor. This memory M has a drain D, a source S%ge, -toG
and a substrate 8B.

This mail & 9M is read RD, write WR, erase 18
B, exhibits the state of 4') of inactive NOP. The contents of these four states are as follows.

The memory contents of RD2 memory M can be seen.

WR: Memory MK “IJ is set.

B8: Memari MKrOJ is set.

Nor: Even if the power is turned off, the memory contents will not change.

The 111th "t" shows the following circuit elements.

Zener diode: DI -Ds Resistor: R1-Rm Capacitor f: CI MO8 field effect transistor (P channel type): Q1
~Qu4/A-): IVt~IVy AND circuit: Mu1 NAND circuit: Nmu1~Nmu3 NOR circuit: N11~NRs (1) is the power supply terminal, (8) is the data terminal (input/output terminal) In addition to this, there is also a ground terminal (not shown). Power supply terminal (1) K'' supplied DC voltage VDDa,
+*v (when tllllll is disconnected>, -1sv and h-5
ov changes to s value. When the data terminal (8) is an input terminal.

Write/erase selection signal 5 (WB/
1B')%, or "1", is supplied, and in the case of an output terminal, the readout output of M is obtained from this. The relationship between read RD, write WR and erase is as follows.

Table 1 (2) shows a voltage level detection circuit, which detects the value of the DC voltage VDD at the power supply terminal (1). This detection circuit (
In 2), resistor R1 and four Zener diodes D
1 to D4 are sequentially connected in series between terminal (1) and ground, and the midpoint of the connection between the diodes, Ds and D4 is connected to the inverter Tl.
Connected to the gate of transistor Q2 of Al&<28>. A resistor @Rt is connected in parallel to the diode 7D4. Qs is a silane resistor as a load of the inverter circuit (2a). A non-operation detection signal 8 (NOP) #u is provided at the output end of the inverter circuit (additional), that is, point '1'.
tlt! :tL, VDD>-5ov, Jia? )V
DD--11V#) @ 8 (NOP) -r I
J, when VDD≦-30V, 8 (NOP) is obtained.

(3) is a constant voltage power supply circuit. Terminal (1) is connected to point PK via a low resistance resistor Rs. Four square energy diodes (m) are connected in series between point P and ground in sequence. F tune transistor Q3 with gate connected to point TK
The drain and source of are connected to both ends of a series circuit of diodes Di, D. still.

The point at which the diodes Dy and D are connected is set as a point = or <
"t leh, voltage Vpp#s -1!iV>VDD>
-30Vf), one point PK constant voltage -13VC) transistor Q3 turns on), one point LK constant voltage -S,
SV is obtained respectively. Also, the voltage VDD is −sov≧VD
When D, the constant voltage at one point P is -2@V() uy resistor Q
s is turned off). Furthermore, /I □ Ode D・
, -13V constant voltage output terminal (9
) is derived.

(4) is a pulse generation circuit, which uses a low voltage (to avoid destroying the memory contents) readout pulse (
The duration is several hundred voices (5ec). That is, when one point is grounded through resistor R4, K.

The resistor Ri-W is grounded through the capacitor C1.

The midpoint between the resistor Ri and the capacitor C1 is connected to one input terminal of the NAND circuit Nλ1'o through the inverter IVs, and the zero point is connected to the other input terminal of the NAND circuit NAI. The output terminal of the NAND circuit NAs is connected to the input terminal of the output terminal IVs. The readout circuit (5) from the inverter IVx is a write/erase signal generation circuit. Non-operation signal from point T & (NOP
) is inverted by passing through the inverter IVm,
The negative phase' immobile signal 8 (NOP) is a NAND circuit N illusion,
It is connected to one input of each of the NAs. In addition, each output terminal car of the inverter Iv of the output latch circuit (7) and the tour path NRs, which will be described later, is a NAND circuit NAx,
NAs #) 4) Other 1: Connected to the output terminal. So, Nando circuit NAm, N
Each output of As is connected to the pot input terminal of an inverter IV4, IVi, respectively. And inverter IV4゜I
Write pulse 8 (WR) and erase pulse 8 from Vi, respectively.
(KB) is generated. And signal generation circuit (5)"C
')! , Direct R voltage VI) 1) KaVDD −-30V
F) t.

If the long sword of the data terminal (8) is “1”, write signal s
(wh) is ``G J teToshikf, erasure message 41B
(Bn) is generated respectively.

Next, circuits around the memory M will be explained.

Gate transistor Q- whose source S of 1% M is high voltage
Grounded through the drain and north of the

The output terminal of the pulse generation circuit (4) is connected to the load transistor Qu (the terminal (9) derived from its gate is connected to the terminal (9) K of the constant voltage circuit (3)) - the high voltage gate transistor Qm. Note ν between drain and source
Connected to the drain D of M.

(6) is a high voltage generating circuit (gate circuit), which is used to apply an appropriate voltage to the memory νM in order to place the memory νM in the four states mentioned above.

Q4~Qs are for gate) 0 point P which is 2 transistor is F tune transistor Q4. 1 of memory M through the drain and source of Q@, respectively.゛Husband＾Gate O% Nap Straight 8B
K-connected. Memory M gate and substrate 8
B is grounded between the drains and sources of transistors pQs and Qm, respectively. The gate of Memo 9M is connected to the pulse generation circuit (
Write pulse 8 (WR) from the 0 selection signal generation circuit (5) connected to the output terminal of 4) is supplied to the gate of the transistor Q4.Erase pulse 8 (ER) from the 0 selection signal generation circuit (5) is transistor Q8. Q- is supplied to each gate.

Reverse phase erase pulse from selection signal generation circuit (5)! 1(I
R) is supplied to each gate of transistors Qs and Qs.

A non-operation signal 8 (NOP) from the detection circuit (2) is supplied to the gates of transistors Qma and Q*, respectively.

(7) is an output latch circuit. αα is an 88-type flip-flop circuit consisting of a Noah circuit NFazeyuki, Nns,
A (set) terminal and an R (reset) terminal are led out from one input terminal of each of the NOR circuits NR* and NRs. Reverse inheritance pulse "(RD) from pulse generation circuit (4)"
When ``'7'' is open, the 1'''' and 2-' terminals (8) are connected to the other input terminal of the AND circuit A1. The output of the AND circuit Al and the output from the connection midpoint of the transistor pQ"*Qll are supplied to the NOR circuit NRsic, and its "
Output is 7sg 7th circuit α0 R (reset))j
It is supplied directly to the I/L child and to the S (set) terminal via the inverter IVg. 7 lip-flop circuit a
The output terminal of e (output terminal of NOR circuit NRz) is connected to data terminal (8)k via a 3-state inverter Vma. This inverter XVt is controlled by a non-operation signal 8 (Nor)l from point τ. Inverter IVy is turned off when VDD is -5ov, and the data terminal (
8) will be prohibited from appearing.

Next, write WR1 read, RD, erase FA of mecans M.
Voltages and control signals of source 8, drain D, gate G and substrate 8B in each state of IL and non-operating NOP, namely write pulse 8 (WR), read 1
j31. Pulse 8 (RD), ff4 left hull x 8
(ma) and the relationship with the non-operation signal 8 (NOP) ka<ru 3.

Table 2 1!3 Table 4 Table 5 Let's explain the operation of Figure 1 with reference to Figure 12 below. Second
The figure is DC voltage VDD')
tllll-F (8) I) Shin-#! 8 (8) I) tl type, Figure 2 shows the waveform of the C-operation signal 51 (NOP), the second figure shows the waveform of the voltage V (L) at point L, and the second rI!
J1 is the waveform of read pulse 8 (RD)%1Ii2FigureP
shows the waveform of the write pulse x 8 (WR), and FIG. 2q shows the waveform of the erase pulse 8(n).

For example, 112m is taken from the left end to the other end along the time axis. ・t1~ri indicate the respective time points. ・First, at time t1, the voltage VDD changes from ■V to 115Vl (2nd WJm)
. At this time, the voltage at point P is ov color 11V k:t
'Caseul. Non-operation 414 #8 (NOP) changes from rOJ to r ri'k (#I2 figure c), therefore the voltage V
(L) changes by -6.5VK from ov (Fig. 2D), and transistors 9 and Qw are turned on. Since the negative phase non-operation signal 8 (N'OP) changes from "1" to "0",
Both write and erase pulses 8 (WR) and 8 (ER) are not obtained and are in the "o" state.
Therefore, the F tuners Qs and Qs are turned on.

For this reason, the source 8 and sub-strata of memory M) 8B
The voltage of becomes ov, and the read pulse m (RD) (second @B) is obtained. Therefore, the gate G and the drain νD are both at -5 V during that period [reading is performed,
The data read from the main terminal νM is supplied to the R8 type interpuff four-circuit circuit Ql and is latched, and the data is sent to the data terminal (8).
It is output as signal 8 (8) (Iris 211IB).

At time point 2, the voltage VDD changes from 11sv to -sov (Figure 2). At this time, the voltage at point P changes from -13V to -2@Ic. The non-operation signal 51 (NOI)) is “1”.
' to '0' (Figure 2C). Therefore, the voltage V (L) remains -&5v (Fig. 2D), and
transistor. 1. Qw is turned off. The reverse-phase inoperation signal 1ITo changes by 1jk from rOJ.Then, the signal 8(8) at the pre-terminal (8) passes through 711-ting and then disappears at one time point tsK. □ becomes the selection pulse rOJ.

Therefore, the write pulse xs (Wi) is not obtained and the erase pulse 8 (liB) (211G) is obtained, so the transistor Q4 is off. 8 and Qs are turned on, and the reverse phase erase pulse 8 (star n
)+-□rOJ, so it is a transistor. a, Q**
It becomes toy.

Therefore, the source 8 and the r-rain D of the memory M are both open, and the voltage of the nap plate 8B is .

-, tOV, and the voltage of G) is the erase pulse 8
During the period (■) oV, erasure is performed.

At time 14, the voltage VDD changes from 130V to 13V (2nd WA person). The voltage at this junction point P changes from -26V to -113Vg. Non-operation signal 5 (NOP) is rOJ
rIJK changes from 6 (2wJO to 111). es.

Therefore, the voltage V (L) remains at -6.5v (second
(D), and transistors Qt and Qw are turned on. Since the anti-phase non-operation signal S (NOJ') changes from "1" to "0", one write and erase pulse s (w'&) is required.

8()iiR) cannot be obtained and is rOJ, the transistors Qa, Qs, and Qs are turned off, and the anti-phase erase pulse g(ga) becomes "1", so the transistor Qs
%Qs is turned on. Therefore, the signal 5 at the output terminal (8)
(8) is the readout output at time t1.

Voltage VDD at point 1 glue car xsv color sov
K Change, do (Figure 2 person). At this time, the voltage at point P changes from -1 sV to -26V. Non-operation signal 8 (NO
P) changes from "1j" to "O" (Figure 2C). Therefore, the voltage V (L) remains at -6, SV (second
aD)% Also, transistors Qy and Qm are turned off. The negative phase non-operation signal 8 (NOP) changes from "0" to "1". And the signal 8 (8) of the data terminal (8) is
After passing through the tainder, one write selection pulse rlJ is generated at one time point t1. Therefore, erase pulse 8 (ER) is not obtained and write pulse 8 (WR) (211F
) is obtained, transistor Q4 is turned on, transistors Qs and Qs are turned off, and the reverse phase erase pulse 8CI is obtained.
B) becomes "1", so transistor Q1. Q is turned on.

For this reason, the source of the message M and the substratum) 8B
The voltage of OV is ov, its dollar in D is open, and the voltage of its G is OV during the writing ANA8 (WR) period -20
VK, writing is performed.

Voltage VDD at time t1 Car 30V Color 1sV
Convert to kffi (Figure 2). At this time, the voltage at point P changes from -26v to -1sv. Non-operation signal 8 (NOP
) changes from rOJ to rlJK (Figure 2C). Therefore, the voltage V(L) is -6,5VF)11-e&')(
12D), and transistor Q? , the Q tightening is turned on. Since the reverse-phase non-operation signal 8 (NO!') changes from "1" to rOJ, the write and erase cloud pulses 8 (WR), 8 (
IR) is not obtained and is rOJ, but transistors Q4, Qi, and Q6 are turned off, and a negative phase erase pulse 8 (
Since ER) becomes "1", transistors Qa and Qs are turned on. Therefore, the signal 8 (8) at the output terminal (8)
This is the readout output at time t1.

At one point in time t$, the voltage VDD changes from 115V to Ov (No. 1). At this time, the voltage at point P is from -13V to GV
) cm(1, the voltage V(L) changes from -6, sV to oVK. Therefore, the voltage in each region of the memory M is open, and the memory M is in an inactive state and stores the written data. are doing.

At time t-, the voltage VDD changes from Ov to -15V (
Figure 2 (person). The voltage at point P is 18 VK from OV
Change. The non-11' signal 8 (NOP) changes by 1 from rOJ (FIG. 2C). Because of the voltage V(
L)) changes from tov to -6.5v (Figure 2D).

Also, transistor Q? The %Q theory is on. Since the negative phase non-operation signal g (NOP) i changes from "1" to "0", the write and erase pulses 5 (vra), 8 (NIL
) cannot be obtained and are "0", so the transistor Q4
．． QI and Q6 are turned off and the %-reverse phase erase pulse 8 (I
Since B) becomes rlJ, F transistors Q. and Q- are turned on.

For this reason, the source S and substratum of memory M) 8B
The voltage becomes ov, and the successive pulses 8 (RD) (Fig. 2 E) are obtained.
During that period, the voltage becomes -5V and the wire is cut out, and the data read from the memory M is supplied to the R8 type 7 lip 7 stomach tube circuit ao and latched, and the data terminal (8) k
8 (8) (Figure 2B).

Next, another example of the present invention will be described with reference to FIG. 3, in which parts corresponding to those in FIG. 1 are designated by the same reference numerals and redundant explanation will be omitted. FIG. 3 shows a case where the data terminal (8) is used exclusively as an output terminal.

In FIG. 3, the following circuit elements are shown.

Zener diode: D1 ~ D $ Resistor: Rt ~ Rs , By , Rs Capacitor: , C1, C snow MO8 field effect F la transistor channel type): Q1
~Qu4 N/(-1: IVs ~IV+s, I
Vs-IVu AND circuit 2 A2 to A4 NAND circuit: NA4 NOR circuit: NR4, ER violation □ Table 6 ゛(9) Detects that the line voltage VDD changes from 11sv to 130VK and generates a high voltage pulse at its leading edge. This is a pulse generation circuit that generates 8 (P). That is, inverter IVs
The output terminal of is grounded through resistor R8, and is also grounded through resistor R7-→capacitor C2. and,
The midpoint of the connection between the resistor 1f and the capacitor Cs is connected to one input end of a seven NAND circuit N4 via an inverter f's. An inverter IVs is connected to the other input of the NAND circuit NA4. The output terminal of the NAND circuit N4 is connected to the input terminal of the inverter IVe. Then, the above-mentioned pulse 8 (P) is obtained from the inverter IVs.

The output latch circuit (7) has an Ra type 7-lip 7-4 circuit (1o') with a T terminal, and its configuration will be explained below. Pulse 8 (P) from the pulse generating circuit (9) is sent to the AND circuit 2 through the T terminal. Commonly supplied to system 3. The respective outputs from the Q and Q output terminals of the NOR circuits NR4 and NRI are also supplied to the AND circuits A2 and M3, respectively, and also to the other NOR circuit NRI.

Supplied to NR4. The outputs of AND circuits Ax and M3 are supplied to NOR circuits N'Ba and NRs, respectively. Pulse 8 (RD) from the pulse generation circuit (4) is sent to the NOR circuit NR4 through the set (8) input terminal and through the AND circuit %A-.
IC is supplied. Transistor Q10. The output from the connection midpoint of Qll is reset) (R) is directly supplied to the NOR circuit NRs via the input terminal, and
The signal is supplied to the AND circuit 4 via.

Also, each a! of NOR circuit NR4, NRI! The forces are Q and Q, respectively.
Supplied to the NAND circuit Nλ2′τPJAs via the output terminal i
be done. The output end of the NOR circuit NRs is connected to the data terminal (8) via the inverter IVu.

In the circuit shown in Fig. 3, the voltage VDD is from 115V to 15V.
When OV < changes, the leading edge of [Pulse generation DO path (9
)'C-Hals s (p) is generated, and this pulse s
At (p), the 7-lipflip circuit (10') of the output latch circuit (7) is inverted, and the inverted data of the sheep is written into the memory Mk. The rest of the configuration and operation are the same as those in Figure 1, so further explanation will be omitted.

Next, still another embodiment of the present invention will be described with reference to FIG. 4, but parts corresponding to those in FIGS. 1 and 3 will be denoted by the same reference numerals, and the description thereof will be omitted.

In the circuit of FIG. 4, the data terminal (8) is used exclusively for output, and the pulse generating circuit (9) in FIG. 3 is omitted to further simplify the configuration.

In Figure 4, the following circuit elements are shown.

Zener diode = D1 ~ D Hatake resistor = R5 ~ 6 , :, ' : 11 ; Capacitor : 01 MO8 field effect transistor (P channel type) : :・
91~-Qu, Invar 1: IV1~IVs,
TV10-IVu AND circuit: MU4 NAND circuit: NAI-NMU3 NOR circuit: NR4, Ni-coupled pulse generation circuit (4) differs from the circuits in FIGS. 1 and 3 in the following points. The connection midpoint of the diode Dy%Ds is connected to the connection midpoint IC of the resistors Ri and Rs through a resistor R6. Then, the connection midpoint of the resistors 4 to R. is grounded through the drain and source of the transistor Qn. The output terminal of the inverter IVs is the transistor Q.
connected to the gate of u.

The output latch circuit (7) is an Rg type 7-lip 7-p circuit α
It has 0. That is, the read pulse 8 (RD) is supplied to the NOR circuit NR4 via the set (8) terminal and further via the AND circuit. Outputs from the connection midpoints of transistors Q and Qu are directly supplied to AND circuit M4 via NOR circuits N, Ri, lc, and inverter IV. The output of NOR circuit NR4 and Nil is the other side's NOR circuit N.
It is supplied to RI and NR4, respectively. The output from the NOR circuit NRa is supplied to the NAND circuit NAi via the Q output terminal, and the output from the NOR circuit NRs is supplied to the NAND circuit NAx via the Q output terminal. The Q output terminal is connected to the output terminal (8) via the inverter IVu.

In the circuit shown in Figure 4, the voltage VDD ranges from -15V to -5OW.
When the voltage VDD changes from 15oV to 115VVc, the pulse generation circuit (4) generates a pulse at the trailing edge when the voltage VDD changes from 15oV to 115VVc, and this pulse causes the contents of the memory M to be written. Make sure to read it properly. Other configurations and operations are shown in Figure 1.

Since this is the same as in FIG. 3, further explanation will be omitted.

According to the present invention described above, the number of terminal bins can be reduced to three, thereby making it possible to obtain a control circuit for a non-volatile memory suitable for IC implementation.

Note that when applying the present invention to a 2-stroke memory, 1
Although bits are used, when applying to the last channel message, multiple bits may be used.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing a tie-setting chart, and FIG. 3 and 41!1 are circuit diagrams showing other embodiments of the present invention.゛ru. (Re is the power supply terminal% (2) is the voltage level horizontal circuit, (3)
is a constant voltage power supply circuit, (4) is a pulse generation circuit, (5)
, (6) is a write/erase signal generation circuit, (6) is a high voltage generation circuit (gate circuit) i7) is an output latch circuit, and (8) is a data terminal.

Claims (1)

[Claims] 1. A non-volatile make control circuit, characterized in that DC voltages of different values are supplied to power supply terminals to switch the write, erase and read states of a non-volatile memory.