JPS5832174A - Wiring tester - Google Patents
Wiring testerInfo
- Publication number
- JPS5832174A JPS5832174A JP56129453A JP12945381A JPS5832174A JP S5832174 A JPS5832174 A JP S5832174A JP 56129453 A JP56129453 A JP 56129453A JP 12945381 A JP12945381 A JP 12945381A JP S5832174 A JPS5832174 A JP S5832174A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- wiring
- short
- short circuit
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
Abstract
Description
【発明の詳細な説明】
本発明は配線試験器に関し、特に配線状tttat識別
する項目ガえは短絡、半短絡、断線或は正常配線の可否
t1台の配線試験器で識別する−のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring tester, and in particular, it is possible to identify faults in the wiring by using a single wiring tester to determine whether there is a short circuit, half-short circuit, disconnection, or normal wiring.
従来、配線状、at識別する方法として回路試験器等に
より予め配線状at予測し配線状l11t−識別しよう
とする項目、すなわ、ち短絡、半短絡。Conventionally, as a method for identifying the wiring condition, the wiring condition is predicted in advance using a circuit tester or the like, and the wiring condition is to be identified, such as a short circuit or a semi-short circuit.
断線等、各項目毎にその項目に応じた試験器を必要とし
試験項目毎に試験器を選足し、該試験器の試験方法、試
験手順に従って試験するための試験の準備、操作に時間
を要し能率的でなかった。Each item requires a tester suitable for each item, such as wire breakage, etc., and it takes time to select a tester for each test item, and to prepare and operate the test in accordance with the test method and procedure of the tester. It wasn't efficient.
本発明は従来のか\る欠点をなくすため一台の試験器で
配線状態すなわち短絡、手短絡、断線及び正常配線の可
否をタイミングにより順次識別するために試験方法試験
手順の各易な配線試験器を提供するものである。すなわ
ち、本発明は断線、半短絡l:識別するための@i、第
1の設定器と第11第1の比較器と短絡を識別するため
の短絡検出回路とよりなる識別回路、前記断線、短絡中
短絡状態の識別結果にもとづ自正常配線、短絡、半短絡
、断線を識別するためのデーーダ、さらに被試験配線路
を該繊別回路ヘタイミングにより順次切換えるためのタ
イさング回路及び切換回路よりなり、タイミングにより
被試験配線路を順次識別回路の短絡半短絡、断線の各入
力端子に切換え配線状態を識別すること1−*徴とする
ものである。In order to eliminate the drawbacks of the conventional tester, the present invention provides a wiring tester with a simple test method and test procedure, in order to sequentially identify the wiring status, that is, short circuit, manual short circuit, disconnection, and whether normal wiring is possible or not, using a single tester. It provides: That is, the present invention provides an identification circuit including a first setter, an eleventh first comparator, and a short-circuit detection circuit for identifying a short circuit; A datar for identifying self-normal wiring, short circuit, half-short circuit, and disconnection based on the identification result of the short-circuit condition, and a tying circuit for sequentially switching the wiring path under test to the sorting circuit according to the timing. It consists of a switching circuit, and the wiring path to be tested is sequentially switched to each input terminal of a short circuit, semi-short circuit, or disconnection of the identification circuit according to the timing to identify the wiring state.
次に本発明の実施1IIllt図面をm−て説明する。Next, the embodiment 1 of the present invention will be explained with reference to the drawings.
811図は本発明の実施列回路構成図でToり被試験配
線路tが切換回路りと結線され、さらに切換回路りから
萬I、第2の各比較器J、−並びに短絡検出回路jへ結
線されている。一方第1、第2の各比較器J及びダは断
線か否かを識別するための基準[を与える第1の設定器
lと亭短絡用基準ll1t与える第1の設定器1と夫々
結線されている。又被試験配線路を前記比較器J、−及
び短絡検出回路5へ順次切換るためタイζフグ回路lと
切換回路りが結線され被試験配線路tの配線状llをタ
イミングにより順次識別で救る様構成されている。:尚
第1図のスイッチ8は多数の被試験配線路tの夫々に応
じて選択するスイッチである。Figure 811 is a circuit configuration diagram of an implementation column of the present invention, in which the wiring path t to be tested is connected to the switching circuit, and further from the switching circuit to the cassette I, the second comparators J, -, and the short circuit detection circuit j. wired. On the other hand, the first and second comparators J and D are respectively connected to a first setting device l which provides a reference for determining whether or not there is a disconnection, and a first setting device 1 which provides a reference for a short circuit. ing. In addition, in order to sequentially switch the wiring path under test to the comparators J and - and the short-circuit detection circuit 5, the tie ζ puffer circuit l and the switching circuit are connected, and the wiring pattern ll of the wiring path t to be tested is identified and saved in sequence according to the timing. It is configured as follows. Note that the switch 8 in FIG. 1 is a switch that is selected in accordance with each of a large number of wiring paths t to be tested.
又、短絡検出回路Sの詳細について@X図を用−てさら
に説gAt加えると、
第2図に於いてjaは信号入力端子、jbは接地端子、
rl、r!* ram r4* rl−rl1 Fi低
抵抗SCけダイオード、jhはノット回路、DiIfi
ダイオード、SCRkiサイリスタ、Trはトランジス
タ、 jd、je、jf、3g Fi回路途中の夫々該
当端子でToる。今、負荷(本発明に於いては被試験配
線路)Lが短絡している場合、入力端子jaK入力信号
が入6ov(Lowレベル)に ・なると、ダイオード
SCがオンし、14子5dがLOW レベルとなり端
子jeがHI GHレベルになろうとし、トランジスタ
Trがオンするため抵抗r、 K大きな電流が流れ抵
抗r、の両端電圧により抵抗r、 t−通してサイリ
スタ8CRt−オンさせる。In addition, if we further explain the details of the short circuit detection circuit S using diagram @X, in Figure 2, ja is the signal input terminal, jb is the ground terminal,
rl, r! * ram r4 * rl-rl1 Fi low resistance SC diode, jh is not circuit, DiIfi
The diode, SCRki thyristor, and Tr are transistors, jd, je, jf, and 3g. Each terminal is connected to the corresponding terminal in the middle of the Fi circuit. Now, when the load (the wiring path under test in the present invention) L is short-circuited, when the input terminal jaK input signal becomes 6ov (Low level), the diode SC turns on and the 14th element 5d becomes LOW. The terminal je is about to go to the HIGH level, and the transistor Tr is turned on, so a large current flows through the resistors r and K, and the voltage across the resistors r and t turns on the thyristor 8CRt through the resistors r and t.
このため端子jeはLOW レベルにおさえられトラ
ンジスタTrはオフし端子jg #1)(IGHレベル
になる。又、正常な負荷が端子jgに接続されている場
合はトランジスタTrKFiサイリスク8CRをオンさ
せるだけの大台な電lLは流れず入力信号が入っている
間トランジスタTrはオンの状atsm続し、端子sg
はLOW レベル状mt−維持すう。Therefore, the terminal je is suppressed to LOW level, and the transistor Tr is turned off, and the terminal jg #1) becomes the IGH level.Also, if a normal load is connected to the terminal jg, the transistor TrKFi is only turned on. The transistor Tr remains on while the input signal is input without a large current flowing, and the terminal sg
is maintained at a LOW level.
すなわち1人力信号が入ってから短時間経過し几後端子
jgの状態が正常負荷時はLOW レベル短絡時はHI
GHレベルとなり短絡検出を行うことができる。今、被
試験配線路デtタイミング回路Sからの指示により切換
回路7の中のスイッチを14子8W/に切換え図示の通
り短絡検出回路!へ接続し短絡検出を行う。この場合被
試験配線路9が短絡していればデコーダ6からの指示に
よりタイミング回路gは切換スイッチクヘ次のステップ
へ進める事を中止さす指示を出すと共に配線が短絡して
いることを出力する。In other words, after a short period of time has passed since the input of the human power signal, the state of terminal jg is LOW when the load is normal, and HI when there is a short circuit.
It becomes GH level and short circuit detection can be performed. Now, according to the instruction from the wiring path det timing circuit S to be tested, the switch in the switching circuit 7 is switched to 14-pin 8W/short circuit detection circuit as shown in the figure. Connect to to detect short circuit. In this case, if the wiring path 9 to be tested is short-circuited, the timing circuit g in response to an instruction from the decoder 6 issues an instruction to the changeover switch to stop proceeding to the next step, and also outputs that the wiring path is short-circuited.
一方短絡でなければタイミング回路Sのタイミングによ
り切換回路りのスイッチSWを端子8WJ に切換える
べく指示し鉦線路を半短絡状態識別用の比較器参に接続
し設定器コに設定されている咳と比較し比較の結果、半
短絡状態であればデコーダ6より半短絡であることを出
力する。又半短絡でなければ前記同様タイミング回路l
のタイミングにより断縁識別用の比較器3に接続し設定
器lと比較され、比較の結果。On the other hand, if there is no short circuit, the timing circuit S instructs the switch SW of the switching circuit to switch to terminal 8WJ, connects the gong line to the comparator for identifying the half-short circuit state, and connects the gong line to the comparator reference for identifying the half-short circuit state. If the result of the comparison is a half-short circuit, the decoder 6 outputs that it is a half-short circuit. Also, if there is no half-short circuit, the same timing circuit as above.
At the timing of , the signal is connected to the comparator 3 for disconnection identification and compared with the setting device 1, and the comparison result is compared with the setting device 1.
断線状態であればデコ、−ダ6より断、蘇であうことを
出力す、る、断線状態でなければタイミング回Nr&の
タイミングによりデコーダ6の人力状態の論理により正
常配線と識別されデコーダ6より正常配線であることが
出力される。If the wire is disconnected, the decoder 6 outputs a message indicating that it is disconnected. If the wire is not disconnected, it is identified as normal wiring by the logic of the manual state of the decoder 6 at the timing of timing Nr&, and the decoder 6 outputs a message indicating that it is normal. It is output that it is a wiring.
以上の説明から明らかな−に本発明に於いては配聴試験
項目毎、即ち短絡、半短絡、断線、正常配線か否かt−
識別する場合、タイミングにより被試験配線路を順次、
前記各識別回路へ切換えるため、試験項目毎に試験器を
必要とせず容易にかつ迅速に配線状態を識別できる効果
がある。It is clear from the above explanation that in the present invention, each listening test item is checked, i.e., short circuit, half short circuit, disconnection, normal wiring or not.
When identifying, the wiring paths under test are sequentially identified depending on the timing.
Since switching to each of the identification circuits described above is performed, there is an effect that the wiring state can be easily and quickly identified without requiring a tester for each test item.
Ii1図は本発明の実施列回路構成図、第コ図Ifi嬉
/図における短絡検出回路の詳細図を示す。
図でI及び2は設定器、J及びりは比較器。
!fは短絡検出回路、6はデコーダ、?Vi切換回路、
gはタイミング回路、9ilt被試験配線路をそれぞれ
示す。
特許出願人 株式会社日本製鋼所
代理人 曽我道照
第V図Fig. II1 shows a detailed diagram of the short circuit detection circuit in Fig. 1, which is a circuit diagram for implementing the present invention. In the figure, I and 2 are setters, and J and 2 are comparators. ! f is a short circuit detection circuit, 6 is a decoder, ? Vi switching circuit,
g indicates a timing circuit and 9ilt indicates a wiring path under test, respectively. Patent applicant: Japan Steel Works Co., Ltd. Agent: Dosho Soga Figure V
Claims (1)
半短絡を識別するための第1.第1の設定器と#E/、
IIJの比較器と、短絡を識別す%まための短絡検出回
路とよりなる識別回路。 前記、断線、蜆絡、半短絡状態の識別結果にもとず龜正
當配線短絡、牛短絡、断線を識別する九めのデコーダ、
さらに被試験配線路を該識別a絡へタイミングにより順
次切換えるためのタイ建ング回路、及び切換回路よりな
り、タイミングにより被試験配線路t−順次、識別回路
の短絡、牛短絡、断線の各入力端子に切換え配線状態を
識別することt特徴とする配線試験器。[Claims] In a wiring tester for identifying wiring conditions, disconnection,
First, to identify half-short circuits. the first setting device and #E/,
An identification circuit consisting of a IIJ comparator and a short circuit detection circuit for identifying short circuits. a ninth decoder that identifies a short circuit, a short circuit, and a disconnection based on the identification results of the disconnection, short circuit, and half-short circuit;
Furthermore, it consists of a tie-setting circuit and a switching circuit for sequentially switching the wiring path under test to the identification a circuit according to the timing, and inputs for short circuit, short circuit, and disconnection of the identification circuit to sequentially switch the wiring path under test to the identification circuit t according to the timing. A wiring tester characterized by switching to a terminal and identifying the wiring state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56129453A JPS5832174A (en) | 1981-08-20 | 1981-08-20 | Wiring tester |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56129453A JPS5832174A (en) | 1981-08-20 | 1981-08-20 | Wiring tester |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5832174A true JPS5832174A (en) | 1983-02-25 |
Family
ID=15009852
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56129453A Pending JPS5832174A (en) | 1981-08-20 | 1981-08-20 | Wiring tester |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5832174A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0715990A3 (en) * | 1994-12-06 | 1996-08-14 | Hella Kg Hueck & Co | Switching arrangement for controlling and checking electrical loads in motor vehicles |
-
1981
- 1981-08-20 JP JP56129453A patent/JPS5832174A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0715990A3 (en) * | 1994-12-06 | 1996-08-14 | Hella Kg Hueck & Co | Switching arrangement for controlling and checking electrical loads in motor vehicles |
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