JPS5831523A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5831523A
JPS5831523A JP12953481A JP12953481A JPS5831523A JP S5831523 A JPS5831523 A JP S5831523A JP 12953481 A JP12953481 A JP 12953481A JP 12953481 A JP12953481 A JP 12953481A JP S5831523 A JPS5831523 A JP S5831523A
Authority
JP
Japan
Prior art keywords
film
psg
etching
psg film
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12953481A
Other languages
Japanese (ja)
Inventor
Kazuya Nagase
永瀬 一哉
Takaaki Momose
百瀬 孝昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12953481A priority Critical patent/JPS5831523A/en
Publication of JPS5831523A publication Critical patent/JPS5831523A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Abstract

PURPOSE:To obtain an electrode window having no difference in level and suitable for electrode wiring by a method wherein taper etching is also applied to a block film in forming the electrode window at a phosphoric silicic acid glass film (PSG film) and the first resist film is removed by a sulfuric acid peroxide solution as a promotion measure. CONSTITUTION:A negative type resist film 6 is applied on the upper surface of a PSG film 5 on an Si3N4 film 4 coated through an SiO2 film 8 for patterning and the PSG film 5 is etched by a fluoric acid group etching solution. The Si3N4 film is left as no etching is done and the PSG film becomes a taper-shaped window side by applying side etching to the PSG film. After applying exfoliation treatment to the resist film 6 by a sulfuric acid peroxide solution, the PSG film 5 is heated at about 1,000 deg.C under inert gas atmosphere and the surface of the PSG film 5 is melted. The resist film 7 is again applied and after coating the PSG film 5 by patterning, isotropic dry etching is done by carbon tetrafluoride (CF4) gas and the exposed Si3N4 film 4 is formed to be an electrode window providing a taper-shaped internal side.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関し、特に不純物拡散
阻止膜(ブロック膜)を設けた憐けい酸ガラス膜(PS
G@)に電極窓を形成する製造方法の敗勢に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a silicic acid glass film (PS) provided with an impurity diffusion prevention film (block film).
Regarding the failure of the manufacturing method for forming electrode windows in G@).

集積回路(IC)などの半導体装置は表面状縣に影響さ
れやすいため、表面をPSG膜で被覆し、外部からの水
分やナトリウムイオンの侵入を防止する方策がとられて
おり、殆んどの半導体素子表面はPSG膜をパツシペー
V=!Iン膜として保護されているといっても過言では
ない。そのため、ICではPSG膜を被着した後、電極
窓を開けて電極配線が表されるが、P S G 111
o1!厚tf l [μm1以上と厚く、エツチングし
て窓あけしただけでは窓側面の凹凸や段差のため、その
上に形成する電極配線が断線する心配がある。そのため
、約1000[tl]Q高温度に加熱してPSG膜表面
を溶融し、窓側面が平滑となるようなメルト処理が行わ
れる。
Semiconductor devices such as integrated circuits (ICs) are easily affected by surface particles, so measures are taken to coat the surface with a PSG film to prevent moisture and sodium ions from entering from the outside, and most semiconductor devices The surface of the element is covered with a PSG film. It is no exaggeration to say that it is protected as an insulating film. Therefore, in an IC, after a PSG film is deposited, an electrode window is opened to expose the electrode wiring, but PSG 111
o1! Thickness tf l [[mu]m or more is thick, and if the window is simply etched and opened, there is a risk that the electrode wiring formed thereon will be disconnected due to irregularities and steps on the side surface of the window. Therefore, a melting process is performed to melt the PSG film surface by heating to a high temperature of about 1000 [tl]Q and to make the window side surface smooth.

しかしながら、PSG膜は燐を多く含んでいるから、こ
のような高温に加熱すれば、燐が電極窓内に拡1する。
However, since the PSG film contains a large amount of phosphorus, when heated to such a high temperature, phosphorus will spread into the electrode window.

もし電極窓内の半導体領域がN型領域であれば、燐はN
型不純物であるから問題はないが、P型領埴であるとこ
こにPN接合を生じさせることになり、電極接続あるい
は半導体素子特性に悪影響を及ぼす、したがって、PS
GIIを被着する前に窒化シリコン(5iBN4 ) 
IIからなるブロック膜を形成する製造方法が原曲よυ
′用いられており、例えば0−MO8型工Cではpチャ
ネル半導体素子のp5ソース領域、ドレイン11 域カ
形成されているため全体にブロック膜を設けて電fil
l轍を形成している。
If the semiconductor region within the electrode window is an N-type region, phosphorus
There is no problem because it is a P-type impurity, but if it is a P-type impurity, a PN junction will occur here, which will have an adverse effect on the electrode connection or semiconductor device characteristics.
Silicon nitride (5iBN4) before depositing GII
The manufacturing method for forming a block film consisting of II is the original song.
For example, in the 0-MO8 type C, the p5 source region and drain 11 region of the p-channel semiconductor element are formed, so a blocking film is provided over the entire area to prevent electric current.
It forms a rut.

従来このようなブロック膜を設は九PSG膜の電極依形
成方法を説明すると、第1図ないし第8図がその工程順
断面図である。例えばN5半導体基板l上のPg領域2
に11E極窓を窓あけする場合、第1図に示すように酸
化シリコン(Sin、 )!lIBを介して被着した5
iaN4膜4およびその上に形成したP13G膜6の表
面にしシスト膜6をパターンユングし、弗酸系のエツチ
ング溶液でエツチングする。そうすると、露出したPS
GSbO2エツチングされて、サイドエッチが進行しテ
ーパー形状の側面の窓がえられる0次いで、第2図に示
すように、レジスト116を溶解除去し死後、不活性ガ
ス雰囲気中で約1000(:t3]に加熱して、PSG
膜60表面をメルトする。この際、半導体基板lオヨU
 P mtll域2 ハ5ins 118 (!: 5
isN4114 トチ被覆されているので、PSGII
6から燐が拡散されることがない0次いで、第8図に示
すようにトリフロロ゛メタン(CHF5 )ガスを用い
て表面を、垂直にエツチングする異方性エツチングを行
ない、電極窓上の露肝したSi8N4膜4と5iOB 
$IIBとをエツチングして、P型領域2を露出させ電
!iii慾を完成する。
To explain a method for forming a PSG film depending on electrodes, in which such a block film has been conventionally formed, FIGS. 1 to 8 are cross-sectional views in the order of steps. For example, Pg region 2 on N5 semiconductor substrate l
When opening the 11E electrode window, as shown in Figure 1, silicon oxide (Sin, )! 5 deposited via lIB
A cyst film 6 is patterned on the surfaces of the iaN4 film 4 and the P13G film 6 formed thereon, and etched with a hydrofluoric acid-based etching solution. Then, the exposed PS
GSbO2 is etched, side etching progresses, and a tapered side window is obtained.Next, as shown in FIG. 2, the resist 116 is dissolved and removed. Heat to PSG
The surface of the membrane 60 is melted. At this time, the semiconductor substrate
P mtll area 2 5ins 118 (!: 5
isN4114 Since it is covered with horse chestnut, PSGII
Then, as shown in Fig. 8, anisotropic etching is performed to vertically etch the surface using trifluoromethane (CHF5) gas to remove the exposed liver on the electrode window. Si8N4 film 4 and 5iOB
$IIB is etched to expose the P-type region 2, and then the P-type region 2 is etched. Complete iii.

このようにして、従来よりPSG#にテーバ−形状の電
極窓を形成しておシ、最初のウェットエツチングによっ
てPSGIIをテーパー形状とするものの、2度目のエ
ツチングはドライエツチングによって異方性エツチング
を行なうため精度良く形成されるが、側面の段差形状は
解消されない。
In this way, a tapered electrode window is conventionally formed in PSG#, and although the first wet etching gives PSGII a tapered shape, the second etching is anisotropic etching by dry etching. Therefore, it is formed with high precision, but the step shape on the side surface is not eliminated.

しかも、IC表面は多数の電極窓を同時に窺あけするた
め、エツチングその池のバラツキから少しPSG膜が窓
面に残存することもあり、その場合にはドライエツチン
グによってPSG膜も除去されて、段差は一層大きくな
る。そうすれば、その上面に形成される電極配線は断線
の心配が生じ、又形成時に断線していなくてもこの部分
での電極配線接続が不充分で、接触抵抗が大きくなるか
ら長期間使用中に発熱溶融して断線に至ることにな9、
信頼性1好ましいことではない。
Moreover, since many electrode windows on the IC surface are simultaneously exposed, a small amount of PSG film may remain on the window surface due to variations in the etching process. becomes even larger. If this happens, there is a risk that the electrode wiring formed on the top surface will break, and even if it is not broken at the time of formation, the electrode wiring connection at this part will be insufficient and the contact resistance will increase, so it will not be used for a long time. This may cause the wire to melt due to heat generation and lead to wire breakage9.
Reliability 1: Not desirable.

本発明はこのような問題点を解決することを目的として
、その特徴はPSG膜にテーパー形状の電極窓を形成し
た後、レジスト膜を過酸化−硫酸溶液で溶解除去し、次
いでPSG膜をメルトして、再びPSG膜上にレジスト
膜パターンを形成し、次いでブロック膜を等方性エツチ
ングして電極窓をあける工程を含む製造方法であり、以
下図面を参照して詳細に説明する。
The present invention aims to solve these problems, and its characteristics are that after forming a tapered electrode window on a PSG film, the resist film is dissolved and removed with a peroxide-sulfuric acid solution, and then the PSG film is melted. This manufacturing method includes the steps of forming a resist film pattern on the PSG film again, and then isotropically etching the block film to open an electrode window, and will be described in detail below with reference to the drawings.

第4図ないし第7図は本発明にか−る製造方法の工程順
図で、前記した従来例と同じく、N型半導体基板l上の
P5領域2に電極室を窓あけする実施例で説明する。第
4図に示すように、 Sing膜8を介して被着した5
iaN41114(膜厚数100[入])、その上に同
じく気相成長させ九P13G膜5(IIII[μm91
1)の上面にネガ型しシスト膜6を塗布しパターンユン
グして、電Wi意以外の表面を被覆し電極室上の露出し
たPSG膜5を弗酸系エツチング溶液でエツチングする
。5isN4膜は弗酸系エツチング溶液ではエツチング
されないから残存し、PSG膜はサイドエッチされてテ
ーパー形状の窓側面となる。次いで第5図に示すように
レジスト膜6を過酸化−硫酸液で剥離処理した後、不活
性ガス雰囲気中で約1000[℃]に加熱してPSGS
bO2面をメルトする。このPSG膜のメルトは前記し
たようにエツチング面の凹凸をなだらかにし、更にテー
パー形状の勾配もゆるやかにするものである。又過酸化
−硫酸液(Per Oxi、mon。
Figures 4 to 7 are step-by-step diagrams of the manufacturing method according to the present invention, and will be explained using an example in which an electrode chamber is opened in the P5 region 2 on the N-type semiconductor substrate l, similar to the conventional example described above. do. As shown in FIG.
iaN41114 (thickness: 100 [μm]), on which a 9P13G film 5 (III [μm 91
1) A negative type cyst film 6 is applied to the upper surface and patterned to cover the surface other than the electrode chamber, and the exposed PSG film 5 on the electrode chamber is etched with a hydrofluoric acid etching solution. The 5isN4 film is not etched by the hydrofluoric acid etching solution, so it remains, and the PSG film is side-etched to form a tapered window side surface. Next, as shown in FIG. 5, the resist film 6 is stripped with a peroxide-sulfuric acid solution, and then heated to about 1000 [°C] in an inert gas atmosphere to form PSGS.
Melt the bO2 side. As described above, this PSG film melt smoothes the unevenness of the etched surface and also makes the slope of the tapered shape gentle. Also, peroxide-sulfuric acid solution (PerOxi, mon.

5ulfurio Aoi、d )はレジスト膜剥離す
ると共にSi、3N4aII表面を変質させて、以後の
Si8N4膜表面のエツチングを助長させる効果をもっ
ている。
5ulfurio Aoi, d) has the effect of stripping the resist film and altering the Si, 3N4aII surface to promote subsequent etching of the Si8N4 film surface.

次いで、第6図に示すように再度レジスト膜7ヲ塗布し
、パターンユングしてPSG膜5を被覆し死後、四弗化
炭素(0F4)ガスを用い九バレ〜形エツチング装置に
て等方性ドライエツチングを行ない、露出した5iBN
i膜4を図示のようにテーパー状内側面をもった電極窓
に形成する。この際5LaN4%厚が薄いため、過酸化
−硫酸液処理されないSi3N4膜の場合にはほとんど
テーパーがつかないが、過酸化−硫酸処理された513
N4膜の場合には充分なテーパー状側面が得られる0次
いで、5iOsl18を弗酸系エラチン“グ溶液でエツ
チングし、図示のようにテーパー状側面をもった電極窓
に形成する。最後にしシス)Illを溶解除去して第7
図に示す形状の電Wi鎌とする。尚、再度形成するレジ
スト膜7には解像度の高いポジ型しVストが好ましく、
又このようにレジスト膜7を被覆するのはPSG膜がC
F4ガスでエツチングされ易いからで、2回目のエツチ
ングではできるだけPSG膜を傷けることなく、電極窓
を高精度に維持する目的をもっている。又、これらのS
i3N4膜4と5ill膜8とをウェットエツチングす
るとテーパー状となるが、それでは微細な部分にエツチ
ング液が残存して、腐蝕するなどの悪影響を与えるため
ドライエツチング法によ抄テーパー形状とする以上の実
施例から判るように、本発明はブロック膜をもテーパー
エツチングすることを主な特徴とし、その助長策として
過酸化−硫酸溶液で最初のレジスト膜を除去するもので
、このようにして形成すれば段差はなくなシ、電極配線
に好適の電極窓が得られる。したがって、本発明はIC
の信頼性向上に極めて有効な方法である。
Next, as shown in FIG. 6, the resist film 7 is applied again and patterned to cover the PSG film 5. After death, it is isotropically etched using a nine-barrel type etching device using carbon tetrafluoride (0F4) gas. 5iBN exposed after dry etching
The i-film 4 is formed into an electrode window having a tapered inner surface as shown. At this time, since the 5LaN4% thickness is thin, there is almost no taper in the case of a Si3N4 film that is not treated with a peroxide-sulfuric acid solution, but with 5LaN4% that is treated with a peroxide-sulfuric acid solution,
In the case of the N4 film, a sufficient tapered side surface can be obtained.Next, the 5iOsl18 is etched with a hydrofluoric acid-based etching solution to form an electrode window with a tapered side surface as shown in the figure. 7th by dissolving and removing Ill.
An electric Wi sickle with the shape shown in the figure is used. It should be noted that the resist film 7 to be re-formed is preferably a positive type with high resolution and a V-type resist film.
Also, the reason why the resist film 7 is covered in this way is that the PSG film is C.
This is because it is easily etched by F4 gas, and the purpose of the second etching is to maintain the electrode window with high precision without damaging the PSG film as much as possible. Also, these S
Wet etching the i3N4 film 4 and the 5ill film 8 results in a tapered shape, but in this case, the etching solution remains in minute parts and causes adverse effects such as corrosion, so it is more difficult to create a tapered shape than by dry etching. As can be seen from the examples, the main feature of the present invention is to taper-etch the block film as well, and to facilitate this process, the first resist film is removed using a peroxide-sulfuric acid solution. In other words, there is no step difference, and an electrode window suitable for electrode wiring can be obtained. Therefore, the present invention
This is an extremely effective method for improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第8図は従来の製造方法の工程順断面図、
第41図ないし第7図は本発明にか\る製造方法の工程
順断面図である。 図中、lはN型半導体基板、2はP型領域、8はSin
、 [、4は5isN4I!11.51jPSG膜、6
゜7はレジスト膜を示している。 第1図 第2・4 第3゛°℃ 第 4vA 6 第7図
Figures 1 to 8 are cross-sectional views of the conventional manufacturing method in the order of steps;
FIGS. 41 to 7 are cross-sectional views in the order of steps of the manufacturing method according to the present invention. In the figure, l is an N-type semiconductor substrate, 2 is a P-type region, and 8 is a Sin
, [,4 is 5isN4I! 11.51jPSG film, 6
7 indicates a resist film. Fig. 1 Fig. 2.4 Fig. 3゛°℃ Fig. 4 vA 6 Fig. 7

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に窒化シリコン膜からなる不純物拡散阻止
膜を形成し、その上に燐けい酸ガラス族を被着して電F
jAl!をあけ、更に該燐けい酸ガラス族をメ〃トシた
後、上記不純物拡散阻止膜に電極窓をあける半導体装置
の製造方法において、燐けい酸ガラス膜にテーパー形状
の電極窓をあけた後、上面のレジス)@パターンを過酸
化−硫酸溶液で溶解除去する工程、次いで燐けい酸ガラ
ス族をメルトした後、再度該憐けい酸ガラス膜上にレジ
スト膜パターンを形成する工程、次いで不純物拡散阻止
膜を等方性エツチングして電極窓を形成する工程を含む
ことを特徴とする半導体装置の製造方法・
An impurity diffusion prevention film made of a silicon nitride film is formed on a semiconductor substrate, a phosphosilicate glass group is deposited on the film, and an electric F.
jAl! In the method for manufacturing a semiconductor device, in which a tapered electrode window is formed in the phosphosilicate glass film, in the method for manufacturing a semiconductor device, the electrode window is formed in the impurity diffusion prevention film after the phosphosilicate glass group is further removed. A step of dissolving and removing the upper resist pattern with a peroxide-sulfuric acid solution, followed by a step of melting the phosphosilicate glass group, and then forming a resist film pattern on the phosphosilicate glass film again, followed by impurity diffusion prevention. A method for manufacturing a semiconductor device, comprising the step of isotropically etching a film to form an electrode window.
JP12953481A 1981-08-18 1981-08-18 Manufacture of semiconductor device Pending JPS5831523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12953481A JPS5831523A (en) 1981-08-18 1981-08-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12953481A JPS5831523A (en) 1981-08-18 1981-08-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5831523A true JPS5831523A (en) 1983-02-24

Family

ID=15011889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12953481A Pending JPS5831523A (en) 1981-08-18 1981-08-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5831523A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824801A (en) * 1986-09-09 1989-04-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing aluminum bonding pad with PSG coating
US5490901A (en) * 1993-03-15 1996-02-13 Hyundai Electronics Industries Co., Ltd. Method for forming a contact hole in a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824801A (en) * 1986-09-09 1989-04-25 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing aluminum bonding pad with PSG coating
US5490901A (en) * 1993-03-15 1996-02-13 Hyundai Electronics Industries Co., Ltd. Method for forming a contact hole in a semiconductor device

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