JPS5830613B2 - Voice calculator with program - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable voice calculator that sequentially outputs program information stored in a memory by voice.

In conventional key-operated program calculators, whether the program has been correctly stored is checked by looking at the display or printed results.

However, this requires the programmer to look at his own manuscript and also to look at the display or print, which is time consuming and often tiring.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and it outputs the program contents stored in the memory sequentially by voice for checking, and further adjusts the reading interval of the program contents from the memory to change the sound quality. The purpose of this invention is to make it possible for the operator to adjust the time length between words in the audio output program content without any trouble.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a programmable voice calculator according to the present invention. In the figure, KU represents a key unit, and this unit includes a group of keys including various keys such as numeric, function, and program keys, as well as a start key SK and It has a reset key PCK for resetting the program counter PRC.

EC is an encoder, B1 is the first buffer register,
PRM is a program memory that stores program information, B2 is a second buffer register, DC is a decoder, CU is a central processing circuit, CC is a code converter, V
AC is an address counter, VDC is an address decoder, VROM is a read-only memory that stores digital information to be output as audio, DA is a digital-to-analog converter, LPF is a low-pass filter, D
is the driver circuit, SP is the speaker, JE is the VROM program end code detection circuit, MM is the monostable multi-byte break, Qo is the pulse generator, INC is P
RC reset circuit, Q1 to Q3 are sequential signal generation circuits S
HR is a shift register, FE is a flip-flop circuit,
JED is a judge circuit, Go-G6. G8 is an AND gate, G7 is an OR gate, SW2 is a mode changeover switch, SW is a program write mode W,
Program reading execution mode R1 has each mode terminal of normal calculation mode N and check mode CH for checking the stored contents of the program memory, SW2 has an auto mode terminal A that automatically outputs the program memory contents as voice, It has an audio output mode terminal N for manual checking.

In the above configuration, the program memory PRM contains codes corresponding to the keys, such as the Hult code (H), the memory plus code (M), the multiplication instruction code (X), the square root code (f-), and the equal code ( -) and a program end code (E) are stored.

H, X, -1M, J are stored in the program memory as shown in Figure 1.
-...When programming E, when you want to check it, set switch Sw1 to check mode CH,
key units) When you press the start key SK of KU, if switch RO■2 is in auto mode A, the
11 Hart 1;, "Times", "Equals", "M11, "1 equals"..."End 1' are output.

Also, set the switch RO■2 to normal mode N (and if you press the start key SK, first 11 hart 11 and then press it again I'times, from now on, each time you press the start key SK, '1 equals', 1M1""Haruto"'...
・Proceed as follows and output the audio one by one.

Therefore, the program can be checked at a speed that suits the operator.

Of course, even in the auto mode A, the length of time between each word can be adjusted using the volume VR.

Next, the operation will be explained.

■ When switch SW is set to program write mode W.

Set the switch Sw1 to program write mode W, and first press the program counter reset key PCK to reset the program counter PRC reset circuit INC.
This counter is stored in program memory P.
Indicate the first digit of RM.

In this way, when a key block in the key unit (Key unit) KU is pressed, for example, the Halt (H) key, the code is converted by the encoder EC and stored in the first buffer register B1. Gate G1 is turned on, and sequential signal generating circuits Q1 to Q3 are activated via OR gate G9.

Q1 to Q3 operate as shown in FIG. 2 with respect to the input signal Q+in.

Gate G due to the occurrence of Suhars Q1.

is turned on and the program counter PRC is turned on.
The contents of the first buffer B1 are placed in the digit of the program memory PRM corresponding to the + position.

Here, the first digit will contain the Hult (H) code.

In this mode, the order signal generating circuit Q2 is not concerned, and the counter PRC is shifted to the left by one digit with the pulse Q3, and the "1" position is moved to the second digit, in preparation for the next key input (the state shown in FIG. 1).

Next, when you press the multiplication instruction (X) key on the key block, the corresponding code is generated by the encoder EC,
When the signal enters the buffer B1, the gate G1 is turned on to activate the sequential signal generating circuits Q1 to Q3.

In the sequential signal generating circuit Q1, a multiplication instruction (X) code is input into the second digit of the program memory PRM whose contents in the buffer B1 are specified by the program counter PRC.

Then, in the next sequential signal generation circuit Q3, the counter PRC
shift.

Repeat this to perform normal program input.

α When set to mode R, which reads and executes a program.

Complete the program input in the program write mode W above, switch switch 8v to mode R for reading and executing the program, press the program counter reset key PCK, and reset the counter using the reset circuit INC of the program counter PRC to the initial state. return.

When the start key SK is pressed, the gate G2 is turned on and the sequence signal generating circuits Q1 to Q3 are operated.

The pulse Q inputs the contents of the first digit of the program memory PRM into the second buffer B2 via the gate G3.

Shift the program counter PRC with pulse Q3.

DC is a decoder that decodes the contents of the second buffer B2 and generates a signal that causes the central processing circuit CU to execute the desired arithmetic control, and this is only when the read execution mode R is in effect and R2→CU is executed. It is.

The first program is H (Hart), which indicates data manual operation, especially the central processing circuit CU does not operate, and therefore the processing end signal E.

It doesn't come out either. After inputting the data to the computer, press the start key SK.
When is pressed again, the sequential signal generating circuits Q1 to Q3 operate in the same way, and PRM-+B2 is performed with the pulse Q1.

Since the program run J-PRC has been shifted in the second buffer B2 by the previous pulse Q3, the second digit X (multiplication instruction) code is stored in the second buffer B2.

Therefore, the processing corresponding to the X code is carried out by the central processing circuit CU.
At the same time, the counter PRC is shifted again using pulse Q3.

After processing in the central processing circuit CU, when a processing end signal Eo is generated, the gate G is turned on to activate the sequential signal generation circuits Q1 to Q3.

The flip-flop FE is set by the start key SK and reset when the judge circuit JED detects that the content of the second buffer is an END code.

Here, flip-flop FE is in the set state.

Arithmetic processing end signal E in R mode. is applied to the gate G4, the sequential signal generating circuit Q operates through the gate G9, and the third digit of the program memory PRM is equal to (-
) enters the second buffer B2 and is processed by the central processing circuit CU.

That is, since it was processed as HX-, if X- is a square calculation, it means that the square calculation of the data input into the computer at the time of H was automatically performed.

In this way, all signals other than the H (Hart) code are the arithmetic processing end signal E of the central processing circuit CU.

The program automatically progresses based on the output.

When the END signal E reaches the second buffer B2, the flip-flop FE is reset, the gate G4 is turned off, and the processing is stopped.

■ When switch product V is set to check mode CH.

If you reset the counter PRC using the program counter reset key PCK and press the start key SK, the gate G5 will turn on and, since the counter PRC is in its initial state, the first digit of the program memory PRM will be set to H. (Hart) code into the second buffer B2.

In the subsequent sequential signal generation circuit Q2, the gate G3 is turned on.

Here, the VROM is a read-only memory that stores digital information to be outputted as audio, and has an area for each word as shown in the figure.

This VROM is accessed by address counter VAC.

The address code of address counter VAC is decoded by address decoder VDC to access a desired step.

When address counter VAC is in reset state, VROM
None of the steps are accessed.

For example, if you want to generate 11ichi+1, counter V
When the initial address of the +1 11 area of the VROM is input to AC, the fourth step of the audio data forming "I" is output from the ROM output R6.

EN in the final step of the following 11+1 areas
The address counter VAC automatically counts up until the D code arrives, and audio digital information is sequentially output from the VROM output R6.

When the END code is detected by the END code detection circuit,
Reset address counter VAC again.

During this time, the Ro output of the VROM is supplied to the speaker SP via the digital-to-analog converter DA, the low-pass filter LPF, and the driver circuit to generate 11-11.

Now set switch Sw2 to auto mode A.

When the END code is generated, the output of the END code detection circuit JE is output, which resets the address counter VAC and at the same time activates the monostable multi-bi break MM.

Generate a pulse.

This time chart is shown in FIG.

This monostable multi-bi flake MM and pulse generation circuit Q
.

The processing corresponds to a kind of delay circuit that provides a pause time for the voice when the END code is output and the next word is uttered, making it easier to hear.

The volume VR attached to the monostable multi-vibrate MM is for making the output pulse width of the monostable multi-vibrate JMM variable.

The time until the arrival of the END code is applied to the gate G6 is adjusted by the volume VR.

CC is a code converter for converting the code of the second buffer B2 into an initial address of the VROM in order to specify the area of the VROM corresponding to the code stored in the second buffer B2.

The second signal is generated by the sequential signal generating circuit Q2 through the gate G8.
A predetermined word is uttered by converting the contents of buffer B2 in code converter CC and inputting it into address counter VAC.

For example, as mentioned above, the first word "Haruto" is uttered, and the output R8 of the VROM is 11Harto 1! When the END code comes, the pulse Q is delayed.

is output, and if switch SW2 is in auto mode A, gate G6 is turned on to generate Ql again.

Then, the multiplication instruction (X) code in the second digit of the program memory PRM enters the second buffer B2, and the program address counter VAC corresponding to the be done.

Thereafter, the contents of the program memory PRM are automatically output as audio.

After that, when the END near code E of the program memory PRM arrives at the second buffer B2, the judge circuit J
ED becomes 1, the flip-flop FE is reset, the gate G6 is turned off, and the process ends.

Of course, since the pulse Q2 is generated following the sequential signal generating circuit Q1, 11 end 11 is uttered.

The above is the state of auto mode A.

If the switch Sw2 is in the normal N mode, the gate G6 is always off, so even if you press the start key SK and say 11 halt 1 and the END code comes to the output R6, the next multiplication instruction code It doesn't move to

To move to X, press the start key SK again and move to gate G5.
It is sufficient to turn on the sequential signal generating circuits Q1 to Q3 to generate signals.

That is, in the normal operation mode N of the switch Sw2, 1 of the program memory PRM is executed every time the start key SK is pressed.
This is a manual check audio output mode that outputs audio for each step.

In the audio above, the H chord is uttered as 11 hart 11F chord is 11 root + 1, but instead of this, H can be simply expressed as +1 1, F is 11 go 11, etc. Of course.

As described above, according to the present invention, since the program contents stored in the memory are sequentially outputted by voice,
There is no need to check whether the program contents are correctly stored by looking at both the original and the display or print result, and the program contents can be checked without taking much time or tiring.

In addition, in response to the output of the audio memory that stores digital information representing words, it is possible to adjust the reading interval of the next stored content read from the program memory, so the time between the words that are output as audio can be adjusted. The length can be adjusted without changing the sound quality, and program checks can be performed at a speed that suits the operator.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an audio calculator showing an embodiment of the present invention, Fig. 2 is a time chart of each pulse generated in the sequential signal generation circuit, and Fig. 3 is a time chart of each pulse of the audio output speed adjustment circuit. Show chart. In the figure, KU: key unit, K: key group, SK start key, PCK: reset key, EC: encoder, B
1: First buffer, PRM Niprogram memory, B
2: second buffer, DC: decoder, CU: central processing circuit, CC: code converter, VAC near address counter, VDC near address decoder, VROM: read-only memory that stores digital information to be output as audio DA: Digital to analog converter, LPF:
0-pass filter, D driver circuit, SP: speaker, JE: END code detection circuit, MM: monostable multi-by-break, PRC nib program counter, INC: reset circuit, Q, ~Q3: sequential signal generation circuit, SHR : Shift register, FE: Flip-flop, JED: Judge circuit, Go-G6°G8: Ant gate, G7: OR gate, SW. SW2: Mode changeover switch, W Niprogramming write mode, R Niprogramming reading execution mode, N: Normal calculation mode, CH: Check mode, A: Auto mode,
N: Manual check mode.

Claims (1)

[Scope of Claims] 1. A programmable calculator having a program memory, comprising: means for instructing reading of stored contents from the memory; and a voice memory for storing digital information representing a word corresponding to the stored contents of the memory; Address selection for selecting an address of digital information representing a predetermined word in the audio memory based on stored contents that are inserted between the program memory and the audio memory and are sequentially output from the program memory in response to the instruction means. a sound generator that outputs sound corresponding to digital information output from the sound memory; and a sound generator configured to set a reading interval of stored contents to be read from the program memory next in response to the digital output information after the sound is generated. A programmable voice calculator characterized by comprising an adjustment circuit.