JPS5830326U - Receiving machine - Google Patents
Receiving machineInfo
- Publication number
- JPS5830326U JPS5830326U JP12401881U JP12401881U JPS5830326U JP S5830326 U JPS5830326 U JP S5830326U JP 12401881 U JP12401881 U JP 12401881U JP 12401881 U JP12401881 U JP 12401881U JP S5830326 U JPS5830326 U JP S5830326U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- stored
- pulse train
- width modulated
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面はこの考案の受信機の１実施例を示し、第１図は一
部のブロック図、第２図はＰＷＭ信号の説明図、第３図
は第１図の動作説明用の波形図である。
ＳＧ・・・信号発生回路、１０・・・積分回路、１１・
・・検出回路、１２・・・ＦＥＴスイッチ素子。The drawings show one embodiment of the receiver of this invention, Fig. 1 is a partial block diagram, Fig. 2 is an explanatory diagram of a PWM signal, and Fig. 3 is a waveform diagram for explaining the operation of Fig. 1. . SG...signal generation circuit, 10...integrator circuit, 11.
...Detection circuit, 12...FET switch element.
Claims (1)
の記憶時に、パルス列信号を順次に変化させ記憶すべき
局のパルス列信号を記憶し、受信選局時に、前記記憶し
た当該局のパイレス列信号にもと匈くパルス幅変調信号
を出力する信号発生回路と、−該信号発生回路のパルス
幅変調信号をアナログ変換し同調指示信号を出力する積
分回路とを備え、前記同調指示信号により受信選局を行
なう受信機において、前記記憶時に受信信号の変動を検
出する検出回路と、該検出回路の出力により前記積分回
路の時定数を小さく切り換えるスイッチング手段とを設
けた受信機。A pulse train signal for a pulse width modulated signal for reception tuning. When storing the signal, the pulse train signal is sequentially changed and the pulse train signal of the station to be stored is stored, and when reception tuning is performed, the pulse train signal of the stored station is stored. a signal generating circuit that outputs a pulse width modulated signal in response to a signal; and an integrating circuit that converts the pulse width modulated signal of the signal generating circuit into analog and outputs a tuning instruction signal, the signal generating circuit receiving the tuning instruction signal; A receiver for selecting a channel, comprising: a detection circuit for detecting fluctuations in the received signal during storage; and switching means for switching the time constant of the integrating circuit to a smaller value based on the output of the detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12401881U JPS5830326U (en) | 1981-08-20 | 1981-08-20 | Receiving machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12401881U JPS5830326U (en) | 1981-08-20 | 1981-08-20 | Receiving machine |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5830326U true JPS5830326U (en) | 1983-02-28 |
Family
ID=29917905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12401881U Pending JPS5830326U (en) | 1981-08-20 | 1981-08-20 | Receiving machine |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5830326U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6356824U (en) * | 1986-10-02 | 1988-04-15 |
-
1981
- 1981-08-20 JP JP12401881U patent/JPS5830326U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6356824U (en) * | 1986-10-02 | 1988-04-15 |
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