JPS5830251A - Digital signal transmitting system - Google Patents

Abstract

PURPOSE:To realize a digital signal transmitting system, by making an arrangement that, when high speed digital signals are encoded into CMI codes, low speed digital signals are also transmitted by overlapping them on the high speed digital signals by applying CRV. CONSTITUTION:High speed data from an input terminal 101 are supplied to one input side of each AND gate 302 and 308, and, at the same time, inputted into one input side of AND gates 303 and 304 after they are inverted. A CRV designate signal from another terminal 301 is directly inputted into the other input side of the AND gate 303, and, at the same time, inputted into the other input side of the AND gates 302 and 304. The output of each AND gate 302, 303, and 304 is inputted into the other input side of each AND gate 305, 306, and 307, respectively. A high speed clock pulse is inputted into the other input side of each AND gate 305 and 306 from a terminal 102, and the pulse is inputted into the other input side of the AND gate 307 after it is inverted. The output of the AND gate 305 is inputted into a toggle type FF309.

Description

[Detailed description of the invention] This actual bright line high speed CM I (Coded Mark) n
The present invention relates to a digital signal transmission system in which a low-speed digital signal is superimposed on a V*rsion code and transmitted.

Conventionally, to multiplex and transmit a high-speed digital signal and a low-speed digital signal, the two signals were time-division multiplexed, converted to a code format suitable for the transmission path, and sent to the transmission path. . Figure 1 shows the block diagram of the company.
High-speed digital signals are input as data and clock pairs from high-speed data signal input terminal 101 and high-speed clock pulse input terminal 102, respectively. A low-speed digital signal is similarly input from the low-speed data signal input terminal 103 and the low-speed clock pulse input terminal 104. These high-speed data and low-speed data signal lines are once written into buffer memories 9105 and 106 using high-speed clock pulses and low-speed clock pulses, respectively. If we assume that the high speed clock frequency is fh and the low speed clock frequency is 4ft, the clock frequency fm will be significantly higher than fh+fz because it includes time-division multiplexed digital signal line frame synchronization pulses. From the multiplexed clock pulse input terminal 107, a μ clock pulse having a frequency of fm is input.

The frame pattern generation circuit 108 generates multiplexed clock pulses and frame synchronization pulses, and also supplies read pulses to one-buffer memories 105 and 106. In the multiplexing gate 109, buffer memories 105, 10
Signals read out from 6 and frame pattern generation circuit 1
08 frame synchronization pulses are combined into one signal.

The above is a synchronous multiplexing method, that is, a multiplexing method when the three clock pulses are synchronized, but when they are asynchronous, it is necessary to perform, for example, well-known stuff synchronization. The encoding circuit 110 performs multiplexing) 109
The time-division multiplexed signal is converted into a code format suitable for the transmission path 111 and sent to the transmission path 111. Various code formats have been proposed so far, but B 8 I (Bit g@qu@nce Ind@p
CM I (C
od@d Mark Inversion) code is preferable. Since the CMI code is a type of IB2B code, it has the disadvantage that the required bandwidth of the transmission path is wide.
This drawback can be overcome by using transmission technology, especially optical fiber transmission technology, which has recently made remarkable progress.

FIG. 2 shows a block diagram of the receiving section for the transmitting section in FIG.
Equalization amplification and identification reproduction are carried out at 01, and the decoding circuit 20
2 is input. The regeneration circuit 201 simultaneously regenerates multiplexed clock pulses and supplies them to the decoding circuit 202 and frame synchronization circuit 203. The decoding circuit 202 performs the reverse operation of the encoding circuit 110 to restore the original time division multiplexed signal. The frame synchronization circuit 203 detects a frame synchronization pulse from this signal, performs frame synchronization, and supplies a control pulse to the demultiplexing gate 204 at the same time. A demultiplexing gate 204 separates the time-division multiplexed signal into a high-speed digital signal and a low-speed digital signal, and writes them into buffer memories 205 and 206, respectively. The contents of backup memories 205 and 206 are stored at terminal 207.
It is read out by high-speed clock pulses and low-speed clock pulses inputted from terminals 209 and 208, respectively.
210. These clock pulses are obtained from the regeneration circuit 201, and the main multiplexed clock pulses (4L<> are added with a certain operation to the clock pulses) are PL
In some cases, it is supplied to L, etc., and in some cases, it is made by K.
It may also be supplied from another device on the receiving side. (9) If stuff synchronization is performed on the sending side, a corresponding destuffing operation is performed on the receiving side.

As explained above, in the conventional method, the bit rate of the time-division multiplexed signal is higher than the bit rate of the high-speed digital signal, so compared to the case of transmitting only the high-speed digital signal, the transmission distance etc. On the transmitting side, it is necessary to prepare a generator for multiplexed clock pulses with a frequency higher than the high-speed clock frequency for rounding that converts the speed of the signal, and on the transmitting side,
It had drawbacks such as requiring two backup memories on each receiving side.

This invention line In order to eliminate these drawbacks, CRY (Coding
A low-speed digital signal is superimposed on the low-speed digital signal and transmitted, and will be explained in detail below.

As is well known, the CMI code is
1#) into either @01" or 110" block, and data @1m (or ''O#
) is encoded alternately into blocks of @00" and extended "11'. In the following explanation, 10” of data is @0
1” and encode the data 11” to 100! or 11
Assume that the book is encoded alternately as 1”.

Since the CMI code has a redundant code structure, C
By applying RT, other information can be superimposed. Specifically, if the data 11# is encoded as ``00'', the next data ``1m'' will be @11.
The part that should be encoded as ``@00'' is intentionally encoded.

This is called a Hiro ``1'' CRV and has been used in the past for superimposed transmission of frame synchronization pulses.

In this invention, when CMI encoding a high-speed digital signal, a new @O'' CRY is used in addition to @1 ``(2) CRV for the purpose of superimposing a low-speed digital signal without changing the bit rate. That's it.

@o "oc RV means data po"o- which is originally -0
What should be encoded as ``1'' is encoded as @1o#.The rules for multiplying CRY are, for example, CRY
If the designated signal is "0m", high-speed data is CMI-encoded without applying CRT, and if the CRY designated signal is @12, if the high-speed data is 0#, then @0" is CRV, @
If it is 1", then -1" CRV is used.

FIG. 3 shows a configuration example of a CMI encoding circuit according to the CRY rule, in which high-speed data from the input terminal 101 is supplied to one input side of AND gates 302 and 308, and also to one input side of AND gates 303 and 304. It is inverted and input to one input side. The CRY designation signal from terminal 301 is AN
It is directly inputted to the other input side of the D gate 3o3, and is inverted and inputted to the other input side of the AND gates 302 and 304. The outputs of AND game) 3()2, 303, and 304 are respectively AND game) 305, 306, and 307.
is input to one input side of the . AND goo) 305,3
A high-speed clock pulse is input from the terminal 102 to each other input side of the AND gate 307, and this pulse is inverted and input to the other input 11 of the AND gate 307. AND gate 3
The output of 05 is input to a toggle type flip-flop 309, and each output of 306 and 307 is supplied to one input side of an OR gate 311 through an OR gate 310. The output of flip 70 tube 309 is supplied to the other input side of AND gate 308, which
The output of 08 is outputted to the output terminal 312 through the other input side of the OR gate 311.

FIG. 4 is a time chart for explaining the operation of the circuit shown in FIG. It is assumed that the high-speed data, the CRY designation signal, and the high-speed clock pulse inputted from the terminals 101, 301, and 102 are in phase with each other as shown in FIG. 4A, B, and CK. If they are not aligned, they can be aligned using a latch circuit as is well known.

In FIG. 3, the CRY designation signal O”
In a state where CMI encoding is not performed and only CMI encoding is performed, high-speed data @1'' is sent to the flip-flop 30 through AND gates 302 and 305 as a signal shown in Figure 4.
Therefore, the output shown in FIG. 4E, which is the input frequency divided by half, is obtained from the tritub flop 309. AND by the output of this flip-flop 309
Since the gate 308 is controlled to 11# of high-speed data
Hiro alternately passes through the gate 308 and outputs to the output terminal 312.
11'' or ``0G'' are output alternately.If the high-speed data is @0'', the output of , which appears at output terminal 312.

When the CRY designation signal of the terminal 30J becomes @1', the gates 302 and 304 are inhibited, so the high-speed data becomes "I".
In the case of , the inversion of the flip-flop 309 by @"1# is prevented, so in the example of FIG. 4, "11" is output where @00" should be output. If the data is @0”, AND gate 303
If the output of ND gate 306 is @1', then υ@10
# is output to terminal 312 instead of "01".

This figure 3 is an AND game) 302, 305, 308, clip 70 tube 309 is a commercial for high speed data "1m"
I code, perform its CRY, AND game) 303.3
04.306.307, OR game) 310 performs CMI code and CRY for high speed data @0'm. In this way, from the CMI code output terminal 312,
As shown in FIG. 4H, a CMI code multiplied by CRv is output.

The signal is sent out to this coded transmission path, reproduced and decoded by the receiving section.

FIG. 5 shows an example of the configuration of the receiving section reproduction and CMI decoding circuit, in which the code signal from the transmission path 111 is equivalently amplified by the equivalent amplifier circuit 501, and its output is sent to the timing circuit 50.
2 and the high-speed clock pulse is extracted, and the output of the equivalent amplifier circuit 501 is supplied to the D-type flip-flop p-tub 5.
03,504 data terminal DK is input. Clock pulses of mutually opposite phases from the timing circuit 502 are input to the trigger terminals T of these seven lip-flops 503 and 504. The Q output of the flip 70 tube 503 is supplied with an AND gate SOS, 5IOK, and the 100 output is a MUND game) 50
9,511. Q of slip 70 knob 504
The output is fed to AND gate 509.510 and the hundred output is fed to AND gate 5o8.511. The respective outputs of the AND gates 508 and 509 are input to the data terminal of the D-type 7-rip-7 quadruple 506 through the NOR gate 16. The outputs of the AND gates 510 and 511 are respectively input to AND gates 512 and 513, and the input clock to the trigger terminal T of the flip-flop 504 is also input to these gates 512 and 513. AND goo) 5
The outputs of 12 and 513 are respectively input to the set terminal S and reset terminal R of the set-reset type flip 70 knob 519, and are also input to the AND gate) 514 and 51, respectively.
5 is input. The Q output of flip-flop 519 is D
input to the data terminal of the flip-flop 505,
A clock applied to the trigger terminal of the flip-flop 5030 is applied to the trigger terminal T of the flip-flop 505. The Q output of flip-flop 505 is AND
The signal is inverted and input directly to the gate 514 and to the IAND gate 515 . AND) The output of 514 and 515 is OR
is input to OR gate 518 through gate 517, and O
The output of line AND gate 508 is also input to R gate 518 . The outputs of the NOR gate 516 and the OR gate 518 are input to the data terminals of the FiD type 7-lip 7 quadruple 506 and 507, and these flip-flops 506 and 507
The input clock to the trigger terminal T of the flip-flop 505 is input to the trigger terminal T of the 7-lip 70-tub 5.
Each Q output of 06.507 is a high-speed data signal output terminal 20
9, 1 is output to the CRY detection signal output terminal 520, and the output of the timing circuit 502 is output to the high-speed clock pulse output terminal 521.

FIG. 6 is a time chart for explaining the operation of the circuit shown in FIG. A pulse waveform as shown in FIG. 6 is outputted from the equivalent amplifier circuit 501, and its polarity is the same as the output of the CMI encoding circuit shown in FIG. 3 (FIG. 4H).

For example, the timing circuit 502 is configured such that the tank circuit is driven at the falling edge of the input power, and the timing circuit 502 is configured to drive the tank circuit at the falling edge of the input power, as shown in FIGS.
Outputs high-speed p-clock pulses with mutually opposite polarities. Therefore, the value of the first half of each bit of the input data (FIG. 6A) is read into the 7 lip-flop 503, the value of the eaves is read into the 7-lip 70-tub 504, and these 7 lip-flops 503.
Each Q output of 504 is as shown in Fig. 6, EK. Therefore, when the input sign is 101'', the output of AND gate 509 becomes @1'# as shown in FIG. 6F, which is inverted by NOR gate 516 and sent to flip-flop 506 as shown in FIG. The data is read, and a high-speed data signal @0'' is output to the terminal 209 as shown in FIG. 6G. If the input sign is @10”, the output of gate 508 is 111
), this is inverted by the NOR gate 516 and read into the flip-flop 506, and is connected to the terminal 209 as shown in FIG.
"01" is output as shown. Code ""01", '"
Since the output of the NOR gate 516 is film other than "10", "1" is output to the terminal 209.

If the input code is ``''10#, as mentioned above, AND
When the output of gate 508 goes high as shown in FIG. 6H, this is read into flip 70 knob 507, whose output goes high. CRT for “Tsumushi@0”
Specification is detected.

When the input sign is @"11", the output of the AND gate 510 becomes @1", and this and the clock are ANDed by the gate 512, and the output is as shown in FIG. 6I. On the other hand, If the input sign is ''001, AND gate 5
When the output of 11 is at a high level, this and the clock are ANDed by a gate 513, and the output becomes a high level as shown in FIG. 6J.

The outputs of these AND gates 512 and 513 (Fig. 6 I,
J) The shift flip 70 knob 519 is set and reset controlled, and its output is rounded to be read into the 7 flip flop 05, outputs are obtained alternately to the gates 512 and 513,
In other words, in the case of a regular CMI code for 9'1', the output of the 7 lip-flop 505 rises at the falling edge of the output of the gate 512, as shown in FIG.
It falls at the fall of the output of step 3]. Therefore, no output is produced from gates 514, 515 during such operation. but,
If outputs do not occur alternately from G) 512 and 511, but an output occurs continuously from one of them, G) 514,
An output from one side of 515 is produced as shown in the sixth diagram,
This is read into the 7 lip-flop 507, and the CMI code CRY designation for @1# is detected at the output terminal 520.

In this way, high-speed data signal output terminal 209 and CR
From the Y detection signal output terminal 520, signals G and N in FIG.
Waveforms as shown in Figure 6A are output, and these are delayed by a little more than one time slot than the waveforms in Figure 6A, and are restored to the original high-speed data signal (Figure 4A) and CRv designation signal (Figure 4B). It is a reproduction of. Therefore, by adding a low-speed digital signal to the CRV designation signal input terminal 301, it is possible to perform superimposed transmission of the high-speed CMI code without increasing its bit rate.

However, if CRY is applied too frequently, the timing circuit 502 will not operate properly, so there is an upper limit to the bit rate of the low-speed digital signal that can be superimposed. Assume that CRV is applied at regular intervals, and that the timing circuit 502 is configured to drive a tank circuit with a resonance frequency of fil at the falling edge of an input pulse. CR
In the case of a CMI code that is not multiplied by Y, a pulse falls at least once every three time slots, at a short interval between time slots. However, when CRY of "0#" is encountered, the pulse falls at the center of the time slot, so the tank circuit is driven in the opposite phase.

Considering the worst case in which high-speed data is always @01 in the time slot where CRY is applied, there must be at least two regular falling points of the pulse within the interval where CRV is not applied, and the conditions for this are: This means that the period in which CRV is not applied is 7 time slots or more. Therefore, the upper limit of the bit rate of low-speed digital signals that can be transmitted in a superimposed manner is flXnax −f h
/8.

The above is the basic principle of this invention, but what is confusing when actually using this invention is how to generate a CRY designation signal from a low-speed digital signal that is a pair of data and clock. Since this is a problem, we will explain the method in detail below. FIG. 7 shows a block diagram of the transmitting section in the first embodiment of the present invention, in which low-speed data from the terminal 103 is temporarily written to the batzer memory 701. The frame pattern generator 702 generates 7-ray 15 synchronizing pulses and also supplies read pulses to the pack memory 701 . The multiplexing gate 703 synthesizes the low-speed data read from the buffer memory 701 and the frame synchronization pulse to generate a CRY designation signal,
The signal is supplied to the CMI encoding circuit 704 shown in the figure.

FIG. 8 shows an example of a specific frame structure. In the time slot 12 for frame synchronization, CRY is always applied, and in the time slot 13 for low-speed digital signal superimposition, if the Hiro low-speed data is @1m or @Om, CRY is applied. @O”
If d@l” & then CRY is not applied. Time slot l at the interval of the frame synchronization time slot 12, time slot j at the interval of the low-speed digital signal superimposition time slot 13, and The reason for the difference is that the frame synchronization time slot 12 can be easily distinguished from the low-speed digital signal superimposition time slot 13 in order to ensure frame synchronization on the receiving side.

FIG. 9 shows a block diagram of the receiving section in the first embodiment of the invention with lines, and the input code is input from the transmission line 11 to the reproduction and CMI decoding circuit 901 shown in FIG. The CRT detection signal along with the high speed clock pulse is supplied to a frame synchronization circuit 902, and frame synchronization is established. The frame synchronization circuit 902 is a separation gate 903
supply control pulses to the acRV at isolation gate 903
The frame synchronization system is separated from the detection signal and only low-speed data is written to the backup memory 904. The contents of the backup memory 904 are read out using slow clock pulses that are created by dividing high-speed clock pulses or are supplied from other devices on the receiving side.
The original low-speed data is reproduced at the terminal 210. Comparing this embodiment with the conventional method described earlier, there is no need to prepare a clock pulse with a frequency of fm on the transmitting side, and only one backup memory is required on the transmitting and receiving sides. It has advantages such as being easy to use and easy to configure.

In the above theory of the first embodiment, it is assumed that the high-speed clock pulse and the low-speed clock pulse are synchronized, but if they are in an asynchronous relationship, it is necessary to perform stuff synchronization. , it is necessary to provide a time slot for inserting the stuff designation pulse even in the 7-frame configuration. Furthermore, in the above embodiment, a frame for superimposing a low-speed digital signal is configured independently of the frame configuration of the high-speed digital signal itself, but depending on the case, it is possible to make the latter subordinate to the former. When constructing a frame of a high-speed digital signal, low-speed data is superimposed on a specific time slot, and in that time slot, for example, low-speed data is
``If it is 11, multiply it by CRY, and if it is @0#, make it jin without multiplying CRY.

FIG. 10 IIi shows a block diagram of a transmitting section in a second embodiment of the present invention, in which a low-speed digital signal from a terminal 103 is converted into a DMI signal by a well-known D"MI encoding circuit 1001.
encoded. DMI code is data @01 (or @12) in "01" or "10" block, data @1m (or @Om) in "OOm or '
It is encoded into ``11'' blocks, and the polarity is always reversed at the break between blocks. In the following explanation, data "O" is encoded as @01# or @10", and data @1" is encoded as @00# or @11". An example of the waveform of the DMI code is shown in FIG. This DMI code is shown as a solid line and is reread by the D7 lip 7a tube 1002 with high speed clock pulses from terminal 102.

D type 7 lip flop 1003 is 7 lip flop 10
It functions to cause the output of G'2 to continue for 1/f h, that is, one cycle of the high-speed clock pulse. The 7 lip flop 10020Q output and the 1 output of 7 lip flop 1003 are input to
The output of the knob 1002 (the output and the Q output of the flip-flop 1003 are AND) is input to 1006, and the output of 1005 and 1006 is OR gate 1007
supplied to The gates 10G5, 1006, and 1007 function to take the difference between the outputs of the flip 70 knobs 1002 and 1003, and each time the polarity of the DMI code is reversed, the output of 1007 becomes @l for a period of 1/fh. (D-type flip 70 knob 1004 is goo)
It is used to align the phases of the output of the CMI code 1007 and the high speed clock pulse, and its output is supplied to the CMI encoding circuit 704 as a CRY designation signal. Therefore, each time the polarity of the slow DMI code is reversed, one fast C
When CRY is applied to the MI code, it becomes K.

FIG. 12 shows a block diagram of the receiving section in the second embodiment of the present invention shown in 10 mK, in which the CRY detection signal output from the reproduction and CMI decoding circuit 901 is guided to the toggle type flip-flop 1201. The DMI code (or its inverted polarity) is reproduced.

As is well known, even if the polarity of the DMI code is reversed, there is no problem with decoding.The reproduced DMI code is guided to a timing circuit 1202 and a decoding circuit 1203. The timing circuit 1202 uses a well-known method to set the frequency to 21.
A clock pulse of 1 or htt is generated, and the decoding circuit 1203 outputs a low speed data signal to a terminal 210 and a low speed p clock pulse to a terminal 1204 in a well-known manner.

In this embodiment, compared to the first real/male side, the maximum bit rate of the low-speed digital signal that can be superimposed is approximately 172, but there is no need to configure a frame for superimposing the low-speed digital signal, and the low-speed There is no need to prepare a buffer memory for speed conversion of digital signals, and low-speed digital signals can be superimposed on high-speed CMI codes and transmitted with an extremely simple hardware configuration.

Furthermore, if the low-speed clock pulse and the high-speed clock pulse are in an asynchronous relationship, in the first embodiment, it is necessary to perform stuff synchronization on the transmitting side and destuffing on the receiving side, which complicates the configuration accordingly. However, a major feature of this second embodiment is that the configuration of the transmitting and receiving sections remains the same regardless of whether they are synchronized or not. Naori MI
The code has the disadvantage that if the original data has a very long period of time, the decoder may lose block synchronization, but in order to avoid this, the code is When encoding the data "ol", encoding may be performed such that the polarity is reversed slightly ahead of the center of the block. A code such as ``Jin'' is newly named a ``one-modified DMI code''.DMI encoding circuit 10
Normally, a clock pulse with a duty ratio of 50 is input to o1, but in order to perform modified DMI encoding, this duty ratio may be slightly changed. Further, in the configuration shown in FIG. 12, K, which decodes the modified DMI code, uses the timing circuit 1202 to generate a pulse with a width of 17211 by triggering a monostable multivibrator at the polarity change point of the input pulse. The decoding circuit 120 is configured to drive a tank circuit with a resonance frequency of ft.
3 can be eliminated by configuring the circuit to identify whether or not the polarity of the code is reversed in the middle of a block, using a pulse supplied from the timing circuit 1202, for example, in the same way as a normal DMI decoding circuit.・If you use a modified DMI code, no matter how much '01 delay there is in the original low-speed data, the timing circuit will tell you that the frequency is ft, and its phase will always have a constant relationship with the modified DMI code input to the timing circuit. Since clock pulses are extracted stably, that is, block synchronization is always achieved, BSI is ensured even for transmission of low-speed digital signals.

FIG. 13 shows a schematic diagram of the transmitting section in the third embodiment of the present invention, in which low-speed data input from terminals 103 and 104 and low-speed clock pulses are converted into one binary symbol by a low-speed clock pulse encoding circuit 1301. . In this case, it is necessary to be able to reproduce the original low-speed data and low-speed clock pulse from this binary symbol, and from the viewpoint of ensuring BSI, for example, CM
I code is preferable. The frequency dividing circuit 1302 is connected to the terminal 102
The frequency of the high-speed clock pulse from 1 is divided, and a pulse with a width of 1/fh is generated at a rate of 1 for every n pulses. A gate 1303 performs a logical product of the output of the encoder circuit 1301 and the output of the encoder circuit 1301.
This is taken as the CRV designation signal to the CMI encoding circuit 704. In this case, the minimum value of the time interval at which the polarity of the binary symbol output from the encoding circuit 1301 changes is n
/f It is necessary to be several times or more of h.

FIG. 14 shows a schematic diagram of the receiving section in the third embodiment of the present invention, in which the CRY detection signal output from the reproduction and CMI decoding circuit 901 is transmitted to the monostable multivibrator 1.
401, where a pulse of width n/fh is created. The output of the monostable multivibrator 1401 is a reproduction of the binary symbol output from the encoding circuit 1301. This output is led to a timing circuit 1402 and a decoding circuit 1403, where the original low-speed data and low-speed clock pulses are recovered.

Similar to the second embodiment, this third embodiment also has the advantage of being able to transmit a low-speed digital signal by superimposing it on a high-speed CMI code with a very simple hardware configuration. However, the maximum bit rate of the low-speed digital signal that can be superimposed is still a fraction of that of the tlE2 embodiment. Instead, even if spike-like noise occurs in the low-speed binary strokes reproduced due to an error occurring in the transmission path, the noise can be removed by filtering the noise (not shown). is possible, and therefore the transmission quality of low-speed digital signals is extremely improved.

Note that in this third embodiment, the low-speed binary symbol is @1”
Then, a fast CMI code requires CRY every n time slots.
The configuration is such that if it is ``gaka\shi, @0'', all <
If it is 0#, then CRY is done every n time slots, @1
``In that case, it is also possible to perform superimposed transmission of low-speed binary strokes with a configuration in which all<CRY does not occur.

As explained above, according to the present invention, when CMI-encoding a high-speed digital signal, it is possible to superimpose a low-speed digital signal on it and transmit it using a simple hardware configuration without increasing the bit rate. In particular, in the second and third embodiments of the present invention, this can be done with a very simple I-doware configuration regardless of whether the high-speed digital signal and the low-speed digital signal are synchronized. Therefore, the present invention provides an extremely effective means when a high-speed digital signal and a low-speed digital signal are to be simultaneously transmitted using one transmission path.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a transmitting unit when transmitting high-speed digital signals and low-speed digital signals by time division multiplexing, Fig. 2 is a block diagram showing a receiving unit for the transmitting unit in Fig. 1, and Fig. 3 is CRv+t commonly used in this invention
A logic circuit diagram showing an example of the configuration of a CMI encoding circuit, a time chart for explaining the circuit operation in the fourth figure, and a time chart for explaining the circuit operation in FIG. FIG. 6 is a logic/circuit diagram showing an example of a circuit configuration. FIG. 6 is a time chart for explaining the circuit operation of the FLC diagram. FIG. 7 is a block diagram showing a transmitter in the first embodiment of the present invention. FIG. 8 is a diagram showing an example of the frame structure in the first embodiment, FIG. 9 is a block diagram showing the receiving section in the first embodiment, and FIG. 10 is a block diagram showing the transmitting section in the second embodiment of the present invention. , FIG. 11 is a waveform diagram showing examples of DMI codes and modified DMI codes,
FIG. 12 is a block diagram showing a receiving section in a second embodiment of the invention, FIG. 13 is a block diagram showing a transmitting section in a third embodiment of the invention, and FIG. 14 is a block diagram showing a receiving section in a third embodiment of the invention. FIG. 101: High speed data signal input terminal, 102: High speed clock pulse input terminal, 103: Low speed data signal input terminal,
104: Low-speed clock pulse input terminal, 105, 106
: X7 memory, 107: Multiplexed clock pulse input terminal, 108 = Frame pattern generation circuit, 109: Multiplexed gate, 110: Encoding circuit, 111: Transmission line, 2
01: Reproduction circuit, 202: Decoding circuit, 203: Frame synchronization circuit, 204: Separation gate, 205.206: X7 memory, 207: High speed clock pulse input terminal,
208: Low-speed clock pulse input terminal, 209: High-speed data signal output terminal, 210: Low-speed data signal output terminal,
301: CR'V designated signal input terminal, 302i3G3.
304.305.306.307.306: AND gate, 309: T7 lip flop, 310.311:
312: CMI code output terminal, 501: Equivalent amplifier circuit, 502: Timing circuit, 503.504
．． 505. 506.507: D type flip-flop, 508.50
9,510,511,512,513゜514.515
:AND gate, s1e: NOR gate, 51
7.518: OR gate, 519: SR7 rig 7E tab, 520: CRY detection signal output terminal, 521: High speed clock pulse output terminal, 701: X7 memory, 70
2: 7-lem pattern generator, 703: multiplexing gate,
704: CMI encoding circuit of FIG. 3, 901: Reproduction and CMI decoding circuit of FIG. 5, 902: Frame synchronization circuit, 903: Separation gate, 904: Back-up E-J
)-v-1001: DMI encoding circuit, 1002
．． 1003.1004: D type flip-flop, 100
5,1006: AND Gamegoo 1007: OR gate,
1201: T-type flip 70 tube, 1202: Timing circuit, 1203: DMI encoding circuit, 12G4: Low-speed clock pulse output terminal, 1301: Encoding circuit, 13
02: Frequency divider circuit, 1303: ANI) gate, 1401
: Monostable multivibrator, 1402: Timing circuit, 1403: Decoding circuit. Patent applicant: Takashi Kusano, agent of Nippon Telegraph and Telephone Public Corporation

Claims (1)

[Claims] (1) In a digital signal transmission method in which a low-speed digital signal is superimposed on a high-speed digital signal and transmitted, the high-speed digital signal is subjected to CMI encoding, and the expanded high-speed data is transmitted in the time slot in which the low-speed digital signal is superimposed. 1” (Hiro @0”) and this is @11
” (or “oo”), it is encoded as “00# (or -11’), and high-speed data is @0# (or @1”) and this is @01’
(or 110”) in the case of CMI code code fossil, conversely encode CRY to “10” (or ``01”)
A digital signal transmission method characterized in that a low-speed digital signal is superimposed on a high-speed CMI code and transmitted.