JPS5829908B2 - Signal processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal processing method for converting short-period binary signals into long-period binary signals by partially overlapping them. The present invention relates to a signal processing method that can improve recorded image quality when the number of bits per line is different.

In digital facsimile transmission, where the image reading means on the transmitting side is a photo diode array and the recording means on the receiving side is a heat-sensitive recording element array, the number of bits per line (read dot density) on the transmitting side is A problem arises when the number of bits per line (recording dot density) on the receiving side is different.

First, when a signal read at high resolution is modulated using an analog modem and transmitted, the minute jitter during transmission is magnified by 1 for each recorded dot on the recording side, reducing the image quality. It will deteriorate it.

Furthermore, even when a high-resolution signal is sampled using a recording clock on the transmitting side in order to synchronize the transmitting and receiving clocks, the image quality deteriorates because the button signals are missed or overlapped more than necessary at the time of sampling.

The latter example will be explained with reference to the drawings.

In the conventional sampling method shown in Fig. 1, a binary image signal a read at high resolution is guided to an edge-trigger type flip-flop 1, and the same flip-flop 1 is driven at the rising edge of a clock b. .

This clock b is the output of the oscillator 2 divided by the divider 3, and has the same frequency as the recording clock.

With the above configuration, as shown in FIG. 2, the binary signal string a is sampled at the rising edge of the clock b, and the flip-flop 1 obtains the binary signal string C having the recording clock component. .

The number of bits in one line of this binary signal C is equal to the number of dots in one line on the recording side.

However, as shown in FIG.
n s n at the sampling point position in value signal sequence a
+ 2 s n + 3 s n + 5... Since it has only the n+1 . . .th bit information between the sampling points. The n+4th bit information is missing, and image quality deterioration due to this loss is unavoidable.

The conventional sampling method shown in FIG. 3 is an improvement on the method shown in FIG. Clock the output of 4 b
It was designed to be sampled.

The flip-flop 4 inputs It 1 k in the binary signal sequence a.
It is set by l and reset by the output of the differentiating circuit 5 which differentiates the clock b.

Therefore, the flip-flop 4 stores the logical sum of adjacent bits between each sampling point in the binary signal string a, and as shown in FIG. Column d includes all bit information of binary signal sequence a.

However, there are n between adjacent bits of the binary signal string d.
, n + 2 I n + 3...There is a strong tendency for the m-pit information in the binary signal sequence a to be distributed overlappingly, and if this overlapping bit is (41kl), the recorded image will be blackish Thus, the image quality deteriorates in a tendency opposite to that shown in FIG.

The present invention has been made in view of the above points, and the converted binary signal string contains all the bit information of the original binary signal string,
Moreover, the present invention provides a signal processing method in which the same bit information of the original binary signal does not overlap between adjacent bits.

Based on Figures 5 and 6 below, the reading dot density is n lines/1n.
An embodiment of the present invention applied to a facsimile machine having a recording dot density of 11L and a recording dot density of m dots/mm will be described.

FIG. 5 shows a signal processing section on the transmitting side, and the same parts as those mentioned above are given the same reference numerals.

In the figure, numeral 6 denotes a frequency divider which divides the output of the oscillator 2 by m, and the output of the frequency divider 6 drives a signal reading section 7 such as a photo diode array.

The output A of the signal reading section 7 is the image plane scanned.
(Black) "0" (White) It is a binary image signal, and each bit length is TT.

8 is a frequency divider that divides the output of the oscillator 2 by n()m, and its output B has a period TR (>TT) determined by the frequency division ratio.
and the time width of the it 1 n level is set to be TT.

This signal B is led to four flip-flops of the set-reset type and to a flip-flop 1 of the edge-trigger type.

The flip-flop 4 is kept in a reset state during the period when the signal B has a level of it 1 >i.

Furthermore, flip-flop 1 reads the output of flip-flop 4 at the rising edge of signal B.

If the signal processing section has the above configuration, the flip-flop 4
is the period T during which the signal B is ttObb (=TR−T
) may be set by the original binary signal A,
The period TT in which the signal B is it 1 hs is in a reset state.

Therefore, the reset output of flip-flop 4 is ((
0)) and the output set by it 11Th in the binary signal string A is it I Thm, then the output of the flip-flop 4 is even partially ( j 11) If there is a level part, tt 1 n, and the original binary signal sequence A corresponding to the same period T has all < it
1 If there is no n-level part (j 01Th,
A waveform connects these to the tc Oss level of the reset period TT.

If this signal processing is generally explained with reference to FIG.
The bit information of the original binary signal string A corresponding only to the tt OITh period of the signal B is sampled at the end of the same period T and distributed to the binary signal string C having the bit length TR.

In the example of FIG. 6, each bit of the binary signal string C includes (n),
(n+1.n+2).

(n+3), (n+4.n+5), (n+6.n+
7)... All the bit information of the original binary signal string A is not redundantly distributed between adjacent bits and is included in the IFL.

In the embodiment described above, which solves both the disadvantages of the first analogy and FIG.
Vc, % - time width TT ((1b% part is set to reset state, and only the time width (TR-TT) "Ohs part" is settable state,
Furthermore, the same ((Flip flop 4 at the end of the Oh'r part
However, the present invention is not limited to the configuration of the above-described embodiment, and the point is that the binary signal sequence A of bit length TT is sampled for a period of (TR - TT) with a period of TR. Any device can be used as long as it can detect and generate a binary signal string C having a bit length TR of "1" level or tt Oss level in response to the presence or absence of Oct 1 n level within the synchronization.

According to the signal processing method of the present invention described above, when this is applied to a facsimile machine in which the number of bits per line differs between sending and receiving, deterioration in the quality of the recorded image can be prevented as much as possible.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional sampling method, Fig. 2 is a signal waveform diagram of each part of Fig. 1, Fig. 3 is a block diagram showing an improved example of the conventional sampling method, and Fig. 4 is a block diagram showing an example of the conventional sampling method. FIG. 3 is a signal waveform diagram of various parts, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIG. 6 is a diagram of signal waveforms of various parts of FIG. 1... Edge trigger type flip-flop, 2...
... Oscillator, 4... Set/reset type flip-flop, 6, 8... Frequency divider, 7... Signal reading section.

Claims (1)

[Claims] 1 It corresponds to a signal processing method that converts a binary signal string in which each bit length is TT to a binary signal string having a bit length TR longer than the above bit length, and has a period TR and it 1
It consists of a signal generating section that generates a signal whose time width of the hs level is set to be TT, and a reset type flip-flop.
- a first flip-flop circuit that can be reset for a period of time (TT) and stores the signal level of the binary signal string having the bit length TT that arrives during this period; The signal L// stored in the first flip-flop circuit operates at
a second flip-flop circuit consisting of an edge-trigger type flip-flop that samples a signal and outputs the sampling result as a binary signal string having a rabbit length TR.