JPS5829207A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To obtain an output current increasing function and a temperature compensating function by connecting a bipolar transistor (TR) and an MOSTR in series into an emitter follower system, and connecting a gate electrode to an output terminal. CONSTITUTION:A bipolar NPNTRQ21 and an N channel MOSTR21 are connected in series between power terminals 6 and 7, the base of the TRQ21 is connected to the output terminal of a linear amplifying circuit in an operation amplifier through an input terminal In, and the gate of the MOSTR21 is connected to an output terminal O and also connected to the connection point 8 of both the TRs. If the temperature rises, the base current of the TRQ21 increases to raise the potential at the connection point 8 toward a power potential VDD, and then the gate potential of the TR21 is raised, so the TR21 decreases in impedance to lower the potential at the connection point 8, thus holding the voltages at the connection point 8 and output terminal O constant.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an output 7171 circuit suitable as an output passer for an M0808 transistor.

[Technical Background of the Invention and Problems Therewith] In general, Mo11) transistors are high impedance elements, so when constructing a circuit using Mo11) transistors, it is not reasonable to lower the output impedance of Mo11). The usual method for this purpose is to widen the channel width and shorten the channel length of the M08 transistor used as an output buffer, but this method also has its limitations; for example, in operational amplifier circuits ( If a large output current is required, such as in an operational amplifier, some kind of countermeasure is required. This means that when the operational amplifier is formed using MO8 transistors, the +7 near amplifier circuit installed after the differential amplifier stage is rounded, which requires sufficient voltage gain, and the frequency characteristics do not extend too much. This is because the output current cannot be increased.

Therefore, as a solution to the above problem, it has been conventionally known to use an entuta follower circuit using a bipolar transistor as the output buffer circuit of the operational amplifier. First, an example of the operational amplifier shown in FIG. 1 will be explained. This circuit is roughly divided into a constant current source bias circuit 1, a differential amplifier circuit 2. offset compensation circuit 3,
Threshold matching circuit 4. In the constant current source bias circuit 1, the P channel 11M0
I) The transistor Tr1oy-2 end is connected to the potential (+VDD) supply terminal -, the drain end of the transistor Tr□ is connected to the other power supply potential (-V, , ) supply terminal 7 via the resistor 8, The gate and drain of the transistor Tr1 are commonly connected to obtain a constant voltage.

In the differential amplifier circuit 2, a P-channel type Mo1 for constant current source is used.
Ranjista Tr! The source end of is connected to the power supply terminal 6KmM,
Transistor Tr! The drain end of is P for differential input stage element.
channel fiMO11) transistors,? It is commonly connected to the source end of f4. Transistor Tr@, T
The drain end of r4 is connected to the power supply terminal 7 via N-channel type load M08 transistors 'I'r@ and Tr@, respectively. The gate of the transistor Tr2 is connected to the drain end of the transistor Tr1, and the gate of the transistor Tr2 is connected to the drain end of the transistor Tr1.
The gate of transistor Tr3 is connected to the operational amplifier input voltage supply terminal tnlK, the gate of transistor Tr4 is connected to the operational amplifier input voltage supply terminal tn2Km, and the transistor Tr@,
The gates of Tr. are commonly connected.

In the offset adjustment circuit 3, the constant current source P channel 11
M0Ii) The source end of the transistor TTy is connected to the power supply terminal 6, and the drain end of the transistor 〒r, is connected to a pair of P
Channel 11M08) Transistor Tr@.

The scissors transistor Tr
The drain common connection part of @, Tr・ and t6 output terminal Og are N
The channel load M08 is connected to the power supply terminal 7 via the transistor Tr. The gate of the transistor Tr y is connected to the drain end of the transistor Tr1, the gate of the transistor Tr is connected to the input terminal in2, the gate of the transistor Trs is connected to the input terminal inl, and the output terminal og is connected to the transistor Trl, Tr・、
Commonly connected to the gates of the Tr logic.

In the threshold matching circuit 4, the power supply terminal 6 is connected to the P-channel type load M08 transistor TrB, the N-channel shield part operating M
O8) Connected to the power supply terminal 7 via the transistor Tr12. The drain end of transistor Trll t! I
The output terminal 03 is connected to the gate of the scissors transistor T11, and the gate of the transistor T12 is connected to the drain terminal of the transistor T'rl of the differential amplifier circuit 2 and the output terminal 01.

In the linear amplifier circuit 5, the power supply terminal "6" is connected to the P-channel load M0B transistor Tr13. N-channel inspector MO8) Power supply terminal 7K via transistor T r 14
m! It is continued. The transistor ISO gate is connected to the output terminal 0 of the threshold matching circuit 4, and the drain terminal of the F transistor r1m is connected to the operational amplifier output terminal outK.
m! The gate of the transistor Tr14 is connected to the drain terminal of the transistor Tr4 of the differential amplifier circuit 2 and the output terminal 02 of the differential amplifier circuit 2.

Next, we will explain the operation of the operational amplifier with the above configuration.
illh increase@Circuit 2, constant current source transistor Tr
■ operates in saturation with the DC bias from bias circuit 1,
For example, a constant DC voltage is applied to the input 1n2, and the input &fil
A signal consisting of a constant DC voltage and an AC voltage is applied to the gates of the load transistors Trg and 〒r. The bias voltage of the output Og of the offset compensation circuit 3 is applied to the gates of the load transistors Trg and 〒r. As long as the transistor TJ operates in the saturation region (ζ), the drain current of the vaginal transistor Tr2 is kept constant. Further, in the range where the constant current source transistor T r 1 of the offset compensation circuit 3 operates in the saturation region, its drain current is constant, so the inputs 1nl, in2
The voltage at the output O8 remains substantially constant regardless of the voltage at the output O8, and therefore the gate biases of the load transistors Try and Tr@ of the differential amplification stage do not change.

If the DC voltage level of inputs inl and in2 are both high, the constant current transistor T of the differential amplification stage
r, enters the non-saturation region, the drain current of the transistor Try decreases, and the output of the differential amplifier stage 01.0. DC voltage level becomes low. In order to prevent fluctuations in the output DC voltage level of the differential amplifier stage due to such offset voltage, the offset compensation circuit 3 is assumed to have the following functions. That is, when the drain current of the constant current source transistor Tr2 of the differential amplifier stage decreases,
In proportion to this, the load transistor T r @,
By lowering the gate voltage of T r @, the output DC voltage level of the differential amplifier stage can be made constant. Same), K 雫＠zHm4 e iEmi”gms # gmB=
gnnl °++−−−−−+(1) Has:
凘ms ” まし = knv: gms
``gmto/2''・''' (2).The equation is 9, where W is the channel width of the MθB transistor, L is the channel length, and gas is the gm% of the transistor Tr2. Similarly, j1m3 to gml.

is the transistor Tr@y'r'l (Jim of 1).

The relationship between the above equations (1) and (2), that is, the ratio between the constant current transistors 'i' r 2 and T r 7, and the input stage transistor Trs.

gm ratio between 711 and a pair of load transistors Tr@.

Load transistor Tri for the sum of ff1= of r.
In particular, if the oOgm ratio is set to the same relationship, the drain current of the constant current transistor T r 7 of the offset compensation circuit 3 will also decrease in the same way as the drain current of the transistor Try, so the load transistor 'rrto will decrease by that amount. Drain current also decreases. Therefore, load transistor Tr6. The Tr@ and gate potential also decrease in accordance with the above-mentioned current decrease, thereby making the DC level of the outputs 01 and 0g of the differential amplifier stage constant.

On the other hand, the threshold matching circuit 4 outputs the output 01. of the differential amplifier stage.
Preventing deviation between the input/output characteristics of the linear amplifier circuit 50 and the output voltage of the differential amplifier stage regardless of the DC level of O,
This circuit always tries to keep the DC level of the operational amplifier's output Out constant. That is, input inl as above,
When the DC voltage levels of in2 both rise, even if the DC voltage levels of outputs 01 and 0□ of the differential amplifier stage decrease by 9, the DC bias of the output Os of the threshold matching circuit 4 will change accordingly. rises, so the operational amplifier output Out
The DC voltage will be made constant. However, in this case as well, it is necessary to adjust the g ratio of the transistors Tr 11-T"14, but the 11 g between these transistors must be adjusted.
m ratio (W/L ratio), gmo: gmlz = Ilm, s: gmta
・・・・・・・・・・・・・・・Set as shown in (3). However, Jlmll is a transistor Trll
Similarly, gmts~gm 14 is the jim of transistors 'I'12~T'14.
), the relationship between the load transistor Tr11. Tr1
gm ratio between B and driving transistor “l11m”14
In particular, by making the gm ratio between them the same, the DC level of the operational amplifier output oul can be made constant. However, in this case, the output is 0. Even if ,O, fluctuates, the condition that these output voltages are equal is required.
Since 1°03 is the output of the differential amplification stage, the above condition is satisfied as long as the differential amplification stage has a symmetrical configuration as described above. In this way, input in1. Regardless of the DC voltage level of in2, the DC level of the operational amplifier output Out can be made constant.

In order to increase the output current of such an operational amplifier, for example, an output buffer circuit based on the output buffer circuit of the output buffer circuit, which can be seen in Japanese Unexamined Patent Publication No. 51-123038, has been considered. It is coming. On the other hand, as described above, the offset of the operational amplifier needs to be kept small enough to make the offset compensation circuit 3 internally IR, and it is also desired to keep the offset small even with respect to temperature changes. However, the conventional output buffer circuit described above does not consider such an offset problem at all, and cannot exclude the effects of temperature changes. Moreover, for this reason, conventional output buffer circuits have problems such as thermal runaway.0 [Object of the Invention] The present invention provides an output buffer circuit with a simple circuit configuration that can solve the above problems. This is what we provide.

[Summary of the Invention] The output buffer circuit of the present invention employs a Niotsuta follower system in which a bipolar transistor and an M08 transistor are connected in series between one electrode and the other electrode of a power supply, and the gate electrode of the MO8 transistor is connected to the output. This circuit configuration is characterized in that it can perform the original output current increasing function and the temperature compensation function at the same time.

[Embodiment of the Invention] Next, an embodiment of the present invention will be described with reference to FIG. The output buffer circuit company uses bipolar N between power supply terminals 6 and 7.
PN) transistor Q21sN channel type M08 transistor Tr21 is connected in series. The base of this transistor Qitl is connected to the input terminal In, and this input terminal is connected to the output terminal ou1 of the air amplifier circuit 5 in the operational amplifier shown in FIG. M
08 The gate of the transistor Tr2H is connected to the output terminal 0, so it can be ignored.0 In the operational amplifier circuit of FIG. 1, the linear amplifier circuit 8 requires a sufficient voltage gain, so Frequency characteristics: Does not extend much, making it impossible to increase the output current. In other words, if the QB product is constant, if the voltage gain G is increased, the band width B becomes narrower, and the narrower band width 1 corresponds to the fact that a large current cannot flow instantaneously, so the output current is small. In the embodiment shown in FIG. 2, the output buffer base is configured as a follower to greatly increase the output current, and a MOIS transistor Tr21 is used as the load of the output buffer. The problem is the bipolar transistor Q used as a Niotsuta follower.
21 temperature characteristics.

That is, while the temperature coefficient of current in a chip-board transistor is positive, that in a MOS transistor has the opposite characteristics. Therefore, in the circuit shown in Fig. 2, the gate of MOS transistor Tr21 is connected to connection point 8, and one output terminal is connected to output terminal 0 in order to modify the temperature characteristics (for example, temperature drift, etc.) of the emitter and follower. are doing. To explain how the temperature characteristics are changed as a result,
When the temperature rises, the vane current of the transistor Q2M increases and attempts to raise the potential at the connection point 8 toward the power supply potential VDD. In this way, the potential of connection point 8 (output terminal 0
When the potential of the N-channel MO8) increases, the gate potential of the transistor Tj21 increases. This transistor Try lowers its impedance and operates to lower the potential of the connection point 8, keeping the voltage of the connection point 8 and the output terminal 0 constant. It becomes K like that. In other words, the output parallel circuit shown in the embodiment of FIG. 2 can increase the output current and improve the temperature characteristics with such a simple configuration. Note that the present invention is not limited to the above embodiment. For example, by reversing the polarity of the elements used in Fig. 2, S K
It is also possible to have a configuration as shown in diagram S.

Further, in the embodiment, the present invention was used as an output paraphrase of the MOafi operational amplifier, but the application is not limited to this.

[Effects of the Invention] As explained above, according to the present invention, an increase in output current, temperature compensation, and improvement in frequency characteristics can be achieved with a simple circuit configuration in which the gate of the MO8 transistor is connected to connection point 8 using an emitter follower method. An output buffer circuit that can be improved can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an operational amplifier, and FIGS. 2 and 3 are circuit diagrams of an embodiment of the present invention. 21... Output buffer, Q21... Bipolar transistor, Tr21...
MOS) transistor. Kensuke Chika (ns・l, bar clerk)
) electric 10 ss

Claims (1)

[Claims] A bipolar transistor and an MO8 transistor are connected in series between one electrode and the other electrode of a power source, the base electrode of the bipolar transistor is connected to the input signal supply end, and the output terminal is connected to the connection point between the two transistors. Connect to configure a factory follower circuit, and connect the above MO8.
) An output buffer circuit characterized in that the gate of a transistor is connected to the output terminal.