JPS5828924B2 - automatic gain control device - Google Patents
automatic gain control deviceInfo
- Publication number
- JPS5828924B2 JPS5828924B2 JP51148232A JP14823276A JPS5828924B2 JP S5828924 B2 JPS5828924 B2 JP S5828924B2 JP 51148232 A JP51148232 A JP 51148232A JP 14823276 A JP14823276 A JP 14823276A JP S5828924 B2 JPS5828924 B2 JP S5828924B2
- Authority
- JP
- Japan
- Prior art keywords
- gain control
- circuit
- automatic gain
- response
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000004044 response Effects 0.000 claims description 28
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000013019 agitation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004043 responsiveness Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】
本発明はAM変調された搬送波信号等の自動利得制御装
置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain control device for AM-modulated carrier signals and the like.
AM変調された搬送波信号の自動利得制御方式において
は変調波信号の波形歪が問題となることがある。In automatic gain control methods for AM-modulated carrier signals, waveform distortion of the modulated wave signal may pose a problem.
たとえばテレビ中継放送装置Oこおいては、自動利得制
御系統の時定数によっては同期型(サグ)が発生するた
めコンデンサを挿入し時定数を大きくして発生を防いで
いる。For example, in television relay broadcasting equipment O, synchronization type (sag) may occur depending on the time constant of the automatic gain control system, so a capacitor is inserted to increase the time constant to prevent this from occurring.
しかし時定数を大きくすると、制御制御の応答に時間が
かかり、入力電波の突入時等に過大出力となり電力増1
鴫部を破壊することができる。However, if the time constant is increased, it will take time for the control to respond, resulting in excessive output when input radio waves rush in, resulting in an increase in power of 1.
You can destroy Shirobe.
このため従来は第1図のように利得制御増幅器11の利
得を制御するために検波器12.13にて検波したのち
応答の速い内部自動利得制御回路(内部AGC)14と
時定数の大きい外部自動利得制御回路(外部AGC)1
5との2つの自動利得制御系統を設け、内部AGCの設
定値14を外部AGC15の設定値より高くしておき、
通常の制御は外部AGC15で行ない放送開始時等の急
激な入力増加時に内部AGC14を動作させて電力増幅
部16の保護を行なっている。For this reason, conventionally, as shown in Fig. 1, in order to control the gain of the gain control amplifier 11, the wave is detected by a detector 12, 13, and then an internal automatic gain control circuit (internal AGC) 14 with a fast response and an external circuit with a large time constant are used. Automatic gain control circuit (external AGC) 1
5 and two automatic gain control systems are provided, and the internal AGC setting value 14 is set higher than the external AGC setting value 15,
Normal control is performed by the external AGC 15, and the internal AGC 14 is operated to protect the power amplification section 16 when the input suddenly increases, such as at the start of broadcasting.
しかしこの場合でも第2図のように電力増幅部16が分
配器16a1合戊器16bと組合せて並列接続されたn
個の電力増幅器161.162・・・・・・16nで構
成されている場合に、r個の電力増幅器が故障した時に
は出力が低下し、外部AGC15が働かなることによっ
て利得制御増幅器11の出力が増加し内部AGC14の
設定値Gこ達する。However, even in this case, as shown in FIG.
When the power amplifiers 161, 162, . It increases and reaches the set value G of the internal AGC 14.
すると内部AGC14で利得制御がなされ、サグが発生
し、問題となる。Then, gain control is performed by the internal AGC 14, causing a sag, which becomes a problem.
本発明はこのような欠点を除去したもので、以下にその
実施例(こついて説明する。The present invention eliminates these drawbacks, and examples thereof will be explained below.
第3図において第1図の装置を構成する部分と同一部分
には同符号を付している。In FIG. 3, the same parts as those constituting the apparatus in FIG. 1 are given the same reference numerals.
異なるのは自動利得制御系統17の中に即応各回路17
aと遅応答回路17bを並列に設け、即応各回路17a
の設定値を遅応答回路17bの設定値より高めに設定し
、即応各回路17aで急激な入力増加時の電力増幅部1
6等の保護を行ない、遅応答回路17bで通常時のサグ
のない自動利得制御を行なうようにしたものである。The difference is that each quick response circuit 17 is included in the automatic gain control system 17.
a and the slow response circuit 17b are provided in parallel, and each quick response circuit 17a
is set higher than the setting value of the slow response circuit 17b, and each quick response circuit 17a is used to increase the power amplification section 1 when the input suddenly increases.
6 etc., and the slow response circuit 17b performs automatic gain control without sag during normal operation.
したがって応答性がよくしかも波形歪の発生しな(/煽
動利得制御を行なうことができる。Therefore, responsiveness is good and waveform distortion does not occur (/agitation gain control can be performed).
また第4図および第5図はそれぞれテレビ信号等の多周
波信号(こおける自動利得制御にお0)で2重検波方式
の検波器18を用いた場合の実施例であり、即応各回路
17a1遅応答回路17bを設けることにより急激な入
力増加にも充分な保護機能を有する過度特性にすぐれた
自動利得制御を1系統でも行なうことができる。Furthermore, FIGS. 4 and 5 each show an example in which a double detection type detector 18 is used for a multi-frequency signal such as a television signal (automatic gain control is set to 0), and each of the immediate response circuits 17a1 By providing the slow response circuit 17b, automatic gain control with excellent transient characteristics and sufficient protection against sudden increases in input can be performed with just one system.
なお第6図は上記した第3図〜第5図における即応各回
路17a1遅応答回路17bの具体構成を示すもので、
ダイオード19,20、増幅器21.22、コンデンサ
23等により構成される。Incidentally, FIG. 6 shows the specific configuration of each quick response circuit 17a1 and slow response circuit 17b in FIGS. 3 to 5 described above.
It is composed of diodes 19 and 20, amplifiers 21 and 22, a capacitor 23, and the like.
なお、第6図において示したように、即応各回路の時定
数素子を省略してダイオード及び増幅器素子固有の時定
数を利用しても良い場合もあることは言うまでもない。It goes without saying that, as shown in FIG. 6, the time constant elements of each immediate response circuit may be omitted and the time constants specific to the diodes and amplifier elements may be utilized.
上記実施例より明らかなように本発明によれば、増幅器
と時定数回路と検波用ダイオードの直列接続により構成
されているので応答特性を損うことなく過大入力にも対
処できると共に、2重検波器を用い、かつ、その出力を
応答特性の異る二つの応答回路に共通入力しているので
、過渡応答特性が改善され、またレベル変動に対する信
頼性の高い自動利得制御装置が得られる特長を有する利
得制御装置を提供することができる。As is clear from the above embodiments, according to the present invention, since the amplifier, the time constant circuit, and the detection diode are connected in series, it is possible to cope with excessive input without impairing the response characteristics. Since the output is commonly input to two response circuits with different response characteristics, the transient response characteristics are improved and an automatic gain control device with high reliability against level fluctuations is obtained. A gain control device having a gain control device can be provided.
第1図、第2図は従来の自動利得制御装置のブロック図
、第3図は本発明の一実施例による自動利得制御装置の
ブロック図、第4図は他の実施例のブロック図、第5図
はさらに他の実施例のブロック図、第6図は要部の結線
図である。
11・・・・・・利得制御増幅器、12・・・・・・検
波器、17a・・・・・・即応各回路、17b・・・・
・・遅応答回路。1 and 2 are block diagrams of a conventional automatic gain control device, FIG. 3 is a block diagram of an automatic gain control device according to one embodiment of the present invention, and FIG. 4 is a block diagram of another embodiment. FIG. 5 is a block diagram of still another embodiment, and FIG. 6 is a wiring diagram of the main parts. 11...gain control amplifier, 12...detector, 17a...immediate response circuits, 17b...
...Slow response circuit.
Claims (1)
ぞれ増幅器と時定数回路と検波用のダイオードの直列接
続から成る応答速度の異る即応各回路と遅応答回路と、
前記即応各回路および前記遅応答回路の両者の出力Oこ
応じてテレビ信号の利得制御する利得制御回路と、前記
増幅器により、前記即応各回路の出力設定値を前記遅応
答回路の出力設定値より高めに設定することにより入力
の急激な増加に対しては前記即応各回路で、通常時にお
いては前記遅応答回路で自動利得をおこなわせることを
特徴とする自動利得制御装置。1. Each of the outputs of the same two-type detector is inputted, and each quick response circuit and slow response circuit have different response speeds, each consisting of an amplifier, a time constant circuit, and a detection diode connected in series,
A gain control circuit that controls the gain of the television signal according to the outputs of both the quick response circuits and the slow response circuit, and the amplifier, adjust the output settings of the quick response circuits from the output settings of the slow response circuit. An automatic gain control device characterized in that by setting the gain to a high value, the quick response circuits perform automatic gain in response to a sudden increase in input, and the slow response circuit performs automatic gain in normal times.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51148232A JPS5828924B2 (en) | 1976-12-08 | 1976-12-08 | automatic gain control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51148232A JPS5828924B2 (en) | 1976-12-08 | 1976-12-08 | automatic gain control device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5372441A JPS5372441A (en) | 1978-06-27 |
JPS5828924B2 true JPS5828924B2 (en) | 1983-06-18 |
Family
ID=15448210
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51148232A Expired JPS5828924B2 (en) | 1976-12-08 | 1976-12-08 | automatic gain control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5828924B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5516538A (en) * | 1978-07-20 | 1980-02-05 | Nec Corp | Automatic level regulator circuit |
JPS55142243U (en) * | 1979-03-30 | 1980-10-11 | ||
JPS5820017A (en) * | 1981-07-30 | 1983-02-05 | Victor Co Of Japan Ltd | Automatic gain controlling circuit |
JPS59153313A (en) * | 1983-02-22 | 1984-09-01 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
JPS61239708A (en) * | 1985-04-16 | 1986-10-25 | Yaesu Musen Co Ltd | Alc circuit |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49108344U (en) * | 1973-01-12 | 1974-09-17 |
-
1976
- 1976-12-08 JP JP51148232A patent/JPS5828924B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5372441A (en) | 1978-06-27 |
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