JPS5828833A - Preparing flat surface - Google Patents

Preparing flat surface

Info

Publication number
JPS5828833A
JPS5828833A JP12622481A JP12622481A JPS5828833A JP S5828833 A JPS5828833 A JP S5828833A JP 12622481 A JP12622481 A JP 12622481A JP 12622481 A JP12622481 A JP 12622481A JP S5828833 A JPS5828833 A JP S5828833A
Authority
JP
Japan
Prior art keywords
resist
silicon
mask
silicon oxide
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12622481A
Other languages
Japanese (ja)
Inventor
Toshimoto Kodaira
小平 寿源
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP12622481A priority Critical patent/JPS5828833A/en
Publication of JPS5828833A publication Critical patent/JPS5828833A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To eliminate concave or convex on the glass substrate surface having been subjected to patterning by filling only the concaves of level different region with the silicon oxide film through the exposure with the polycrystal silicon which causes concave and convex used as the mask. CONSTITUTION:The desired polycrystal silicon pattern 5 is formed on the surface of glass substrate 4, and moreover the silicon oxide 6 in the same thickness as said polycrystalline silicon is formed on the entire surface in order to fill the convex where there is no polycrystal silicon. Then, the negative resist 7 is coated on the entire surface and is subjected to the irradiation of ultra-violet ray in order to expose this negative resist from the rear side of glass plate. In this case, the polycrystal silicon 5 is used as the mask for light beam and therefore the light beam passes only the region where the polycrystal silicon does not exist, exposing the resist 7. Then, an element is dipped into the resist developer and thereby unexposed resist (b) is removed completely and the silicon oxide is etched with the remaining resist (a) used as the mask. Thereby, only the silicon oxide formed on the polycrystalline silicon 5 is removed.

Description

【発明の詳細な説明】 本発明に薄膜のバターニングによって生ずる。[Detailed description of the invention] The present invention is produced by patterning a thin film.

凹凸を効果的な蕗光力法によって平坦化する方法に関す
るものである。
The present invention relates to a method for flattening unevenness using an effective Fukiko force method.

沿晶表示装((′4に、現在平面f〜り表示装置−S7
の主流を占めるもので矛)す、又技術的にも′f」もC
41純なセグメント表示方式から、大表示容+、4の為
のマ) IJックスアレ一方−氏(F−飛躍的な発展s
ニジ、さらに目表示品)哲向士の為に、液晶の1’、!
 食は10ミク[1ンメートル以下全棉敗してい2)。
Crystalline display device (('4, current plane f~ display device-S7
Technically, 'f' is also C.
41 From pure segment display method to large display capacity +, Ma for 4) IJ xare on the other hand (F- dramatic development
Niji, and more eye display items) For the Tetsuko, the LCD 1',!
The eclipse was 10 miku [everything under 1 m2 was defeated].

このA・Vに薄い液晶層を用いる場合、81晶をはさむ
二枚のガラス板の表面の凹凸(1合びしく制限さtl−
なげ?+、 +(J:ならない。
When using a thin liquid crystal layer for this A/V, the unevenness of the surface of the two glass plates sandwiching the 81 crystal (1.
Nage? +, + (J: Not.

特にアクティブマトリックスアレ一方式による場合、液
1m忙はさむ二枚のカラス柳のうちの一方の表面土嚢ト
ランジスター等を用いπ71、リツクスアレーを惰I反
しなげnにfならない。この時配仰部利及びトランジス
タ一部側として例えば多結晶シリコン薄膜、アルミニュ
ーム薄1トキ等を用い、さらにこれらの薄1iQのパタ
ーニング紮イjなう。この為第1回に示さnる様にカラ
スツ(板表面士に必ず凹凸が牛する。つ1り第1図のV
/1117cおいてげガラス板1の表白土に多結晶シリ
コン2及び−γルミニュームらがバターニングされてい
るが、こ才LI−)の膜厚は通常、多結晶シリコン2が
6000〜5000オングストローム、アルミニューム
75+5000〜10000オングストロームであって
、2図かられかる様にこの膜厚がそのまま段差の大きさ
になる。こ′rLを用いて、液晶パネルを構成する場合
、このガラス板と他のガラス板とを平行に対向させその
間に液晶を封入するので、液晶層の厚みに場所により多
結晶シリコン及びアルミニュームの膜厚分だけ異なる結
果となる。涌晶層の平均厚みを例えば5ミクロンメート
ルとした場合、薄膜の厚みは最大1ミクロンメートルが
考えられ、このノ易自、液晶層の厚みのバラツキは20
パーセントにもなり、従って沿晶が点燈した場合の色む
らはけなはだしく、表示品質に4夕めて低いものとなる
In particular, in the case of a one-type active matrix array, a sandbag transistor or the like is used on one surface of two crows with 1 m of liquid interposed between them, and the array is π71. At this time, for example, polycrystalline silicon thin film, aluminum thin film, etc. are used as the substrate and transistor part side, and these thin films are patterned. For this reason, as shown in Part 1, there will always be unevenness on the surface of the board.
/1117c Polycrystalline silicon 2 and -γ luminium are patterned on the white surface of the glass plate 1, but the film thickness of the polycrystalline silicon 2 is usually 6000 to 5000 angstroms. The film thickness is aluminum 75+5,000 to 10,000 angstroms, and as can be seen from FIG. 2, this film thickness directly becomes the size of the step. When constructing a liquid crystal panel using this glass plate, this glass plate and another glass plate are faced in parallel and the liquid crystal is sealed between them, so polycrystalline silicon and aluminum are added to the thickness of the liquid crystal layer depending on the location. The result differs by the film thickness. For example, if the average thickness of the liquid crystal layer is 5 micrometers, the maximum thickness of the thin film can be considered to be 1 micrometer, and the variation in the thickness of the liquid crystal layer is 20
%, and therefore, when the crystalline light is turned on, the color unevenness is remarkable, and the display quality deteriorates.

本発明は以−トの欠点を改良すべくなさ′n′f?:、
ものであって、俸めて効果的な露光方法を用いるル1に
より、段差の四部のみ全シリコン酸化膜で埋めパターン
を施したガラス基板表面上の凹凸を無くするものである
The present invention aims to improve the above drawbacks. :,
In this method, only four parts of the step are filled with a silicon oxide film to eliminate the unevenness on the surface of the patterned glass substrate by using a highly effective exposure method.

以下図面によって本発明の詳細な説明する。The present invention will be explained in detail below with reference to the drawings.

第2図は本発明によりガラス基板表面に形成し1ζ薄I
I’:&パターンにより生じ1(凹凸を1べて平1日化
する方θSの1例ケその工程1111’iに示しtもの
−(゛ある。
Figure 2 shows a 1ζ thin I formed on the surface of a glass substrate according to the present invention.
I': & An example of a method θS for converting unevenness into one day is shown in the process 1111'i.

耳j2i利(a)で(−rガラス基(Iし4の及「11
1+に所パ?〕の多結+ti’+ ’/ ’Iコンパタ
ーン5が形成前ねてb・す、きらf/j 。
(a) (-r glass group (I and 4 and ``11
Is it 1+? ]'s multi-connection +ti'+'/'I con pattern 5 is formed before b・su, kira f/j.

多結情シリコンの無い凹j%ン711(! lhるべく
、゛啓多結晶シリコンと回じ1[第11)の酸化シリコ
ン6を前哨1全簡にわたって形1’、% Lπ時の哉]
kの断面I′iI!竜金示したものである。次VC第2
トスl (b)の土中((ネー/jレー゛ンスト7全全
面vc檗布[7、ツノラス板のり而↓りこのネガレジス
トを沼fすへ<、紫外Tを照17;1−4−る。この場
合、多結晶シリコン5ケ光のマスク(」とシて月1い、
多結晶シリコンの力1(い′頑)或のみケ光が通過して
、レジスト7をL落光′1−る。従って、図中レジスト
7のイで示す頭載のみ1轄光さ几、bで示した領域に未
露光のn壕である。次にレゾスト現像液に浸して未露光
のレジストロをすべて除去し、残ったレジストイ4τマ
スクとして、酸化シリコン6全エツチングすると、多結
Vシリコン5の十に形成されている酸化シリコンのみが
除去される。酸化シリコン乙のエツチング後残ったレジ
ス[・を除去すると、ガラス基板の断面形状に第2図(
c)K示す様になり表面の凹凸にいたるところで解消し
平面となる。結局凹凸の原[)4となっている多結晶シ
リコンをマスクとして露光を行なうので、この多結晶シ
リコンパターンと、四部を埋める酸化シリコンパターン
が完全に整合する為に、表面の平面度は極めて優れたも
のとなる。埋土の様に本発明によれば、ガラスのごとき
透明な基板上に薄膜パターンを構成して生ずる凹凸は、
基板の透明性により基へ裏面より露光し、′Nj、膜を
マスクとして用いる事により凹部を完全に埋める事が出
来、極めて優れた平坦を旬る事が可能である。上記実施
例で吊?明した薄+1ψ5げ多結晶シリコンであるがこ
1にアルミニューム等の金属ニもちろん、不透明及び半
透明な薄膜すべてに応用可能であり、又凹部を埋める部
側は酸化シリコンのごとき透明側斜でなければならない
。さらにこの技術の応用に表面の平坦化のみでなく、二
種類の部材を合せ誤差無くパターニングする事にも応用
可能である。
Concave 711 without polycrystalline silicon (! In order to make polycrystalline silicon and silicon oxide 6 of turn 1 [11th] in shape 1',% Lπ time)
Cross section I'iI of k! This is what Ryukin showed. Next VC 2nd
Toss l (b) in the soil ((N/j Raynst 7 entire surface VC wooden cloth [7, glue the horn board ↓ Riko's negative resist to the swamp f<, shine ultraviolet T 17; 1-4 In this case, the polycrystalline silicon 5 light mask ("
Only a small amount of light passes through the polycrystalline silicon and falls onto the resist 7. Accordingly, in the figure, only one area of the head of the resist 7 indicated by A is exposed, and n unexposed grooves are formed in the area indicated by b. Next, all unexposed resists are removed by dipping in a resist developer, and the remaining resist toy 4τ is used as a mask to etch all of the silicon oxide 6. Only the silicon oxide formed on the multi-crystalline V silicon 5 is removed. . After etching the silicon oxide layer B, the remaining resist [.
c) As shown in K, the unevenness of the surface disappears everywhere and becomes flat. In the end, exposure is performed using polycrystalline silicon, which is the source of unevenness [4], as a mask, so this polycrystalline silicon pattern and the silicon oxide pattern that fills the four parts match perfectly, resulting in extremely high surface flatness. It becomes something. According to the present invention, like buried soil, the unevenness caused by configuring a thin film pattern on a transparent substrate such as glass,
Due to the transparency of the substrate, it is possible to completely fill the recesses by exposing the base to light from the back side and using the 'Nj film as a mask, making it possible to achieve extremely excellent flatness. Hanging in the above example? Although it is a thin +1ψ5 polycrystalline silicon as described above, it can be applied to all kinds of opaque and semi-transparent thin films, as well as metals such as aluminum. There must be. Furthermore, this technique can be applied not only to surface flattening, but also to patterning two types of members without alignment errors.

−5= 4 図面の!I貞Ipな1悦明 君1図に従来における表面の凹凸11う状を一6L7ζ
ガラスW阪の1例を示す1析面図である。又第2図(a
、)〜(c)に本発明てより表面の凹凸形状を無くした
カラス基1に全製櫓する方/んの1例を・トした断面図
である。
-5= 4 Drawings! The conventional surface unevenness 11 is 16L7ζ
FIG. 1 is an analytical view showing an example of glass W-shaped glass. Also, Figure 2 (a
, ) to (c) are cross-sectional views showing an example of a method for completely manufacturing a turret on a crow base 1 with no uneven surface shape according to the present invention.

+、A・・・ガラス 2.5・・・多債品シリコン 3・・・アルミニューム 6・・・酸化シリコン 7・・・レジスト 以   上 出願人 株式会社諏訪哨工合 代111i人 弁理士最十  務  6−+, A...Glass 2.5...Multi-bond silicon 3...Aluminum 6...Silicon oxide 7...Resist that's all Applicant: Suwa Tokogo Co., Ltd. 111 people, 10th number of patent attorneys 6-

Claims (1)

【特許請求の範囲】[Claims] 透明基板上に、不透明文(1半透明薄膜を形成して、該
不透明文に半透明薄膜をバターニングして生ずる該薄膜
の有無による前記透明基板土の凹凸を、該凹凸面上へ凹
部を埋める部月及びネカ型レジストを形成し、前言ピ不
透明又は半透明薄膜をマスクとして、前記透明基板の裏
面より露光し、前記不透明又は半透明薄膜上の未露光な
前記レジストを現像除去し、露出した、@記凹九を埋め
る部側ヲエッチング除去する墨によって反す事全特徴と
する表面平坦化方法。
An opaque pattern (1 semi-transparent thin film is formed on the transparent substrate, and the unevenness of the transparent substrate soil caused by the presence or absence of the thin film by patterning the semi-transparent thin film on the opaque pattern is formed by forming depressions on the uneven surface. Form a fill-in and negative type resist, expose to light from the back side of the transparent substrate using the opaque or semi-transparent thin film as a mask, develop and remove the unexposed resist on the opaque or semi-transparent thin film, and expose. The surface flattening method is characterized by etching away the side of the part where the grooves are filled with ink.
JP12622481A 1981-08-12 1981-08-12 Preparing flat surface Pending JPS5828833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12622481A JPS5828833A (en) 1981-08-12 1981-08-12 Preparing flat surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12622481A JPS5828833A (en) 1981-08-12 1981-08-12 Preparing flat surface

Publications (1)

Publication Number Publication Date
JPS5828833A true JPS5828833A (en) 1983-02-19

Family

ID=14929820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12622481A Pending JPS5828833A (en) 1981-08-12 1981-08-12 Preparing flat surface

Country Status (1)

Country Link
JP (1) JPS5828833A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01165127A (en) * 1987-12-22 1989-06-29 Nippon Telegr & Teleph Corp <Ntt> Method of flattening surface
US9054042B2 (en) 2011-03-30 2015-06-09 Cambridge Display Technology Limited Surface planarisation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140767A (en) * 1974-10-03 1976-04-05 Fujitsu Ltd Handotaisochi no seizohoho

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5140767A (en) * 1974-10-03 1976-04-05 Fujitsu Ltd Handotaisochi no seizohoho

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01165127A (en) * 1987-12-22 1989-06-29 Nippon Telegr & Teleph Corp <Ntt> Method of flattening surface
US9054042B2 (en) 2011-03-30 2015-06-09 Cambridge Display Technology Limited Surface planarisation

Similar Documents

Publication Publication Date Title
US7361285B2 (en) Method for fabricating cliche and method for forming pattern using the same
JPH03246524A (en) Liquid crystal display element
WO2004075232A1 (en) Original form for partition transfer intaglio and method for forming partitions of plasma display panel using the original form
JPH0433097B2 (en)
JPS5828833A (en) Preparing flat surface
KR940012007A (en) Manufacturing method of light scattering type liquid crystal display device
JPS60235426A (en) Manufacture of semiconductor integrated circuit device
JP2000314894A (en) Device structure for liquid crystal display equipped with alignment post and optical interference layer, and its production
JPS561016A (en) Production of liquid crystal display device
JPH06105678B2 (en) Method for manufacturing semiconductor device
JP3282207B2 (en) Transmission type phase shift mask and method of manufacturing the same
JPS614233A (en) Etching method of transparent electrically conductive film
JPS644662B2 (en)
JPS62229151A (en) Preparation of pattern mask
JPH01296534A (en) Manufacture of gas discharge panel
JP2780265B2 (en) Pattern formation method
KR100212719B1 (en) Method for formation of thin film
KR950009322A (en) How to form a functional coating
JPH063813B2 (en) Method of manufacturing thin film transistor
JPS61156771A (en) Manufacture of thin film semiconductor device
JPS61195589A (en) Thin film el element
KR950015584A (en) Manufacturing Method of Semiconductor Device
JPH06301053A (en) Production of liquid crystal display device
JPS5914677A (en) Manufacture of thin film transistor
JPH01169452A (en) Intaglio printing for forming printed circuit pattern and production thereof as well as printed circuit pattern forming method