JPS5827426A - Pulse voltage generating circuit - Google Patents

Abstract

PURPOSE:To eliminate losses for synthesizing a bias voltage and a pulse voltage, by constituting a pulse voltage generating circuit and a bias voltage generating citcuit with one circuit. CONSTITUTION:When a bias voltage controlling signal PB is inputted, a power supply voltage VBH is divided at a dividing tatio controlling citcuit 73 and a bias voltage VBB is generated. At the period when the bias voltage controlling signal PB is inputted, if a pulse voltage controlling signal PH is inputted, the pulse voltage VBH is generated at a dividing ratio controlling circuit 74. In this case, since the power supply voltage is VBH, the voltage dividing ratio is set to 1. Thus, since a superimposing voltage between the bias and pulse voltages is outputted from an output terminal 77 of a pulse voltage generating circuit 70, the losses for synthesizing these two voltages can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for controlling a pulse voltage using a PNPN switch element, and to a circuit configuration for applying a bias voltage to the PNPN switch element.

Generally, a device using a piezoelectric element is driven by a nocillus-like voltage. For example, a piezoelectric vibrator used in an ultrasonic cross-sectional imaging device or an inkjet printer head using a piezoelectric element is driven by applying a pulse voltage.

As a method of applying pulse voltage to these piezoelectric elements, there is a method of driving one piezoelectric element by providing one pulse voltage generation circuit, but if there are many piezoelectric elements, the pulse voltage generation circuit also needs to be increased by the number of piezoelectric elements. There are many drawbacks depending on the situation. Therefore, a method has been developed that uses a switch or the like to switch the pulse voltage generating circuit of the 11-unit.

When a PNPN switch element is used as a changeover switch in this method, it is necessary to apply a bias voltage to the PNPN switch element to operate it in order to prevent distortion of the voltage waveform during conduction.

FIG. 1 shows an example in which a PNPN switch element switches all pulse voltages and drives a plurality of piezoelectric elements.

In FIG. 1, 10 is a plurality of pressure forming elements 11 arranged in an array.
,12. It is an array of groups.

20'd, PNPN, z, ear F-element 21, 22.
-, a switch array consisting of piezoelectric elements 11, 1
2°... are connected in series, one each.

30 is a circuit that generates a pulse voltage VH and a control signal P)l
Generates a pulse voltage according to the Pulse voltage generation circuit 3
0 is composed of an amplification transistor 31 and buffer transistors 32 and 33, for example. Note that the peak value of the pulse voltage is set by the power supply voltage VBH.

40 is a PNPN switch element 21, 22 .・・・・・・
・This is a DC bias voltage generation circuit. As an example of this bias voltage generation circuit 40, transistors 41, 42, . .

43. That is, the bias voltage value is set by the source voltage Vaa value and generated by the control signal Pa. Note that the diode 44 is connected to the pulse voltage VH.
This is inserted so that it will not be applied to the bias pressure generation circuit when this occurs.

50 is a PNPN switch element 21, 22 .・・・・・・
Control signals G, , G2.・・・・・・
・This is the generation circuit.

60 is a PNPN switch element 21, 22 .・・・・・・
It is a bias load resistance of a DC component when a bias voltage v8 is applied from the bias voltage generation circuit 40 to the piezoelectric elements 11, 12, . . . and is connected in parallel with each other.

Note that 34 is a bypass capacitor for supplying the pulse voltage from the pulse voltage generation circuit 30, and 45 is a resistor for limiting the bias current from the bias voltage generation circuit 40.

With the above circuit configuration, a pulse voltage can be applied to a plurality of piezoelectric elements. This operation will be explained using the operation time sequence shown in FIG.

This causes the piezoelectric element 1 to synchronize with the reference clock pulse CP.
1,12. . . . An example is shown in which the pulse voltage Vp is applied one after another. The bias voltage generation circuit 40 receives P in synchronization with the reference clock pulse CP1'.
A control pulse indicated by a is input.

Therefore, its output has a bias voltage V shown in FIG.
a is generated. In this case, period t+ is a period in which bias voltage Va is generated, and period t2 is an OFF period.

Further, a control signal PH is input to the pulse voltage generating circuit 3o, and a pulse voltage V)I shown in FIG. 2 is generated at the output. The pulse voltage VH is controlled by the input control signal PH so that it is generated only during the period t3, in the middle of the period t1 in which the bias voltage v1 is generated.

Therefore, the PNPN switch elements 21, 22...
A voltage waveform VP in which a bias voltage Vm and a pulse voltage Vn shown in FIG. 2 are superimposed is applied to the common terminal of . Here, the control signals G+, G2, etc. of the PNPN switch elements 21, 22, etc. are caused by the first reference pulse, but G2 is caused by the second reference pulse, , and so on, and the PNPN switch elements 21, 22 . The piezoelectric elements 11, 12 . . . become conductive one after another.・Old... The pulse voltage waveforms Vpl, Vp2, . . . shown in FIG. 2 are sequentially applied.

In this way, the piezoelectric elements 11, 12 . . . . in series with PNPN switch elements 21, 22 . The piezoelectric element can be operated by connecting . . . and applying a signal (Vp) obtained by superimposing the pulse voltage Vot on the bias voltage Va.

However, in general, a bias voltage value Vaa of ten or more V is required, and a pulse voltage value Vas for operating the piezoelectric element 10 requires a high voltage of 2 to 300 V. For this purpose, two power supplies are required: power supply voltage VIIB for the bias voltage generation circuit and power supply voltage VBH for the pulse voltage generation circuit. Furthermore, when the piezoelectric element is driven by a PNPN switch element, there is a drawback that there are two circuits, the pulse voltage generation circuit 30 and the bias voltage generation circuit 40. Therefore, pulse voltage VH and bias voltage V! A resistor 45, a capacitor 34, and the like are inserted to combine the I and I, and there is a problem of loss due to voltage drop caused by these elements.

An object of the present invention is to configure a pulse voltage generation circuit and a bias voltage generation circuit into one circuit, use a single four sources, take out the terminals for outputting the pulse voltage and the bias voltage from the same terminal, and It is an object of the present invention to provide a circuit that completely reduces the loss caused by the loss.

The feature of the present invention is that the ratio of the resistance component d is adjusted by the signal Po for controlling the pulse voltage and the signal 'PB for controlling the bias voltage, and the circuit configuration is such that the bias voltage and the pulse voltage can be extracted from the same output. be.

The present invention will be explained in detail below using the figures.

FIG. 3 shows the basic configuration of a pulse bottom pressure generation circuit 700 according to the present invention.

In FIG. 3, 71 is an output buffer circuit and output terminal 7
7 outputs a pulse voltage Vp. A voltage dividing circuit 72 divides the voltage Vao of the power supply terminal 78. 73.74
1 is a circuit for controlling the division ratio of the voltage dividing circuit 72, the latter is provided for bias voltage control, and the latter is provided for pulse pressure forming control.

Reference numerals 75 and 76 are input terminals of the division ratio control circuits 73 and 74, into which the bias voltage control signal Pa and the pulse voltage signal PH are input.

The operation is similar to the time sequence shown in FIG. 2, and when the bias voltage control signal Pa is input, the division ratio control circuit 7
3 to divide the power supply voltage BH (il-) to generate the bias voltage Vaa.Next, during the period 11 during which the bias voltage control signal Pa is input, when the pulse wake-up pressure control signal Po is input, A pulse voltage VaHe is generated by the ratio control circuit 74. In this case, the power supply voltage is
Therefore, the voltage division ratio is set to 1. In this way, the superimposed d pressure of the bias voltage and the pulse voltage is output from the output terminal 77 of the pulse voltage generation circuit 70, and the loss due to synthesis, which was a conventional problem, or the problem of two acid sources, two circuit configurations, etc. It is now possible to eliminate shortcomings.

FIG. 4 shows an example of a specific circuit. In FIG. 4, parts with the same symbols as in FIG. 3 indicate the same parts as in FIG. 3. The output buffer circuit 71 is constituted by a transistor 101 as a Siemitter follower circuit ft. (The voltage dividing circuit 72 includes a transistor 102 and a transistor 103.
It operates as an i-switch, and the division ratio is adjusted by resistors 201 and 202. For example, when generating the bias voltage Vaa, the transistor 102 is turned on and the power supply voltage VIHt is applied to the resistors 201 and 202 connected in series. Here, the bias voltage value via is expressed by the following equation (1), and the values of the n1 resistors 201 and 202 are set thereby.

However, in equation (1), Ro is the resistance value of the resistor 201, R is the resistance value of the resistor 202, and the base-emitter voltage Vag of the transistor 1010 is omitted.

In this way, by setting the division ratio of the resistors 201 and 202, an arbitrary VIB value can be set. Next, when generating a pulse voltage, the transistor 103 is turned on and the power supply voltage vIIB is applied to the resistor 202.

At this time, the same value as the "power supply voltage vl)I" is obtained as the pulse voltage value.

The division ratio control circuits 73 and 74 are transistors 104°10
5 to control the switching transistors 102j to 103 of the voltage dividing circuit 72. That is, the input signal P is input to the input terminal 75 of the division ratio control circuit 73.
When “H” level is inserted as a, the transistor 10
4 is conductive, and the transistor 10 of the peak voltage component key 11 circuit 72
2 is also conductive. Therefore, the output voltage of the buffer circuit 71 is generated according to equation α).

In addition, an input signal P is input to the input terminal 76 of the division ratio control circuit 74.
When the "H" level is inserted as H, the transistor 10
In this case, the output voltage Vp of the buffer circuit 71 has the amplitude of the power supply voltage VIIH.

Two (or generally more than one) voltage divider circuits like this
It is desirable to generate pulse voltages having different output widths from the same buffer circuit output by controlling the division ratio control circuit.

FIG. 5 shows another specific embodiment of the voltage dividing circuit 72 shown in FIG. 3. In FIG. A certain pressure division ratio is resistor 201,2
02, and its operation is determined by transistors 102,
This is done by turning on and off 103.

When generating a bias voltage, an ON signal (minute g1 in FIG. 4) is applied to the input terminal 72-2 of the voltage divider circuit 72 for ratio control ll.
11 (signal from circuit 73) is input to transistor 102.
conduction. Further, when generating a pulse voltage, it is necessary to simultaneously input an ON signal to the input terminals 72-2 and 72-1 to make the transistors 102 and 103 conductive. Fourth
The difference between the voltage dividing circuit 72 shown in the figure and that shown in FIG. can do. The feature of the embodiment shown in FIG. 5 is that the circuit structure is such that only a pulse voltage is not generated when no bias voltage is generated. In other words, in the piezoelectric element drive circuit using the PNPN switch element shown in Figure 1, it is necessary to apply a pulse voltage after reducing the bias voltage, so if a bias acid ratio is not applied, a pulse voltage will be generated. I try not to do that.

Note that the present invention is not limited to the specific embodiments described above, but also includes various circuit configurations that perform the same type of operation.

As described above, the present invention is effective in obtaining a pulse voltage generating circuit with reduced loss and a simplified circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is an example of a conventional pulse voltage generation circuit for driving a piezoelectric element, FIG. 2 is a time sequence for explaining the circuit operation of FIG. 1, and FIG. 3 is a block configuration of a pulse voltage generation circuit according to the present invention. FIG. 4 is a diagram showing a specific embodiment of the voltage dividing circuit shown in FIG. 3, and FIG. 5 is a diagram showing another specific embodiment of the voltage dividing circuit. 70... Pulse voltage generation circuit, 71... Output buffer circuit, 72... Voltage division circuit, 73... Bias voltage division ratio control circuit, 74... Pulse voltage division circuit (12) 1st Figure 0 -138 ~ 2nd port VF6-m-'' 111 30 yen, Figure 4 Figure 5 Figure 8

Claims (1)

[Claims] 1. During the bias voltage generation period, the pulse voltage generation circuit generates a high voltage pulse voltage superimposed on the bias voltage.
It is equipped with a voltage division circuit that divides at the above division ratio, and two or more division ratio control circuits whose outputs are connected to the inputs of the voltage division circuit and which select the division ratio of the voltage division circuit, and one division ratio control circuit. During a period in which the bias voltage is generated by the voltage divider circuit, another division ratio control circuit is operated to generate the pulse voltage superimposed on the bias voltage by the voltage divider circuit. Pulse voltage generation circuit.