JPH06138848A - Driving device of liquid crystal display panel and liquid crystal display device using the driving device - Google Patents

Abstract

PURPOSE:To realize a multi-gradation display with a small number of set voltages as less as possible and then to improve the performance of the liquid crystal display device with respect to technology which drives an active matrix type liquid crystal display panel on a digital system. CONSTITUTION:The device is equipped with an arithmetic part 1 which receives 1st and 2nd reference voltages 2 and 3 and calculates N kind of voltages, a selection part 6 which is initialized with a line synchronizing signal 5 and selects and outputs the 1st or 2nd reference voltage when inputting the signal 5 or the output voltage 8 of the arithmetic part when not, and a latch part 7 which holds the voltage 9 selected by the selection part for a certain period in response to an arithmetic synchronizing signal 4 and outputs the held voltage as the drive voltage 10 of a data line; and the drive voltage is inputted to the arithmetic part 1 in response to the line synchronizing signal 5 and N kind of voltages are calculated and outputted in the form of staircase waveforms in response to the arithmetic synchronizing signal 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, it relates to a technique for driving an active matrix type liquid crystal display panel by a digital type. With the recent reduction in power consumption of computers, liquid crystal display devices are also required to have low power consumption, and digital systems have become the mainstream.
In connection with this, there is a strong demand for multi-color display (that is, multi-gradation display), and it is required to develop a digital multi-gradation display method.

[0002]

2. Description of the Related Art A method of driving a liquid crystal display panel is roughly classified into an analog method and a digital method. The analog method is a method of directly amplifying an analog video signal and applying it to the liquid crystal, while the digital method is a method of selecting one from a plurality of set voltages and applying it to the liquid crystal.

The analog system has an advantage that full-color display is possible because an analog signal is handled as it is, but it has a drawback that power consumption is large because a large number of operational amplifiers are required. On the other hand, the digital method has an advantage that the power consumption is relatively small, but the number of voltages that can be set is limited due to restrictions on the number of IC terminals and the number of selection analog switches used. There is a problem that there are few.

In the conventionally known digital drive device, the same number of voltages as the number of gradations is internally generated and supplied to the drive IC. For example, 8 * 8 * 8 = 512 colors are displayed by supplying eight types of voltages.

[0005]

As described above, in the conventional digital driving device, about 1 which is close to full color.
256 kinds of voltages are required to display 6.67 million colors, but due to increase in external circuits and restrictions on the number of IC terminals,
It was not possible to realize such multi-gradation display.

The present invention was created in view of the above problems in the prior art, and is of a digital type that can realize multi-gradation display with a set voltage number as small as possible and can contribute to improving the performance of a liquid crystal display device. An object of the present invention is to provide a driving device for a liquid crystal display panel.

[0007]

In order to solve the above problems, a liquid crystal display panel drive apparatus according to the present invention has a first reference voltage 2 and a second reference voltage as shown in the principle configuration diagram of FIG. A calculation unit 1 that receives a voltage 3 and calculates and outputs N kinds of voltages, and is initialized by a line synchronization signal 5, and when the line synchronization signal is input, the first or second reference voltage is selected and output. A selector 6 for selectively outputting the output voltage 8 of the arithmetic unit when the line synchronization signal is not input.
And a latch unit 7 that holds the voltage 9 selected by the selection unit in response to the operation synchronization signal 4 for a certain period and outputs the held voltage as a drive voltage 10 for the data line. In response to the line synchronization signal, the voltage is taken into the operation unit, and the N kinds of voltages are responded to the operation synchronization signal in the form of a stepped waveform (signals 9 and 1 in FIG. 2).
It is characterized in that the arithmetic output is made in (see 0, 8).

In this configuration, the arithmetic unit 1 appropriately performs arithmetic operations (addition, subtraction, etc.) between the first reference voltage 2 (V1) and the second reference voltage 3 (V2). At this time, the reference voltage 2,
One of 3 is taken in as an initial value of the operation performed by the operation unit 1, and the other is taken in as a maximum value or a minimum value of the operation performed in the operation unit 1. For example, if V1 <V2, when the reference voltage 2 (V1) is taken as the initial value, the reference voltage 3 (V2) defines the maximum value, and conversely, the reference voltage 3 (V2) is taken as the initial value. Then, the reference voltage 2 (V1) defines the minimum value.

Reference numeral 11 denotes an AC signal input from the outside, which is used as a control signal for designating the type of calculation. In a preferred embodiment of the present invention, the calculation unit 1 performs the following calculation according to the polarity of the alternating signal 11.
That is, V [n] = V1 + α × (V2-V1) × (n−1) ÷
(N-1) or V [n] = V2-α × (V2-V1) × (n-1) ÷
(N-1), where V [n] is the nth voltage of N types of voltage, V1
Is the first reference voltage, V2 is the second reference voltage (V2> V
1), n is an integer of 1 or more and N or less, and α is a positive real number. In connection with this, the selection unit 6
When the arithmetic unit 1 performs addition, either the output voltage 8 of the arithmetic unit or the first reference voltage 2 (V1) is selectively output, and when the arithmetic unit 1 performs subtraction, the arithmetic unit 1 Of the output voltage 8 or the second reference voltage 3 (V2).

[0010]

The operation timing chart of the apparatus of the present invention is shown in FIG. The illustrated example shows an operation mode in the case where the calculation unit 1 performs addition. First, when both the line synchronization signal 5 and the operation synchronization signal 4 are turned on (“H” level), the first reference voltage 2 (voltage V1) is selected by the selection unit 6, and this selection voltage is held in the latch unit 7. To be done. At this time, the output 10 of the latch unit 7 is returned to the arithmetic unit 1 and the second reference voltage 3
Calculation is performed with (voltage V2), and the calculation result is output as the output voltage 8. The calculation is, for example, ΔV =
If (V2-V1) ÷ (N-1), then ΔV is added.

Next, the line sync signal 5 is turned off ("L").
Level), this time the output voltage 8 of this computing unit 1
Is selected by the selection unit 6. Then, the next operation synchronization signal 4
Is input, this time, the output of the calculation unit 1, namely (V
1 + ΔV) is held in the latch unit 7. Similarly, when the next operation synchronization signal 4 is input, (V1
A voltage corresponding to + 2 × ΔV) is held, and thereafter, every time the operation synchronization signal 4 is input, the output 10 of the latch unit continues to increase or decrease (in the illustrated example, increase) in a stepwise manner. This state continues until the line synchronization signal 5 is input again.

In this way, the two reference voltages 2 (V
1) and 3 (V2) have a stepwise waveform voltage (N kinds of voltages) from the output terminal of the latch unit 7 to drive voltage 1
Obtained as 0. Therefore, the liquid crystal display panel can be driven by taking in the voltage corresponding to the desired grayscale among the N types of voltage waveforms at an appropriate timing. That is, it is possible to realize multi-gradation display with a relatively small number of set voltages. This greatly contributes to improving the performance of the liquid crystal display device.

The maximum value of the voltage of the staircase waveform output from the latch section 7 should be the same potential as the second reference voltage 3 (V2), but actually there are variations in the component characteristics. Therefore, it is slightly displaced. Therefore, in a preferred embodiment of the present invention, the maximum value of the voltage of the staircase waveform output from the latch unit 7 is held and compared with the second reference voltage 3, the above ΔV is reduced so that this difference becomes small. Compensation means for adjusting the magnitude of is provided in the computing unit 1. As a result, it is possible to minimize variations in the voltage of the staircase waveform output from the latch unit 7.

Details of other structural features and operations of the present invention will be described with reference to the accompanying drawings using the embodiments described below.

[0015]

FIG. 3 shows the overall construction of a liquid crystal display panel driving device according to an embodiment of the present invention. Note that, in the following description, the same reference numerals as those shown in FIG. 1 represent the same components, and thus the description thereof will be omitted. In FIG. 3, a portion indicated by A corresponds to the driving device shown in FIG. 1, 12 is digital input data (that is, digitized image data), 13 is an input synchronization clock of the digital input data 12, 14-1 to 14-M are liquid crystal drive voltages supplied to the corresponding data lines, 15 is a counter for counting the operation synchronization signal 4, 1
Reference numeral 6 is a shift register responding to the data input synchronizing clock 13, and 17-1 to 17-M are circuit blocks which are activated by selection signals 24-1 to 24-M from the shift register 16 and drive corresponding data lines. Indicates.

Data line drive blocks 17-1 to 17
Each of -M includes a latch unit 18 that holds the digital input data 12 in response to corresponding selection signals 24-1 to 24-M from the shift register 16, an output of the latch unit and an output 23 of the counter 15. A comparison unit 19 for comparison, and a latch unit 21 for holding the output 10 (voltage of staircase waveform) of the drive device A in response to the output of the comparison unit (comparison result 20).
And a latch unit 22 that holds the output of the latch unit 21 in response to the line synchronization signal 5 and outputs the liquid crystal drive voltages 14-1 to 14-M.

FIG. 4 shows an example of the configuration of the arithmetic unit 1 in the drive unit A. The illustrated example shows a circuit configuration when the arithmetic unit 1 performs addition and has a correction function. In the figure, the correction unit is an analog switch 31 that is turned on / off in response to the line synchronization signal 5.
And an analog switch 32 that turns on and off in response to a power-on reset signal 24, and a switch 31 or 3
A capacitor 33 for holding the drive voltage 10 or the second reference voltage 3 (V2) from the latch unit 7 input via the input terminal 2 and the voltage held by the capacitor are input to the non-inverting input terminal and a voltage follower. 34 that functions as a comparator, and an operational amplifier 35 that inputs the reference voltage 3 (V2) to the non-inverting input terminal and that functions as a comparator.
And a resistor 36 (resistance value R3) connected between the output terminal of the operational amplifier 34 and the inverting input terminal of the operational amplifier 35, and a resistor 37 (resistor connected between the output terminal and the inverting input terminal of the operational amplifier 35). With the values R3).

On the other hand, the adder unit divides the voltage between the output voltage of the operational amplifier 35 and the first reference voltage 2 (V1) by the resistor 3
8 (resistance value (N−1) × R1) and resistor 39 (resistance value R1), and the operational amplifier 40 that inputs the divided voltage to the non-inverting input terminal and functions as a voltage follower.
And an operational amplifier 41 that inputs the reference voltage 2 (V1) to the non-inverting input terminal, an operational amplifier 42 that inputs the reference voltage 2 (V1) to the non-inverting input terminal, an output terminal of the operational amplifier 40, and an inverting input terminal of the operational amplifier 41. Resistor 43 connected between
(Resistance value R2), a resistor 44 (resistance value R2) connected between the input terminal of the driving voltage 10 from the latch section 7 and the inverting input terminal of the operational amplifier 41, the output terminal of the operational amplifier 41, and the inverting input terminal. Resistor 45 (resistance value R2) connected between
And a resistor 46 (resistance value R1) connected between the output terminal of the operational amplifier 41 and the inverting input terminal of the operational amplifier 42, and between the output terminal of the operational amplifier 42 (the output terminal of the output voltage 8) and the inverting input terminal. And the connected resistor 47 (resistance value R1). Operational amplifier 41 and resistors 43, 44 and 4
5 forms an adder circuit, and the operational amplifier 42 and the resistors 46 and 47 form an inverter circuit.

In the above configuration, when the power-on reset signal 24 is input, the operation of the arithmetic unit 1 is started and the switch 32 is turned on only once, whereby the reference voltage 3
(V2) is held in the capacitor 33. After that,
The switch 31 is turned on in response to the line synchronization signal 5, and the maximum value of the driving voltage 10 (voltage having a staircase waveform) from the latch unit 7 is held in the capacitor 33. This drive voltage 10
The maximum value of n is N = N calculated by the calculation unit 1.
Corresponds to the calculation result V [N]. The correction unit as a whole has a function of comparing the maximum value of the drive voltage 10 from the latch unit 7 with the reference voltage 3 (V2) by the comparator 35, and adjusting the magnitude of ΔV so that the difference becomes small. Have This adjustment is performed using the input resistor 36 of the comparator 35 and the feedback resistor 37 of its output voltage. On the other hand, the addition unit as a whole has an error voltage ΔV [= (V2-V1) ÷ (N-1)] and a drive voltage of 10
Are added by an adder circuit, and the addition result is output as an output voltage 8 through an inverter circuit.

In FIG. 4, RA and RB denote external variable resistors, which are voltage dividing resistors 38,
It is connected between the connection point of 39 and the input terminal of the reference voltage 2 (V1) or 3 (V2). Variable resistors RA, RB
It is possible to arbitrarily change the value of N described above by appropriately setting the resistance value of. FIG. 5 shows a configuration example of the selection unit 6 and the latch unit 7 in the drive device A.

In the figure, the selection unit 6 includes an inverter 50 that responds to the line synchronizing signal 5, an analog switch 51 that turns on and off in response to the output of the inverter, and an on switch that responds to the line synchronizing signal 5. And an analog switch 52 for turning off. Also, the latch unit 7 is an analog switch 5 that is turned on / off in response to the operation synchronization signal 4.
3, a capacitor 54 for holding the selection output voltage 9 of the selection unit 6 input through the switch 51 or 52 and the switch 53, and the voltage held by the capacitor is input to the non-inverting input terminal and used as a voltage follower. An operational amplifier 55 that functions, an inverter 56 that responds to the operation synchronization signal 4, an analog switch 57 that turns on / off in response to the output of the inverter, and an output voltage of the operational amplifier 55 that is input through the switch. It has a capacitor 58 and an operational amplifier 59 that inputs the voltage held by the capacitor to a non-inverting input terminal and functions as a voltage follower. This operational amplifier 59
The output of the latch section 7, that is, the drive voltage 10 is taken out from the output terminal of the.

In the above structure, when the line synchronizing signal 5 is at "H" level (on), the switch 52 is turned on and the reference voltage 2 (V1) is selectively output. On the contrary, when the line synchronization signal 5 is at "L" level (OFF), the output of the inverter 50 becomes "H" level, so that the switch 51 is turned on and the output voltage 8 of the arithmetic unit 1 is selectively output.
When the operation synchronization signal 4 is at the “H” level (ON), the switch 53 is turned on, the selected output voltage 9 input through the switch 51 or 52 is held in the capacitor 54, and the operation synchronization signal 4 is at the “L” level. When the level (OFF), the output of the inverter 56 becomes the “H” level, so the switch 57 is turned on, and the output voltage of the operational amplifier 55 is held in the capacitor 58. The held voltage is output as the drive voltage 10 through the voltage follower 59.

Next, a method of driving the liquid crystal display panel using the stepwise waveform voltage obtained by the device of FIG. 3 will be described with reference to the operation timing chart of FIG.
The example of FIG. 6 shows the operation timing when the data line drive block 17-1 is selected by the selection signal 24-1. In addition, P1 to P3 are line synchronization signals 5
Represents the cycle of.

First, in the first period P1, the digital input data 12 is latched in the latch section 18 in response to the input synchronizing clock 13. In the next second period P2, the output 23 obtained by counting the operation synchronization signal 4 by the counter 15 and the first
The comparison unit 19 compares the digital input data 12 latched in the period P1 of the above with the comparison unit 20, and based on the comparison result 20, the step-shaped waveform drive voltage 10 at the timing when the two coincide with each other is latched in the latch unit 21. In the next third cycle P3,
The analog voltage latched in the latch unit 21 is latched in the latch unit 22 in response to the line synchronization signal 5, and the voltage 14-1 latched in the latch unit 22 is used to drive the liquid crystal display panel.

In the above-mentioned embodiment, the resistors 36 and 37 having a fixed resistance value are used as the means for adjusting the magnitude of ΔV in the correction unit of the calculation unit 1. However, this is modified into, for example, FIG. As shown as an example, resistors 36a and 37a having variable resistance values may be used. Further, in the above-described embodiment, the voltage dividing resistor 3 is used as means for arbitrarily changing the value of N in the adding section of the calculating section 1.
Although 8, 39 and external variable resistors RA, RB are used, the means for changing the value of N is not limited to this.

For example, as shown as a modified example in FIG. 8, each resistor as the voltage dividing means may be configured to change its resistance value based on the switching signals C1 and C2. That is, each resistance unit 38a, 39a
The respective parallel-connected plurality of resistors R ₁ ~Rm, R
The value of N can be arbitrarily changed by the switch means SW1 and SW2 which selectively select the plurality of resistors by _{1 to} Rn and the switching signals C1 and C2.

Further, in the description of FIGS. 1 and 2 described above, the second
Although the reference voltage 3 (V2) of is set to be constant, this voltage 3 (V2
When 2) is changed periodically (for example, in synchronization with the line synchronization signal 5), the potential difference between the stages of the drive voltage having the stepwise waveform can be set arbitrarily. Therefore, γ correction can be performed using this function. However, in this case, it is necessary to apply a sawtooth voltage waveform.

Further, when the driver of this embodiment is constructed in the form of an IC and a plurality of driver ICs are used, each I
By changing the reference voltage for each C, it is possible to correct the variation in the output drive voltage of each IC. In addition, each of the reference voltages 2 (V1), 3 depending on the position on the liquid crystal display panel.
By appropriately changing (V2), it is possible to correct uneven brightness on the liquid crystal display panel.

Further, in the case of performing color display, by providing three sets of the driving device of this embodiment for each color of R (red), G (green) and B (blue), each halftone of each color is provided. Color correction can be performed.

[0030]

As described above, according to the present invention, a plurality of types can be obtained by appropriately performing voltage division and calculation (addition, subtraction, etc.) and correction from a set voltage (two reference voltages in the embodiment) that is as small as possible. It is possible to generate a voltage of, and thereby, it is possible to realize multi-gradation display by a digital method. This greatly contributes to improving the performance of the liquid crystal display device. Further, since various corrections such as γ correction can be easily performed, high quality display is possible.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a driving device of a liquid crystal display panel according to the present invention.

FIG. 2 is an operation timing chart of the apparatus of FIG.

FIG. 3 is an overall configuration diagram of a driving device of a liquid crystal display panel according to an embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a calculation unit in FIG.

5 is a circuit diagram showing a configuration example of a selection unit and a latch unit in FIG.

6 is an operation timing chart of the apparatus of FIG.

FIG. 7 is a diagram showing a modification of the correction unit in the arithmetic unit of FIG.

8 is a diagram showing a modified example of an addition unit in the arithmetic unit of FIG.

[Explanation of symbols]

 1 ... Operation part 2 ... 1st reference voltage (V1) 3 ... 2nd reference voltage (V2) 4 ... Operation synchronization signal 5 ... Line synchronization signal 6 ... Selection part 7 ... Latch part 8 ... Output voltage of operation part 9 Output voltage of selection unit 10 Drive voltage of data line (voltage of staircase waveform) 11 Control signal (AC signal) that specifies the type of calculation

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuhiko Kishida 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (14)

[Claims] 1. A digital drive device for driving a liquid crystal display panel by selecting any one of a plurality of types of voltages and supplying it to a corresponding data line as an image data voltage. An operation unit (1) that receives the voltage (2) and the second reference voltage (3) and calculates and outputs N kinds of voltages, and the line synchronization signal (5) is initialized and the line synchronization signal is input. A selection unit (6) that selectively outputs the first or second reference voltage when the line synchronization signal is not input, and outputs the output voltage (8) of the operation unit when the line synchronization signal is not input.
And the voltage (9) selected by the selector is used as the operation synchronization signal (4).
And a latch unit (7) for holding the held voltage for a certain period in response to the data line driving voltage (10), the driving voltage being held in response to the line synchronization signal. A driving device for a liquid crystal display panel, characterized in that the N kinds of voltages are fetched into an arithmetic unit and arithmetically output in the form of a stepwise waveform in response to the arithmetic synchronization signal. 2. The liquid crystal display panel drive device according to claim 1, wherein the arithmetic unit is a control signal (11) for designating an arithmetic type.
Based on the following calculation, V [n] = V1 + α × (V2-V1) × (n-1) ÷
(N-1) or V [n] = V2-α × (V2-V1) × (n-1) ÷
(N-1), where V [n] is the nth voltage of N kinds of voltages, V1 is the first reference voltage, V2 is the second reference voltage (V2> V1), and n is 1 or more and N or less. A driving device for a liquid crystal display panel, which is characterized by performing either one of an integer of α and a positive real number. 3. The liquid crystal display panel drive device according to claim 2, wherein the arithmetic unit temporarily holds the drive voltage from the latch unit, and the held drive voltage. Means (35) for comparing with the second reference voltage and means (38, 39; 38a,) for dividing the voltage based on the result of the comparison.
39a) and means (41, 43-) for adding the divided voltage to the drive voltage and further adding it to the first reference voltage.
45), and thereby the N kinds of voltages are arithmetically output in the form of a stepwise waveform, thereby driving the liquid crystal display panel. 4. The liquid crystal display panel drive device according to claim 3, wherein the arithmetic unit holds the arithmetic result V [N] when n = N and the magnitude of the voltage based on the result of the comparison. A driving device for a liquid crystal display panel, further comprising a correction means for adjusting the value of α so that 5. The liquid crystal display panel driving device according to claim 4, wherein the correction unit is a resistance unit (3) for input to the comparison unit.
6, 36a) and a resistance means (37, 37a) for feedback of the output voltage of the comparison means, a driving device for a liquid crystal display panel. 6. The liquid crystal display panel driving device according to claim 5, wherein the input resistance means and the feedback resistance means are resistors (36, 37) set to the same resistance value (R3), respectively. A drive device for a liquid crystal display panel, which comprises: 7. The liquid crystal display panel driving device according to claim 5, wherein the input resistance means and the feedback resistance means each have a variable resistance value (36a, 37a).
A drive device for a liquid crystal display panel, comprising: 8. The liquid crystal display panel drive device according to claim 4, wherein the voltage dividing means is a first resistance means (3) connected in series.
8.38a) and second resistance means (39, 39a), and the calculation unit calculates the value "/ (N-1)". 9. The liquid crystal display panel driving device according to claim 8, wherein the first resistance means (38) and the second resistance means (3).
9) further comprising a variable resistor (RA, RB) connected between the connection point and the input end of the first or second reference voltage, whereby the value of N can be arbitrarily changed A drive device for a liquid crystal display panel, characterized in that 10. The liquid crystal display panel driving device according to claim 8, wherein the first resistance means (38a) and the second resistance means (39a) are each a plurality of resistors (R) connected in parallel. _{1 to} Rm, R _{1 to} Rn) and switching signals (C1, C
According to 2), a switch means (SW1, SW2) for selectively selectively connecting the plurality of resistors is provided, whereby the value of N can be arbitrarily changed. Drive. 11. A liquid crystal display device using the liquid crystal display panel driving device according to claim 1, wherein at least one of the first and second reference voltages is periodically changed. A liquid crystal display device characterized by performing γ correction. 12. A liquid crystal display device using the drive device for a liquid crystal display panel according to claim 1, wherein the drive device for the liquid crystal display panel is configured in the form of an IC. A liquid crystal display device, wherein at least one of a first reference voltage and a second reference voltage is appropriately adjusted for each IC to correct variations in output drive voltage of the IC. 13. A liquid crystal display device using the driving device for a liquid crystal display panel according to claim 1, wherein the first and second liquid crystal display devices are arranged according to a position on the liquid crystal display panel.
A liquid crystal display device, characterized in that at least one of the reference voltages of (1) is appropriately changed to correct luminance unevenness on the liquid crystal display panel. 14. A liquid crystal display device using the drive device for a liquid crystal display panel according to claim 1, comprising three sets of the drive device for the liquid crystal display panel and providing three types of pixels. A liquid crystal display device characterized in that each set is operated correspondingly to correct chromaticity.