JPS5826671B2 - Teiden Atsudaio - Donoseizouhouhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a constant voltage diode.

Conventional methods for manufacturing constant voltage diodes include an alloying method in which a P-type conductivity type region is created by alloying aluminum wires or spheres on an N-type silicon substrate with a predetermined resistivity, and a PN junction is formed. is P by diffusion method or epitaxial method.
There is a method of forming an N junction.

However, in the alloy method, it is difficult to obtain a uniform PN junction surface with AI, and local breakdown tends to occur easily, and due to the difference in thermal expansion coefficient between Si and AlSi alloy layers, However, it has the disadvantage that cracks are likely to occur, resulting in a large reverse current and large variations in breakdown voltage.

On the other hand, with the diffusion method, a better PN junction can be obtained than with the alloy method, but due to the nature of diffusion, the concentration gradient of impurities near the PN junction cannot be made as steep as the alloy method, and the breakdown voltage is approximately 6V. It is extremely difficult to make the following.

However, the present invention provides a method for manufacturing a constant voltage diode that can produce a uniform PN junction with fewer defects than by the alloy method, and can even have a low breakdown voltage that cannot be obtained by diffusion. .

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

First, FIG. 1 shows an example of a pellet structure of a constant voltage diode manufactured by the method of the present invention.

In Figure 1, 1 is a low resistivity N-type silicon substrate, 2
3 is an oxide film, 3 is a P-type guard ring diffusion layer of a conductivity type opposite to that of the silicon substrate, 4 is a diffusion window that exposes a part of the guard ring diffusion layer, and 5 is a diffusion window and an oxide film on the outer periphery of the diffusion window. a P+ type amorphous or polycrystalline silicon layer deposited to cover the N-type silicon substrate 1; 7 a metal electrode deposited on the P+ layer 5;
Reference numeral 8 denotes a metal protrusion provided to cover the metal electrode 7.

FIG. 2 shows the manufacturing process of the pellet structure shown in FIG.

In FIG. 2, an oxide film 2 is formed on an N-type silicon substrate 1 by a normal thermal oxidation method, and a first annular diffusion window 2a is provided in the oxide film 2 by a photoetching method.

Highly concentrated boron is diffused to a predetermined depth through the diffusion window 2a to form a P-type guard ring diffusion layer 3 (FIG. 2a).

A photoresist film is deposited on the wafer and selectively etched to form a second diffusion window 4 exposing a part of the P-type guard ring diffusion layer 3 (FIG. 2b).

Next, the silicon substrate 1 is placed in a vapor phase growth apparatus 900.
The P+ type amorphous or polycrystalline silicon layer 5 is grown to a thickness of, for example, 1 to 3 microns by heating to a temperature of 0.degree. Cover it with.

At this time, simultaneously with the deposition of the P+ type amorphous or polycrystalline silicon layer 5, a shallow PN main junction 6 with a diffused layer is formed in the N type silicon substrate 1 (FIG. 2C).

The concentration gradient of impurities in the main PN junction 6 is very steep, and a uniform PN junction surface can be obtained.

Next, a photoresist film is deposited on the surface of the P+ type amorphous or polycrystalline silicon layer 5 of the wafer, and a P+ type amorphous or polycrystalline silicon layer is formed inside the diffusion window 4 and on the oxide film 2 on its outer periphery. 5 remains, and the other deposited films are selectively removed by a mixed acid etching solution.

It is very important to leave the inside of the diffusion window 4 and its outer periphery and remove the deposits from the other parts.
Since the P+ type amorphous or polycrystalline silicon layer 5 remaining on the oxide film 2 on the outer periphery of the P+ type amorphous or polycrystalline silicon layer 5 has an effect as a protective film and an electrode for the PN main junction 6, at least the P type guard ring diffusion layer 3
It is necessary to provide a diameter sufficiently larger than the outer diameter of the outer diameter.

Next, an electrode metal (for example, Au, Ag, etc.) is vapor-deposited on the surface of the P+ type amorphous or polycrystalline silicon layer 5 remaining inside the diffusion window 4 and on the oxide film 2 on its outer periphery to form a metal electrode 7. (Figure 2 d).

Here, a planar type constant voltage diode having a deep P-type guard ring diffusion layer 3 and a shallow PN main junction 6 is obtained.

In this constant voltage diode, the breakdown voltage of the PN main junction 6, which has a very shallow diffusion layer formed within the diffusion window 4, is lower than that of the P-type guard ring, and the breakdown voltage is lower than that of the P-type guard ring.
Since it occurs only inside the mold silicon substrate 1, the electric field under the oxide film 2 is weakened, and excellent electrical characteristics that are less susceptible to the effects of the bonding surface can be obtained.

It goes without saying that the factors that determine the breakdown voltage value of the constant voltage diode are the resistivity of the N-type silicon substrate 1 and the deposition temperature of the P+ type amorphous or polycrystalline silicon layer 5.

In addition, heat treatment after deposition of the P+ type amorphous or polycrystalline silicon layer 5 (for example, thermal oxidation at 1000° C. or higher and impurity diffusion) increases the breakdown voltage, which is the purpose of the present invention. This is not preferable for the production of constant voltage diodes.

Therefore, in the method of the present invention, heat treatment or the like must not be performed after the amorphous or polycrystalline silicon layer is deposited.

The above embodiments have been described in which a silicon substrate is N-type, a guard ring diffusion layer is provided, and an amorphous or polycrystalline silicon layer is provided with a P+ layer, but the present invention is also applicable to a P-type or N+ layer. It goes without saying that it is possible.

As explained above, the constant voltage diode manufactured according to the present invention is a planar type constant voltage diode with a guard ring structure, and the deposition temperature of the amorphous or polycrystalline silicon layer containing impurities is 900°C. Because the temperature is below 100 volts, a very steep impurity concentration gradient that could not be obtained by diffusion methods is formed, resulting in a low breakdown voltage (6V to IV).
is obtained.

In addition, compared to constant voltage diodes manufactured by the alloy method, the reverse current is smaller and electrical characteristics with sharper rise characteristics can be obtained.Furthermore, the variation in breakdown voltage is small, so manufacturing yields are increased and the characteristics are stable. It is easy to mass-produce highly reliable constant voltage diodes, and the manufacturing cost can therefore be greatly reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment of a pellet of a constant voltage diode made according to the present invention, and FIG. 2 is a sectional view showing a manufacturing process of the pellet shown in FIG. 1. In the figure, 1 is an N-type silicon substrate, 2 is an oxide film, and 2a is a first silicon substrate.
3 is a P-type guard ring diffusion layer, 4 is a second diffusion window, 5 is a P+ type amorphous or polycrystalline silicon layer, 6 is a PN main junction, 7 is a metal electrode, and 8 is a metal protrusion. shows.

Claims (1)

[Claims] 1. An annular guard ring diffusion layer of the opposite conductivity type is provided on a silicon substrate of either P type or N type conductivity type, and a part of the guard ring diffusion layer is exposed for diffusion of an insulating film. A method for manufacturing a constant voltage diode, comprising forming a window and depositing an amorphous or polycrystalline silicon layer covering the diffusion window and the insulating film to form a PN junction in the silicon substrate. .