JPS5826212B2 - delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay circuit having a capacitor charging circuit, and an object of the present invention is to make the delay time constant regardless of fluctuations in pulse input voltage and power supply voltage.

Figure 1 shows a conventional delay circuit, in which 1 is an input terminal;
2 is an output terminal, and 3 and 4 are DC power supply terminals.

5 is a capacitor, and the charging path of this capacitor is resistor 6,
It is composed of a diode 7.

8 is a transistor whose emitter terminal is connected to the capacitor 5 mentioned above.
The collector terminal is connected to the output terminal 2 at one end, and a reference voltage obtained by dividing the power supply voltage by a resistor 9.10 is applied to the base terminal.

When a square wave pulse as shown in the figure enters the input terminal 1, the capacitor 5 is charged in a stepwise manner, and the terminal voltage thereof increases.

At this time, the transistor 8 is reverse biased between its base and emitter, so it is in an off state and does not output a signal to the output terminal.

When the charging of the capacitor 5 progresses and the terminal voltage, that is, the emic voltage of the transistor 8 reaches the base voltage, that is, the reference voltage obtained by dividing the power supply voltage by the resistors 9 and 10, the transistor 8 emitters to the base voltage. Current flows and turns on.

Then, a signal appears at the output terminal, which becomes an output pulse synchronized with the input pulse.

The above is an explanation of the operation of the conventional example, and such a delay circuit is often used when obtaining a long delay time with a small capacitor.

However, since the reference voltage and input pulse are completely independent, for example, if the power supply voltage is constant, i.e.
When the reference voltage is constant and the peak value of the input pulse changes (
When various pulses as shown in FIG. 3 are input), the delay time, that is, the time from when the capacitor 5 starts to be charged until it reaches a predetermined reference voltage changes accordingly.

Conversely, even if the peak value of the input pulse is constant and the power supply voltage fluctuates and the reference voltage fluctuates, the delay time will fluctuate.

The present invention has been made in view of the drawbacks of the above-mentioned conventional example, and will be explained below based on FIG. 2.

FIG. 2 shows a delay circuit showing one embodiment of the present invention.
is a constant voltage diode connected to the power supply via a resistor 12 in order to absorb fluctuations in the power supply voltage and provide a constant reference voltage to the base of the transistor 8.

Further, a diode 13 is connected between the cathode terminal of the constant voltage diode 11 and the input terminal 1 in the direction shown in the figure.

Note that other parts are the same as those described in the conventional example and are given the same numbers.

In the above configuration, the basic operation is as explained in the conventional example, so it will not be explained here, but even if the power supply voltage fluctuates, the constant voltage at the base of the transistor 8 is maintained due to the function of the constant voltage diode 11. A reference voltage is provided.

Furthermore, even if various pulses as shown in FIG. 3 are input to the input terminal 1 and their peak values fluctuate, the diode 13 bypasses the voltage regulator diode 11 described above, so the upper part of the waveform changes. be cut.

Therefore, the capacitor 5 is charged by a charging pulse with a constant peak value (which is equal to the zener voltage of the voltage regulator diode) as shown in FIG. Since the voltage is applied to the emitter of transistor 8, the time it takes for transistor 8 to turn on, that is, the delay time, is always constant.

As explained above, the present invention has a configuration in which a reference voltage is made constant using a constant voltage diode, and the cathode terminal of this constant voltage diode and a part of the charging path are connected by a diode. This makes it possible to suppress fluctuations in the power supply voltage and pulse input voltage.

Therefore, a highly accurate delay circuit can be realized with a simple configuration, and is particularly effective when the power supply voltage and input pulse voltage vary independently.

[Brief explanation of the drawing]

Fig. 1 is a delay circuit diagram according to a conventional example, Fig. 2 is a delay circuit diagram according to an embodiment of the present invention, Fig. 3 is an input pulse waveform diagram of the delay circuit, and Fig. 4 is a charging pulse waveform diagram of the same. . 5... Capacitor, 11... Constant voltage diode, 13... Diode.

Claims (1)

[Claims] 1. In a delay circuit that has a capacitor and a charging path that charges the capacitor with a pulse input, and generates an output pulse when the terminal voltage of the capacitor reaches a predetermined reference voltage, a constant voltage that makes the reference voltage constant. A delay circuit in which a cathode terminal of a diode and a portion of the charging path are connected through a diode.