JPS5825272A - Mos integrated circuit - Google Patents

Abstract

PURPOSE:To produce miniaturized MOSIC's of high density and of wider power margin by forming driving and loading transistors by means of the first and the second layers of polysilicon respectively. CONSTITUTION:When the FET1 whose gate electrode is the first polysilicon layer 1 is used for driving, the threshold voltage Vth can be stable to an extent of the short channel length L so that an element can be miniaturized. When the transistor is used for loading, dependency of the threshold voltage Vth on backgate bias is higher than the FET2 whose gate electrode is the second polysilicon layer 2, so that the ''1'' level of the output is reduced as compared with the case in which the FET2 is used for loading. Therefore, use of the FET2 for loading allows wider power margin. Manufacture of MOSIC's in such a way permits miniaturization of the products, speed-up of operation by reduction in the gate capacitance and formation of EPROM's having stabilized output.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Mos integrated circuit having two layers of polysilicon electrodes.

Integrated circuits, especially MOS integrated circuits, are used for their high-voltage changes or for charge storage.
Two-layer polysilicon processes have recently become very popular for forming (electrically rewritable +7-domain memories), in which case transistors are formed in the first polysilicon layer or Or whether to form a transistor with the second layer of I silicon has not been given much consideration, and conventionally transistors have been made with one layer (%) with two layers), but recently, with regard to #, IPROM'K has been In order to reduce the memory cell size, the first layer of polysilicon (I), which becomes floating e-), is formed in a self-aligned manner using the second-layer polysilicon r-) electrode, which becomes control dirt, as a mask. In order to reduce the number of steps involved, the dirt electrodes of transistors other than memory cells are made of the second layer of polysilicon.

Figure 1 shows a memory cell used in such a KPROMK. r
-) Electrode 1 is made of IIEI layers 1i1'J silicon layers, control f-) Electrode 1 is made of 82 layers ■f silicon layers. Then, the above floating r-) is placed on the pm semiconductor substrate 3.
The drain 4j is sandwiched between the electrode 1 and the control dart electrode 2.
One layer is formed which becomes the I- and source 5 regions. When it comes to such memories such as lPROM, floating r-F
Inject the electrode IK electrons or make it in a neutral state
Information 0"1"@Q# is determined.

Since this floating r-) electrode 1 must store electrons for a very long time (for example, 10 years), it is electrically insulated and is covered with an insulating film lK of 8102, for example.
Ru. For this reason, the process involves forming the floating r-) electrode 1, then thermally oxidizing it, and then K11lOtOJI! ki
After forming the ll film 6, a control f-)j, which is a second layer of 4-3 layers, is formed. Therefore, the first layer of polysilicon #i iris layer 1111I! (resilicon) will require an extra heat process.

Usually, the peripheral transistor (D
When making a ζ(1'-) electrode, a ζ(1'-) oxide film and a first.
It is noted that the insulating metal 8 between the silicon layers 11 and 11 is also oxidized at the same time.

Usually, the threshold voltage of a transistor is determined by implanting a transistor, such as M a y QI in the case of an N-channel transistor, into the channel region with an ion implantation technique. Before forming the trench (r-) electrode, a hole is implanted into the channel of the transistor. That is, in a transistor in which the first layer 4 silicon is used as the r-) electrode, before forming the ζ081 layer III silicon, the second layer is Before making 11 silicon, one ion ion oxide is added to the silicon.

As mentioned above, the first layer - the transistor line of the second layer 10/Resilison Ototsunzosta)
Also, since the thermal process is longer, the first layer 1113 is
The silicon of the silicon transistor is in the second layer / the silicon V-conductor transistor is diffused into the substrate 1. Therefore, the same amount of
Even in the case of 1), since the thermal process is longer in a single-layer silicon transistor, it diffuses deeply into the base 1 [1], and the 1117 daughter II! in the channel region. However, the second layer of the silicon transistor is also thinner.9, as shown in the characteristics of the fsz diagram, if you want to obtain the same threshold voltage, you will need 81 layers! l
II! Resilin transistors are better) many +#
I have to do a ion grant and %A,
In addition, the first layer of 4-Si transistors has a longer surface area (deeper in the substrate 1), e.g.
When the dark voltages of both silicon transistors are made equal, and their substrate bias characteristics are The transistors in the first layer also appear to have a high concentration on the substrate.

Figure 3 shows the pack r-) bias dependence characteristics as described above, where the horizontal axis is the square root of the substrate potential V, and the vertical axis is the dark value voltage when the substrate potential v1 is Ov, and the dark value when the substrate bias is applied. Each represents the difference from the value voltage. Referring to figure #E3, the threshold voltage difference ΔV□ of the transistor made of polysilicon in the first layer is larger than that of the transistor made of polysilicon in the second layer, and the channel region extends deeper into the substrate 3. ), and exhibits substrate bias dependence as if the substrate concentration were high.

Figure 4 shows the difference in threshold voltage between a transistor with a long channel length (for example, channel length: 40μ) and a transistor with a short channel length, vth=vthL−■□, on the vertical axis, and the effective channel length on the horizontal axis. 9 shows the short channel effect in which the shorter the channel length, the lower the threshold voltage. Referring to FIG. 4, it can be seen that a sudden drop in the threshold voltage in the first layer 4 silicon transistor does not occur even when the effective channel length is shortened. Therefore, the channel length of the first-layer IiI silicon transistor can be made smaller than the channel length of the second-layer Ilisilicon transistor, and if this is utilized, it becomes possible to miniaturize the device.

The present invention has been made in view of the above-mentioned circumstances, and uses a transistor formed by a dirt electrode of 49 silicon layers provided on a semiconductor substrate as a driving transistor. 2 layers of irises 1ds provided in
By having at least a part of the circuit which uses a transistor formed by an orthogonal electrode as a load transistor, it is possible to miniaturize the device and increase the density of the circuit, and also to reduce the output margin. The purpose is to provide an MO8O8 integrated conduit that can perform wide and stable operation.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.The present invention is based on a first layer silicon O transistor and a second layer silicon O transistor as shown in FIG. This is done by taking advantage of the characteristics of That is, the transistor made of polysilicon in the first layer is used as a driving transistor, and the transistor made of polysilicon in the first IEZ layer is used as a load transistor. As can be seen from Figure 4, if a transistor made of polysilicon in the first layer is used as a driving transistor, the dark voltage will be stabilized up to a very short channel length. By using it as a driving transistor,
) Enables miniaturization of elements. In this case, when the first layer polysilicon transistor is used as a load transistor, as can be seen from the above-mentioned figure For example, the output @1 level is lower than when a transistor made of second layer polysilicon is used as a load transistor. 0 threshold voltage to 1v, and its drain -? −)
When a K5VO signal voltage is applied, the voltage #i generated at the source is approximately 3.2V in the first layer silicon transistor, while it is approximately L4Y in the second layer II silicon transistor, as shown in Figure 3. be. In other words,
The output voltage of the second layer 11 silicon transistor is higher than that of the first layer polysilicon transistor;
V output is high. In other words, it is better to use an 8-layer silicon transistor as a load transistor.
A truly spacious power supply! - Jin is secured.

The driving transistor of the first layer polysilicon may be used alone in the first layer 4 silicon, but as shown in FIG. ;
This short-circuiting method may also be used by short-circuiting ν1.
Second layer 1lII! If you use die left tone tact, which directly connects the silicon and 1st layer, there is no need to increase the number of fams for *JII, and you can use the 2-layer 1vV silicone as a mask to create a self-aligned KIIi layer III! If polysilicon is formed, there will be no increase in manufacturing manpower @ 0. 5th Medical Affairs) is a schematic diagram of the thin layer. Figure 6 (&) is a cross-sectional view of the load transistor of the second layer of polysilicon, a compilation. Figure 6 (
b) An example of Fi's Shinhl diagram is shown.

Next, a specific circuit constructed using the above-mentioned transistors will be explained. FIG. 7 is an example of an address pacifier circuit for transmitting an address input to a decoder in a semiconductor memory. In this circuit, the power supply vc (for example !v)
Kl! in series with the reference power supply V, (OV). The transistor 'rt-'-T, which is connected to the inverter! ! Configure 1.

Transistor 'l'1. Tfit; is a load transistor made of second-layer silicon, a transistor? , is a drive transistor made of the first layer of polysilicon. The r-to of the transistor T1 is connected to the chip operation signal CM, and the r-) of the transistor T1 is connected to the address input AK. , are depletion melon transistors, whose r-) is connected to the source by iI. Similarly, the inverter 1 consists of transistors T4 to T connected in series to the power supply VcaV, transistors T4 and T1 are load transistors made of second-layer polysilicon, and transistor T- is The above in Δ−! 1st layer 4V with ISO output as f-) input
v: A drive transistor made of I-in. This in-eater 1. output terminal and reference power supply V, and tit%r at the output terminal of
-) reversed to ! Since the operation signal C is input, the first
A transistor Tt made of layered polysilicon is connected. Inverter 1. %Transistor with the same configuration as the inverter I3/'T@~TH@K"
The circuit is configured by connecting the C power supply Vc #"I@Ill K in series], and the ζO in Δ-/Is output terminal is connected to a Funzo star (similar to the transistor TV).Furthermore, the try yy- X/T*s e T's is voltage 11V, V, voltage K11ll! and buffer circuit Bl
Configure. This transistor 11 is a load transistor made of second layer polysilicon, the output of the inverter I is supplied to the transistor 7, and the transistor Tl is made of first layer I silicon. With the manufactured drive transistor, the output of the inverter 130 is supplied to the dart. A signal having the same phase as that of the address inputter is outputted from the output terminal of this bar 77 circuit BIO. On the other hand, the buffer circuits B and F are also the buffer circuits B! The inverter 1. output is supplied.

An impermeable output is supplied to the load transistor T14 formed of the first layer 4 silicon and the dart.
The driving transistor T formed of the first layer I silicon has a voltage of mVc, V.

The address input AO inverted signal is outputted from the output end of the output terminal of the output circuit B.

By the way, the transistors T4a and T.eTll to which the signals C1 and C1l are input function to reduce current consumption when the chip is in a non-operating state. At this time, the signal cgFi@o'%cg is at the '1' level, so the transistor D1 is activated.

T4#T Hatake's r-t is -o', so inverter 11~I
's no current consumption, also transistor T7sT
11 is turned on and the output of the inverter 11*11 is set to ``0 level (v level), so the potential of the load transistor 'rt*e'rt* of the buffer circuit B is OVK. The current in the Ha ψ7 circuit B15B1 also disappears. The above load transistor Tts*TssK wire 2 layers! Because it uses 4-Si transistors, the
The 1m1m level obtained at the output end of the F circuit Bs*B snow is sufficiently hot.The transistor for driving it is
You can also change the channel length of se'rti.

[Figure 8 is an example of an output buffer circuit for outputting data in the integrated circuit to the outside 11. In this circuit, the inverter I4 is formed by a second layer 11 switching capacitor with r-t connected to north, and connects deaf transistors T,- and %r-t in the integrated circuit. Iris 1 layer II where data is supplied
-Transistor made of silicon! 1! and r-
A switching operation signal CE is input to the top, and a transistor T made of first layer polysilicon is connected between the power supply v0 and the reference power supply V. The inverter Is is formed of transistors 1- to Tll, similar to the above-mentioned inverter Ir. The inverter I@ is composed of a deep-sealed transistor TI formed of 112th layer silicon with f-) connected to the source, and an inverter 1. 1 where the output of is input to the gate
IX 1st layer 4 Transistor Wa formed of silicon
S is connected between power supplies Vca and V@. The output buffer control signal 0]C is input to the output buffer circuit BsFi, f-). The output of inverter A transistor TI formed of the second layer polysilicon and a transistor TI formed of the first layer polysilicon whose output from the inverter I is inputted to ff-) are connected in series to the power supply Vq e Vm. KF is connected between the output terminal of this circuit B and the power supply V.
i, the first layer transistor T formed of 4-Si, to which the inversion ratio capacitor 7a control signal Oz is input;
11 are connected. P, 7A circuit 1. Similarly to the buffer circuit B described above, the transistors are also composed of transistors 1 to 3, and the transistors are formed in the second layer I and 3. The dart (2) is supplied with the output of the inverter 1, and the transistor Ts and r-) formed of the iris 1 layer 11 silicon is the inverter! The output terminal of the O buffer circuit B4 and the power source V1 are connected to the first layer 11, which is supplied with the signal OE, and is formed of silicon. s* #IaW1. The buffer circuit B is for directly outputting data to the outside, and the load transistor T Sm formed of tlllt2 layer 11 silicon is connected to the output terminal of the Δ17 circuit Bs, and ) is connected to the output terminal Kli of the buffer circuit 14, and a driving transistor TI formed of III-layer polysilicon is connected in a train between the power supplies Vce and MA1.In the above circuit, when CH Vf is in the operating state When , the signal CI is “1”, the inverted signal C]c is @01, and the signal ogVi″1m
1 inversion signal ox becomes 1o" and data is sent to the outside from the output terminal of the Δt7 circuit. When the chip is in the non-operating state, the signals CEFi@0', cgll"1", omh
-o', OIc becomes 11, and the current in the output and 7A circuits becomes almost zero.The outputs of p, t, and 7A circuits B1eB4 both become ``0#'', so both transistors rss e
Both Tlg are cut off and the output becomes a high resistance S.

SabK, even if the chip is in operation, if you want the output to be in a high resistance state, set the signal CE to "1", cg to "o", OK
If 10" and i -1"K, the transistor 〒14@
Since Tll is off and transistor Tml#T is on, the output of the buffer circuit B15B4 is at the 1o'' level], thereby both transistors T'is#T
jj is cut off and the output becomes a high resistance state. Even in the output capacitor circuit configured as described above, the output of the load transistor T'ms can be set to a sufficiently large 11" level, and the channel length of the drive transistor D can be shortened. .

As described above, according to the 111IO8 integrated circuit 1i111 of the present invention, the driving transistor is formed from the first layer of silicon, and the load transistor is formed from the second layer of silicon. The transistor can reduce its channel length, thereby reducing the 7"
By reducing the capacity, the female speed can also be improved. i, second
Since layer 11 silicon is used as a load transistor, there is no need to reduce the output level, and the power supply! - Enables high-density integrated circuits with a wide range of dimensions.

In addition, as described above, the present invention uses a transistor formed of the r-) electrode of $9 silicon in the first layer II as a driving transistor, and a dirt electrode of 112 layers 4 silicon.
It goes without saying that the present invention is not limited to the above-mentioned specific circuit example and can be applied to other integrated circuits as long as it includes an open circuit in which a transistor formed with the above is used as a load transistor. Further, the second dirt electrode xi is not limited to dI silicon, but may be made of other electrode materials.

[Brief explanation of the drawing]! [Figure 1 shows a general mFROM element, Figure (a) shows its structural cross-sectional view, Figure 2 shows its Schinhl diagram, Figure 2 shows a characteristic diagram showing the relationship between expanded threshold voltage and ion concentration, and Figure 3 shows a typical mFROM element. Figure F
Figure 1 shows the characteristics dependent on substrate bias, Figure 4 shows the characteristics of the short channel effect, Figure 51115 (-) shows the structure of the driving transistor and its thin diagram, and Figure 6 shows the characteristics of the short channel effect.
Figures 711 and 88 are diagrams showing the structure of a Fi load transistor, its thin line diagram, and diagrams 711 and 88, which are different circuit configuration diagrams to which the circuit of the present invention is applied.

Claims (2)

[Claims] (1) First layer dirt electrode and this first layer ff
-) The first layer f-) of the Mol integrated circuit has an electrode and a two-layer electrode made in a subsequent process.
The MDI (electrode) is made up of the driving transistor Ky#, and the second layer dirt electrode is made of the MDI transistor Ky#.
II) MO exposure integrated circuit characterized in that it has at least one circuit in which a load transistor is formed as a load transistor. (2) The Mol integrated circuit according to claim 1, wherein the driving transistor is constituted by a first layer dirt electrode directly connected to a second layer Ir-meter electrode.