JPS582507B2 - Still image receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention receives a still image signal sent superimposed on a television signal, stores the still image signal in a memory, reads it from this memory, and displays it on a display device such as a cathode ray tube. Regarding devices that reproduce and display still images, there is a function that stores still images sent one after another while updating them, and when the stored still image signal is stored as it is, the still image is displayed immediately when the still image display switch is turned on. can be displayed,
To provide a device that holds a still image signal when in a holding state, regardless of whether a still image is being displayed or not.

Recently, as a measure to expand the amount of information transmitted by television signals, the vertical retrace period of the television signal is used to display static images such as weather maps and news letters separately from normal television broadcast images. A still image signal for transmitting an image is superimposed, and the receiving side receives this still image signal and stores the still image signal for one screen of still images in a memory in a predetermined order. Devices have been developed that read out still image signals in synchronization with the horizontal and vertical scanning of display devices such as the above, and reproduce and display still images.

First, an example of such a still image signal transmission mode and the basic configuration of a receiving device will be described with reference to FIGS. 1 and 2.

Note that one screen of a still image has 240 pixels in the horizontal direction.
Assume that it is made up of bits and 200 lines in the vertical direction.

FIG. 1 shows a mode in which a still image signal is superimposed on a television signal. The 283rd H is omitted.

), for example, a 240-bit image signal V for one horizontal scanning line of a still image, and which program out of multiple programs such as weather forecasts and news, this image signal belongs to. A 4-bit program code signal PC indicating the video signal V, an 8-bit line number code signal LN indicating which horizontal scanning line from the top of the still image this video signal V belongs to, and each of these signals V, PC , LN are superimposed and transmitted.

Note that HS is a horizontal normal signal, and Bu is a color burst signal.

Further, each of the signals V, PC, and LN is transmitted as a binary signal of "1" or "0", and the basic clock frequency thereof is assumed to be 8/5 times the color subcarrier frequency of 3.58 MHz.

FIG. 2 is a block diagram showing the basic configuration of a receiving apparatus that receives such a multiplexed television signal, stores it in a memory, and displays and reproduces a still image on a cathode ray tube.

In this device, first, a receiver circuit 1 including a tuner, a VIF circuit, a video detection circuit, etc. receives the multiplexed television signal as described above, a sync separation circuit 2 extracts a composite sync signal, and a horizontal oscillation and horizontal AFC circuit 3 forms a horizontal pulse, and a vertical synchronization separation circuit 4 forms a vertical pulse.

Furthermore, the local subcarrier oscillation circuit 5 oscillates a 3.58 MHz color subcarrier signal synchronized with the burst signal Bu, and the reception clock signal generation circuit 6 multiplies this by 8/5 to 5.7.
A basic clock signal of 3 MHz is obtained and used as it is or after being counted down by a clock counter 7 as a clock signal for controlling the memory and other circuits described later.

On the other hand, from the television signal obtained by the receiving circuit 1, the 20th H.
Each signal STX, PC, LN and V superimposed on the eye
A still image signal extraction circuit 8 takes out the image signal V, and the image signal V is supplied to a buffer memory 9 having a storage capacity of 240 bits, for example, for one horizontal scanning line.

Further, the program code signal PC is extracted by the program code signal extraction circuit 10, and when the program code signal PC indicates a program desired to be received, the program code signal PC is extracted from the buffer memory 9.
is controlled and an image signal V is written therein.

The line number code signal LN is extracted by a line number code signal extraction circuit 11, and is the count output of a line counter 12 which counts horizontal pulses and detects which horizontal scanning line is being stored and reproduced by the receiving device. Comparison circuit 13 compares them, and when they match, input gate 14 is opened, image signal V from buffer memory 9 is added to main memory 15, and stored in a predetermined storage location in main memory 15.

The main memory 15 has a storage capacity capable of storing image signals V for one side of a still image. For example, the image signal V per horizontal scanning line is 240 bits and the image signal V is 200 horizontal scanning lines. If one screen is to be formed by using 1 screen, it has a storage capacity of 48K bits.

The main memory 15 may be configured by a shift register or the like.

After storing the image signal V in the main memory 15 in this way, the image signal V is read out from the main memory 15 in synchronization with the horizontal and vertical scanning of the cathode ray tube 16, and the mixing circuit 17 converts the image signal V into a normal television signal. By mixing it with a video signal and applying it to the cathode ray tube 16, a desired still image can be reproduced and displayed.

Further, the reference phase signal STX is supplied to the reference phase signal extracting circuit 1.
By applying this to the clock counter 7 as a reset pulse, the phase of the output clock signal of the clock counter 7 is synchronized with the phase of the reference phase signal STX, and accurate receiving, storing, and reading operations are established. That's what I do.

19 receives horizontal pulses, vertical pulses, clock signals, line count output signals, etc., and supplies clock signals, gate signals, etc. to operate each of the above-mentioned circuits with a predetermined phase relationship (timing); This is a control signal generation circuit for controlling the entire circuit that controls storage and readout operations.

In addition, in the above-mentioned receiving device, a clock signal is generated as a phase reference for the color burst signal, but this is done so that the clock of the multiplexed signal is synchronized with the color subcarrier signal on the transmitting side before being transmitted. It's for a reason.

That is, by using a clock signal having the same phase as the clock on the transmitting side on the receiving device side, a still image signal can be properly received, stored, read out, and reproduced as a still image.

This also applies to systems that transmit still image signals without using color subcarrier signals, such as systems that specifically insert a reference signal for generating a reception clock into a multiplexed signal.

The clock signal thus created on the receiving side is used not only for controlling storage of the image signal V, but also as a clock signal for controlling other still image receiving circuits, for example, as a clock signal for reading out the image signal V from the main memory. If it is also used as a signal, the circuit configuration becomes very simple and convenient.

As described above, it is possible to receive a still image signal, store it in the memory, read it out, and receive a still image.

On the other hand, such still image receiving devices are generally used in such a way that normal television reception images are displayed at normal times, and still images are displayed when necessary. When switching to displaying a still image while displaying a received image, it is desirable that the still image can be displayed immediately without waiting time.
Users often want to play back the same still image over and over again when necessary, so in such cases it is desirable to be able to retain the still image signal in memory. .

The present invention provides such a still image receiving device with two modes: storing the still image signal in the memory and updating the stored content each time it is received, and holding the stored content in the memory as it is without updating it. In the update state, newly received still images are stored each time during the period when still images are not displayed, and when the next time you switch to displaying still images, It is possible to immediately update and display the latest stored still image, and in the retained state, the stored contents of the memory are not cleared, so that they are retained even when switching to displaying still images. The object of the present invention is to provide a device that can display still images that are still images.

An embodiment of the present invention will be described below with reference to FIG.

Incidentally, in FIG. 3, the same parts as in the prior art are designated by the same reference numerals as in FIG. 2, and the explanation thereof will be omitted.

Here, the first section 20 switches whether to supply the still image signal V from the buffer memory 9 to the main memory 15 to update the stored content, or not to supply the still image signal V to the main memory 15 and to maintain the stored content. A switch circuit 21 supplies the still image signal read from the main memory 15 to a display device including the cathode ray tube 16 after the mixing circuit 17 to display a still image, or displays the still image signal. This is a second switch circuit that switches whether or not to display only a normal television image without supplying the television image.

Further, a portion 22 indicates that the second switch circuit 21 is in the updated state when the first switch circuit 20 is in an updated state.
When the main memory 15 is switched to display only normal television images, the main memory 15 is once cleared and then put into the updated storage state, and when the first switch circuit 20 is in the holding state, the second switch circuit 2
This is a clear control circuit that controls the memory clear operation so that the main memory 15 is not cleared and the stored contents are held as they are regardless of whether the main memory 15 is switched or not.

Next, its detailed configuration and operation will be explained.

First, the first switch circuit 20 will be described.

As mentioned above, the output of the comparator circuit 13 is stored in the main memory 1.
When the line in the clock at 5 matches the line number of the received still image signal, that is, the pulse becomes high only for one horizontal scanning period during the transfer period of the still image signal from the buffer memory 9 to the main memory 15. It is also added to the AND gate 23.

When the update storage stop switch 24 in the first switch circuit 20 is opened and the update storage state is established, the TT signal is connected to the other input of the AND gate 23 via the resistor 25.
A voltage of L high level (+5V) is applied, and at this time, the output of the comparator circuit 13 is directly outputted from the AND gate 23, making the AND gate 26 conductive.

At the same time, the signal is inverted by the inverter 27 and becomes a low level, thereby blocking the AND gate 28.

Therefore, at this time, the output of the buffer memory 9, that is, the newly received still image signal for one line passes through the AND gate 26 and the OR gate 29 to the main memory 15.
The stored contents of the main memory 15 are rewritten and updated by 1H.

When the output of the comparator circuit 13 is at a low level, that is, in a period other than the transfer period, the AND gate 28 becomes conductive, contrary to the present case.
The ND gate 26 is shut off, and the stored contents read from the main memory 15 are passed through the AND gates 30, 28 and O.
It is returned to the input of the main memory 15 via the R gate 29 and is circulated.

As a result, a still image is displayed in the same way as in the case described above.

Next, when the update storage stop switch 24 is closed,
Since AND gate 23 is cut off, its output is always at a low level, making AND gate 28 conductive and AND gate 26 cut off.

Therefore, no new still image signal is added to the main memory 15 from the buffer memory 9, and the AND gates 30, 2
8 and the OR gate 29, the stored contents are not updated and are held as they are.

Therefore, at this time, if the still image signal is read out from the main memory 15, the same still image can be repeatedly reproduced for a long time at any time.

In the above operation, the AND gate 30 is assumed to be conductive, but this AND gate 30 is controlled during clear control as described later.

Next, the second switch circuit 21 will be described.

When the switch 31 for switching and specifying whether or not to display a still image is closed and it is specified to display only the normal television received image, the flip-flop 32
The set terminal of Q changes from high level to low level, thereby being set, and its Q terminal output changes from high level to low level.

This Q terminal output is applied to the trigger terminal of a monostable multivibrator 33 for generating a clear control signal, triggering the monostable multivibrator 33 to generate a high level clear control signal from the Q terminal.

The output pulse width of the clear control signal output from the monostable multivibrator 33 is made slightly longer than one field period.

The Q terminal output of monostable multivibrator 33 is NAND
gate 34 and through this to AND gate 30.

Therefore, when the switch 24 of the first switch circuit 20 is opened and update storage is designated, the output of the NAND gate becomes low level during this clear control signal, and the A
The ND gate 30 is shut off for a little longer than 1 field, and 1
All the memory contents of the main memory 15 having the memory capacity for the field are cleared.

Once the memory contents of the main memory 15 have been cleared in this way, a new still image signal of the specified still image program is recorded in the main memory 15 in an updated storage state, so after that, the display switching switch 31 and designates still image display, a still image of the latest information up to that point is immediately displayed.

Therefore, at this time, if a still image program is specified, the latest still image can be obtained without waiting time.

Also, at this time, a new still image signal is stored after once clearing the main memory 15, so if the switch 31 is changed after displaying a still image and the program is switched to a new still image program. However, only the still image signal of a new program can be stored, and only the new still image can be displayed without the influence of the previous still image.

The flip-flop 32 is used to prevent the switch 31 from chattering, and the NAND gate 37 calculates the logical product of the Q terminal output of the monostable multivibrator 33 delayed by the resistor 35 and the capacitor 36 and the point terminal output.
A trailing edge pulse is formed by resetting to this pulse.

It goes without saying that the monostable multivibrator 33 can operate even if its trigger input terminal is directly connected to the switch 31.

In addition, when the display switching switch 31 of the second switch circuit 21 is closed and it is specified to display only the received television image, the AND gate 38 is also shut off, and the mixing circuit 17 is switched off. Since the read still image signal output of the memory 15 is not transmitted and the output of the mixing circuit 17 does not include a still image signal, no still image is displayed.

On the other hand, when the switch 24 of the first switch circuit 20 for memory state switching is closed and update memory is specified, the NAND gate 34 is always cut off, so even if the switch 31 is opened or closed, the monostable multivibrator is not activated. 33
The clear control signal output from main memory 1 does not pass through NAND gate 34 and is not transmitted to AND gate 30.
The memory contents of 5 are not cleared and are retained as they are.

In this state, if the display switching switch 31 is opened to specify still image display, the AND gate 38 becomes conductive, and the memory contents held in the main memory 15 are read out at any time, and the held still image remains unchanged. cathode ray tube 16
displayed above.

Therefore, important still images can be stored forever by keeping them in this holding state, and can be read out and displayed immediately when desired to be displayed.

Note that in this device, instead of the output of the comparator circuit 13,
If a roll gate pulse is supplied to the AND gate 23 during any 1H period after the display period, and the still image being received is of the desired program, an additional 1H is added after the end of the display period of each field. By clocking the buffer memory 9 and the main memory 16 so that the output of the AND gate 23 is at a high level for 1H period, the oldest still image signal stored in the main memory 15 can be read. The newly received still image signal is inputted and stored at the end of the main memory 15 by erasing 1H for each field, and the other still image signals are stored so that the storage position is raised by one line. It is possible to perform a so-called roll display in which still images are sequentially moved upward.

If the contents of the main memory 15 are updated and stored so that they can be displayed in rolls like this, when the switch 31 is released to specify the display of a still image, the waiting time will be reduced even for the previous one field of still images. Can be displayed without.

Therefore, when updating and storing data, it is desirable to close the switch 31 to specify display of only the received television image, and at the same time operate the main memory 15 in a rolling state.

This can be easily achieved by manually switching to roll.

It is assumed that the program selection switch for still image reception continues to specify the program that has been received up to that point even if the display of the received television image is specified.

As detailed above, the still image receiving device of the present invention includes a receiving circuit that receives a still image signal superimposed and sent during the vertical blanking period of a television signal, and a receiving circuit that stores the received still image signal. It comprises a memory for storing the still image signal and a reproduction circuit for reading the still image signal from the memory and displaying the still image, and each time the still image signal is received, it is supplied to the memory to update the stored contents, or it is not supplied. a first switch circuit for switching whether or not to retain the stored contents; When the first switch circuit is in an updated state, the second switch circuit switches to display only the normal television image. When the above-mentioned memory is once cleared and then put into the updated storage state, and when the above-mentioned first switch circuit is in the holding state, the above-mentioned memory is not cleared and the stored contents are updated regardless of whether the above-mentioned second switch circuit is switched. The invention is characterized by comprising a clear control circuit for holding the .

Therefore, according to the present invention, when the first switch circuit switches to the updated memory state, even when the second switch circuit switches to display only the television reception signal and not display the still image, a new still image is displayed. Since the image signal is received and stored in the memory while being updated, when the second switch circuit is switched to still image display, the latest still image up to that point can be immediately displayed without waiting time.

Furthermore, when the second switch circuit is switched to display the received television image, the contents of the memory are cleared once,
Since the new still image signal is then stored, only the new still image can be displayed without being adversely affected by the old still image.

Furthermore, when the first switch circuit is switched to the holding state, the contents of the memory are retained regardless of whether the second switch circuit is switched, so important still images, etc. can be retained forever. , and can be read and displayed whenever the second switch circuit instructs to display a still image.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram showing an example of a still image signal, FIG. 2 is a block diagram of a conventional still image receiving device, and FIG. 3 is a block diagram of main parts of a still image receiving device in an embodiment of the present invention. It is a diagram. 1... Receiving circuit, 8... 20H extraction circuit, 9... Buffer memory, 10...
・Program code extraction circuit, 11... Line number code extraction circuit, 12... Line counter, 13
... Comparison circuit, 14 ... Input gate,
15...Main memory, 16...Cathode ray tube, 17...Mixing circuit, 18...Reference phase signal extraction circuit, 19... Control signal generation circuit, 20...first switch circuit, 21...
...Second switch circuit, 22...Clear control circuit, 23, 26, 28, 30, 38...A
ND gate, 24... switch, 25...
...Resistor, 27...Inverter, 29...
OR gate, 31... switch, 32...
...Flip-flop, 33... Monostable multivibrator, 34, 37... NAND gate, 35... Resistor, 36... Capacitor.

Claims (1)

[Claims] 1. A receiving circuit that receives a still image signal superimposed and sent during the vertical blanking period of a television signal;
It includes a memory for storing and accumulating the received still image signal, and a reproducing circuit that reads the still image signal from this memory and displays the still image, and supplies the still image signal to the memory each time the still image signal is received to store the stored contents. The first step is to switch whether to update the memory content or to retain the memory contents without supplying it.
a second switch circuit that switches between supplying the still image signal read from the memory to the display device to display a still image, or not supplying the still image signal to the display device and displaying only a normal television received image; , when the first switch circuit is in the updated state and the second switch circuit is switched to display only the normal television received image, the memory is once cleared and then updated memory. and a clear control circuit that holds the memory contents without clearing the memory regardless of whether or not the second switch circuit is switched when the first switch circuit is in the holding state. A still image receiving device characterized by. 2. A monostable multivibrator that is triggered when the second switch circuit is switched to the normal television image display state, and a monostable multivibrator that is triggered only when the first switch circuit is switched to the update state. 2. The still image receiving device according to claim 1, further comprising a gate for taking out the output of the stable multivibrator, and the memory is cleared by the output of the gate. 3. A flip-flop that is inverted when the switch provided in the second switch circuit is switched to a normal television image display state, and the monostable multivibrator is triggered by the output of this flip-flop. A still image receiving device according to claim 2.