JPS5824515Y2 - Power field effect transistor drive circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a drive circuit for an FET in an amplifier using a power junction field effect transistor (FET), and particularly to a power FET drive circuit in an amplifier intended to use the FET as a switching element. It is related to circuits.

Generally, in order to perform switching operations on FETs in this type of amplifier, the FETs are driven with a rectangular waveform as is well known.
In order to apply the driving waveform to the gate of the FET without changing the driving waveform, it is necessary to make the driving impedance lower than the gate input impedance, which requires a large amount of driving power.

If the rectangular waveform is disturbed, not only will the amplification efficiency of the FET amplifier decrease, but the FET element will generate more heat, which will require a larger heatsink for the amplifier, increasing costs. It is extremely important to do this completely with a rectangular waveform.

In view of the above, it is an object of the present invention to provide a power FET drive circuit that requires less switching driving power for a power junction FET and can switch the FET with a high frequency accurate rectangular waveform.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the circuit of the power junction FET0 at high frequency.

In FIG. 1, G is the gate, D is the drain, and S is the source.

The gate input impedance Zin is determined by C5 and Cr when the source is grounded.

The gate input capacitance Cin seen from the gate G is C1o=Ci
+Cr, but it can be thought of as mainly Ci.

Therefore, gate input impedance Zin=1/ω・Ci
n, and C1 of the current power junction FET is 3000
It is about pF'-1000pF.

For example, C: = 2000pF, ω = 2πf (f =
lo OkHz), Zln-800Ω.

The harmonic components included in the 100 kHz rectangular waveform in the switching waveform drive include I MHz, and require a rising time of 1 μs, which in this case becomes Zin-80Ω.

FIG. 2 is a diagram showing the operation of a push-pull circuit of a power junction FET, where .DELTA.D is the drain current, vGs is the gate-source voltage, and VDD is the voltage applied to the drain.

In the figure, to operate the FET, vGs=O to vGs=
-20v×2 signal waveform is required.

That is, as is well known in the push-pull circuit operation, when VDD=140V, if the voltage amplification factor of the FET is μ, the gate signal needs to be VDDX2/μ=40V.

Now, assuming that the FET input impedance Z, n = 80Ω, and the drive waveform voltage VGS = 40VPP, in the conventional FET push-pull circuit shown in Figure 3, if RG is the emitter resistance of the drive transistor, the FET The driving power P is P=(VGS)/RG=(40)/so=
It becomes 20 watts.

Note that these driving voltages are independent of the output power of the FET and are not injected into the gate of the FET.

The power is simply used to apply a rectangular voltage to the gate of the FET, and one of the characteristics of the FET, which is the high input impedance of the voltage-controlled element, is not utilized.

Now, FIG. 4 shows a bush-pull circuit type amplifier using a drive circuit according to an embodiment of the present invention.

The input signal (square wave) is connected to the oscillation circuit through the coupling transformer T-1.
PNP type amplification stage transistor Q1. It enters the base of each of Q2 and is amplified to a voltage that is the sum of the supply power supply negative voltage -B and the supply power supply positive voltage terminal B.

The outputs of the amplifier stage transistors Q1 and Q2 are respectively input to the bases of emitter follower drive transistors Q3 and Q4, and although the voltage is not amplified, the impedance is converted as is well known and the output impedance is lowered.

The emitters of these driving transistors Q3 and Q4 are each N-channel power junction type FET Q5 whose source is grounded.
- Directly connected to the gate of Q6.

Further, each of the driving transistors Q3 and Q4 has a collector connected to a negative potential -B and an emitter connected to a positive potential terminal B through an emitter resistor RG.

In this way, power junction FETQ5. When Q6 is an N-channel type, the amplifier stage transistors Ql-Q2 are PNP type, and the driving transistors Q3. P also in Q4
Using the NP type, the collectors of the amplification stage transistors Ql-Q2 are connected to a negative voltage -B through resistors, the emitters of the amplification stage transistors Q□-Q2 are respectively connected to a positive potential element B, and the driving transistors Q3. The collectors of Q4 are each connected to negative potential -B, and the emitters of drive transistors Q3-Q4 are each connected to positive potential B through resistors RG.

Note that the power junction FET Q5. If Q6 is a P-channel type opposite to that shown in FIG. 4, the amplification stage transistor Ql-
NPN type is used for Q2, and driving transistors Q3-Q
NPN type is also used for 4, and amplification stage transistors Ql-Q2
The collectors of the amplifier stage transistors Ql-Q2 are connected to the positive potential terminal B through resistors, the emitters of the amplifier stage transistors Ql-Q2 are connected to the negative potential -B, respectively, and the collectors of the driving transistors Q3-Q4 are connected to the positive potential terminal B, respectively. Transistor Q3
-The emitter of Q4 is at a negative potential through each resistor RG.
Connected to B.

In addition, in FIG. 4, T-2 is a transformer for coupling FETs Q5-Q6 and load RL.

FIG. 5 shows the gate signal waveforms of FETQ5-Q6.

The following explanation will be made regarding the N-channel FET, but it goes without saying that the same explanation can be given to the operation of the P-channel FET by simply converting the voltage sign.

In FIG. 5, when the FET gate voltage is zero, the drain and source of the FET are in a conductive ON state, and when the voltage is -B, the FET is in an open QFF' state.

Now, the waveform shown in Figure 5 is the ideal switching waveform of the signal waveform applied to the gate of the FET.

Now, the emitter resistance Ro of driving transistors Q3-Q4
The O value is the gate input impedance Z of FETQ5-Q6
, n, and if the supply voltage positive voltage element B is not added, the gate voltage waveform will be the waveform shown in Figure 5.

■The reason why the rising part of the waveform does not become a rectangular wave is because the rectangular wave on the input side is due to the output impedance of the driving transistors Q3-Q4 and the FET Q5. This occurs because the gate capacitance Ci of Q6 constitutes an integrating circuit.

To sharpen this rise, lower the emitter resistance RG and drive transistor Q3. Although it is necessary to lower the output impedance of Q4, the problem arises that the driving power increases as described above.

Therefore, in order to make the gate drive voltage an ideal rectangular wave, the present invention connects the emitter side of the drive transistor to the positive potential terminal B.
It is characterized by:

That is, by applying a positive voltage +B as the emitter side voltage of the driving transistor, the (2) waveform in FIG. 5 rises by the positive voltage, like the 0 waveform.

However, due to the characteristics of FE'l', it has diode characteristics between the gate and source, and the positive voltage part of the 0 waveform is clipped by the diode action of the FET, so it does not appear as a drive waveform, and is not ideal. It becomes a rectangular wave shape.

As a result of the above explanation, the gate waveform of the FET becomes the waveform (2) that is optimal for the switching operation.

The driving power at this time is the driving transistor Q3-Q4
It is determined by the emitter resistance RGO value and the positive voltage terminal B on the emitter side, but in the circuit example of the present invention, the negative voltage of the power supply - B =
-40V, positive voltage element B=15V, frequency 100kHz, RG=6.8 and Ω, the calculated power loss due to driving was 0.8 watts, but the actual value was 0.8 watts.

The difference between the measured value and the calculated value is the drive transistor Q3-Q4.
Efficiency and FETQ5. It is thought that the consumption is due to the diode characteristics in Q6.

The power consumption in the drive circuit consisting of transistors Q1 to Q4 was actually measured to be 4 watts, and in the conventional circuit shown in FIG. is the driving power of

As described above, the present invention can utilize the characteristics of the power FET for the maximum wave in a high frequency FET switching amplifier, and
It is a FET drive circuit that can turn on and off the T load with a precise square wave voltage and reduces drive power, making it possible to reduce the power of the drive amplifier circuit, reducing the size of the transistor used and the capacity of the power supply circuit. It has a great effect on power amplifiers and is a significant improvement in terms of cost reduction and performance improvement, and its industrial value is extremely large.

[Brief explanation of the drawing]

Figure 1 is an equivalent circuit diagram of a power junction field effect transistor, Figure 2 is a diagram showing the operating line of the bush-pull circuit of a power junction field effect transistor, and Figure 3 is a diagram of a conventional power junction field effect transistor. FIG. 4 is a circuit diagram showing a push-pull circuit amplifier using an effect transistor as a switching element, and FIG. 4 is a circuit diagram showing a drive circuit according to an embodiment of the present invention as a power field effect transistor drive circuit of FIG. 5 is a diagram for explaining the gate-source voltage waveform of the field effect transistor Q5 or Q''6 in FIG. 4. Ql and Q2...Amplification stage transistors, Q3
and Q4...drive transistor, Q5 and Q6...power field effect transistor, 10B
...Supply power supply positive voltage, -B...Supply power supply negative voltage, RG...Emitter resistance, T-1 and T-2...Transformer, RL...Load.

Claims (1)

[Scope of utility model registration request] A drive circuit for a field effect transistor in an amplifier using a grounded source power junction field effect transistor as a switching element, the drive circuit having a positive voltage and a negative voltage as a power supply, and having an input signal as a base. and an emitter-follower drive transistor whose base is connected to the collector of the amplification stage transistor, the emitter of the drive transistor being directly connected to the gate of the field effect transistor, and the emitter follower drive transistor receiving the field effect transistor. effect transistor is N
In the case of a channel type, the collector of the amplification stage transistor and the collector of the drive transistor are connected to the negative voltage, the emitter of the amplification stage transistor and the emitter of the drive transistor are connected to the positive voltage, and conversely, the collector of the amplification stage transistor and the drive transistor are connected to the positive voltage. When the effect transistor is a P-channel type, the collector of the amplification stage transistor and the collector of the drive transistor are connected to the positive voltage, and the emitter of the amplification stage transistor and the emitter of the drive transistor are connected to the negative voltage. A power field effect transistor drive circuit characterized by: