JPS5823995B2 - Irosingou Shiyori Cairo - Google Patents

Irosingou Shiyori Cairo

Info

Publication number
JPS5823995B2
JPS5823995B2 JP50128701A JP12870175A JPS5823995B2 JP S5823995 B2 JPS5823995 B2 JP S5823995B2 JP 50128701 A JP50128701 A JP 50128701A JP 12870175 A JP12870175 A JP 12870175A JP S5823995 B2 JPS5823995 B2 JP S5823995B2
Authority
JP
Japan
Prior art keywords
circuit
signal
output
supplied
burst
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50128701A
Other languages
Japanese (ja)
Other versions
JPS5252327A (en
Inventor
岡部全克
赤沢進
村上恭一
土屋尭央
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP50128701A priority Critical patent/JPS5823995B2/en
Priority to GB4354476A priority patent/GB1558395A/en
Priority to DE19762647905 priority patent/DE2647905B2/en
Priority to NL7611813A priority patent/NL189383C/en
Priority to AU19139/76A priority patent/AU508242B2/en
Publication of JPS5252327A publication Critical patent/JPS5252327A/en
Publication of JPS5823995B2 publication Critical patent/JPS5823995B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00Details of colour television systems
    • H04N9/64Circuits for processing colour signals
    • H04N9/646Circuits for processing colour signals for image enhancement, e.g. vertical detail restoration, cross-colour elimination, contour correction, chrominance trapping filters

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)

Description

【発明の詳細な説明】 本発明は例えはPAL方式のカラーテレビ信号の搬送色
信号から色信号(R−Y成分およびB−Y成分)を復調
するのに適用される色信号処理回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color signal processing circuit applied to demodulate a color signal (RY component and BY component) from a carrier color signal of a PAL color television signal, for example.

本発明の理解の容易のため従来の色信号処理回路の一例
について第1図を参照して説明するに、同図において、
1はPAL方式の複合カラーテレビ信号より分離された
搬送色信号およびバースト信号の供給される端子を示す
In order to facilitate understanding of the present invention, an example of a conventional color signal processing circuit will be described with reference to FIG.
Reference numeral 1 indicates a terminal to which a carrier color signal and a burst signal separated from a PAL composite color television signal are supplied.

この搬送色信号は色信号の(R−Y)成分および(B−
Y)成分により変調された直角二相平衡変調波であり、
(R−Y)成分により変調される搬送波の位相がIH(
1水平周期)毎に反転され、これと共にバースト信号の
位相がIH毎に(B−Y)軸に対して135°遅れるか
進んだものとなされている。
This carrier color signal consists of the (R-Y) component of the color signal and the (B-
Y) is a quadrature two-phase balanced modulated wave modulated by the component,
The phase of the carrier wave modulated by the (RY) component is IH (
At the same time, the phase of the burst signal is delayed or advanced by 135° with respect to the (BY) axis for each IH.

この搬送色信号が可変利得増幅器の構成のACC回路2
を介してIH(1水平周期)遅延線3に供給されると共
に、加算回路4および減算回路5に供給され、また、こ
れら加算回路4および減算回路5にIH遅延線3の出力
が供給されることにより、加算回路4の出力に搬送色信
号中の(B−Y)成分が得られ、減算回路5の出力に搬
送色信号中の(R−Y)成分が得られる。
This carrier color signal is transmitted to an ACC circuit 2 having a variable gain amplifier configuration.
is supplied to the IH (one horizontal period) delay line 3 via the IH (one horizontal period) delay line 3, and is also supplied to the addition circuit 4 and the subtraction circuit 5, and the output of the IH delay line 3 is supplied to the addition circuit 4 and the subtraction circuit 5. As a result, the (B-Y) component in the carrier color signal is obtained at the output of the adder circuit 4, and the (R-Y) component in the carrier color signal is obtained at the output of the subtractor circuit 5.

これらの信号が例えは二重平衡接続の復調回路6Bおよ
び6Rにより復調され、端子IBおよび7Rにそれぞれ
バースト信号の復調出力を含む(B−y:)成分の色信
号および(R−Y)成分の色信号が現れることになる。
These signals are demodulated by, for example, double-balanced demodulation circuits 6B and 6R, and the (B-y:) component chrominance signal and (R-Y) component including the demodulated output of the burst signal are output to terminals IB and 7R, respectively. A color signal will appear.

復調回路6Bには電圧制御形の可変周波数発振器8から
(B−Y )軸と一致した位相の搬送波が供給される。
A carrier wave whose phase coincides with the (BY) axis is supplied from a voltage-controlled variable frequency oscillator 8 to the demodulation circuit 6B.

このため加算回路4の出力からパーストゲート回路9で
、バースト信号が分離され、このバースト信号が位相検
波回路10で位相検波され、その検波出力が可変周波数
発振器8に制御電圧として供給される。
Therefore, a burst signal is separated from the output of the adder circuit 4 by a burst gate circuit 9, this burst signal is phase detected by a phase detection circuit 10, and the detected output is supplied to the variable frequency oscillator 8 as a control voltage.

パーストゲート回路9には、端子11からバーストフラ
ッグが供給される。
A burst flag is supplied to the burst gate circuit 9 from a terminal 11 .

ましてスイッチ回路13の一方の入力端子aに供給分し
てスイッチ回路13の他方の入力端子すに供給される。
Furthermore, the amount supplied to one input terminal a of the switch circuit 13 is supplied to the other input terminal a of the switch circuit 13.

スイッチ回路13はフリップフロップ15の出力で制御
される電子スイッチで、フリップフロップ15に端子1
6から水平同期パルスが供給されることによりIH毎に
切換えられる。
The switch circuit 13 is an electronic switch controlled by the output of the flip-flop 15.
Switching is performed for each IH by supplying a horizontal synchronizing pulse from 6.

従って、スイッチ回路13の出力端子Cに生じるIH毎
に(トY)軸あるいは−(R−Y)軸に一致するように
位相が切換えられた搬送波が復調回路6Rに供給される
Therefore, for each IH generated at the output terminal C of the switch circuit 13, a carrier wave whose phase is switched to coincide with the (Y) axis or the -(RY) axis is supplied to the demodulation circuit 6R.

さらに端子7Rに得られるバースト信号の復調出力およ
び(R−Y)成分がパーストゲート回路11に供給され
、その出力に得られるバースト信号の復調出力が色信号
のレベルおよび極性制御信号発生回路18に供給される
Further, the demodulated output of the burst signal obtained at the terminal 7R and the (R-Y) component are supplied to the burst gate circuit 11, and the demodulated output of the burst signal obtained at the output is supplied to the color signal level and polarity control signal generation circuit 18. Supplied.

この回路18はゲート回路17の出力よりACC回路2
に対するACC電圧を形成すると共に、復調回路6Rの
出力の(R−Y)成分の極性が正しいか否かの識別を行
なうもので、極性が正しくない場合にはフリップフロッ
プ15に対して訂正信号を与えるものである。
This circuit 18 is connected to the ACC circuit 2 from the output of the gate circuit 17.
In addition to forming an ACC voltage for the demodulation circuit 6R, it also determines whether the polarity of the (RY) component output from the demodulation circuit 6R is correct or not. If the polarity is incorrect, it sends a correction signal to the flip-flop 15. It is something to give.

かかる色信号処理回路において、白黒画像のときのよう
に、端子1にバースト信号のみ供給された場合を考える
と、加算回路4および減算回路5の出力には、原理的に
はバースト信号のみが現れるはずであるが、実際にはI
H遅延線3の出力には遅延媒体における不要反射のため
に水平ブランキング期間以外で20数dB〜30dB(
IH遅延された信号に対して)の不要信号が含まれてい
る。
In such a color signal processing circuit, if we consider a case where only a burst signal is supplied to terminal 1, as in the case of a monochrome image, only burst signals appear in the outputs of addition circuit 4 and subtraction circuit 5 in principle. It should be, but actually I
The output of the H delay line 3 has a level of 20-30 dB (20-odd B to 30 dB) outside the horizontal blanking period due to unnecessary reflections in the delay medium.
Contains unnecessary signals (with respect to IH-delayed signals).

この不要信号が復調回路6Bおよび6Rで復調されるた
めに、画面が暗くなるとたでの色縞が現れて、画質が劣
下する欠点があった。
Since these unnecessary signals are demodulated by the demodulation circuits 6B and 6R, color stripes appear when the screen becomes dark, resulting in a deterioration in image quality.

本発明は上述の点を考慮して、第2図に示すようにゲー
ト回路19をIH遅延線3の入力側に設けて、端子20
からバースト期間のみ発生するゲートパルスを供給し、
IH遅延線3に供給されるバースト信号を遮断するかあ
るいは減少させるようにしたものである。
In consideration of the above points, the present invention provides a gate circuit 19 on the input side of the IH delay line 3 as shown in FIG.
A gate pulse that occurs only during the burst period is supplied from
The burst signal supplied to the IH delay line 3 is cut off or reduced.

以下1本発明の一実施例について第3図を参照して説明
するに、同図において、21はIH遅延線3の遅延媒体
を示し、22および23は入力側および出力側の変換器
を示し、夫々の変換器の電極から入力端子24a 、2
4bおよび出力端子25aおよび25bが導出される。
An embodiment of the present invention will be described below with reference to FIG. 3. In the figure, 21 indicates a delay medium of the IH delay line 3, and 22 and 23 indicate converters on the input side and output side. , from the electrodes of the respective transducers to the input terminals 24a, 2
4b and output terminals 25a and 25b are led out.

また、ACC回路2の出力が供給される入力端子26が
トランジスタ27のベースに接続され、そのエミッタが
抵抗器28を介して接地されると共に、そのコレクタが
抵抗器29および補償コイル30の並列回路と抵抗器3
1とを介して電源端子(+VCC)に接続され、この抵
抗器29の両端がIH遅延線30入力端子24aおよび
24bにそれぞれ接続される。
Further, an input terminal 26 to which the output of the ACC circuit 2 is supplied is connected to the base of a transistor 27, its emitter is grounded via a resistor 28, and its collector is connected to a parallel circuit of a resistor 29 and a compensation coil 30. and resistor 3
1 to the power supply terminal (+VCC), and both ends of this resistor 29 are connected to input terminals 24a and 24b of the IH delay line 30, respectively.

これと共に抵抗器290両端がそれぞれダイオード32
aおよび32bのアノードに接続され、これらダイオー
ドのカソードが抵抗器33を介してゲートパルスPgの
供給端子20に接続される。
Along with this, both ends of the resistor 290 are connected to diodes 32, respectively.
a and 32b, and the cathodes of these diodes are connected via a resistor 33 to the supply terminal 20 of the gate pulse Pg.

ゲートパルスPgはフライバック期間のみ発生する負の
パルスで、このゲートパルスPgにより端子20が電源
電圧+VCCより高い電位からこれより低い電位とされ
、フライバック期間のみでダイオード32a 、32b
がオンし、従って、IH遅延線の入力端子24a 、2
4bが交流的に短絡されるようになされている。
The gate pulse Pg is a negative pulse that occurs only during the flyback period, and this gate pulse Pg changes the terminal 20 from a potential higher than the power supply voltage +VCC to a lower potential, and the diodes 32a and 32b are connected only during the flyback period.
is turned on, therefore, the input terminals 24a, 2 of the IH delay line
4b is short-circuited in an alternating current manner.

ゲートパルスPgは水平フライバックパルスなどから形
成することができる。
The gate pulse Pg can be formed from a horizontal flyback pulse or the like.

また、IH遅延線3の出力端子25a 、25b間に補
償用コイル34が接続されると共に、出力端子25aが
抵抗器35を介して接地され、出力端子25bが抵抗器
36を介して接地される。
Further, a compensation coil 34 is connected between the output terminals 25a and 25b of the IH delay line 3, and the output terminal 25a is grounded via a resistor 35, and the output terminal 25b is grounded via a resistor 36. .

この出力端子25aおよび抵抗器35の接続点がトラン
ジスタ27のエミッタに抵抗器37を介して接続され、
出力端子25bおよび抵抗器36の接続点がトランジス
タ27のエミッタに抵抗器38を介して接続される。
A connection point between the output terminal 25a and the resistor 35 is connected to the emitter of the transistor 27 via the resistor 37,
A connection point between output terminal 25b and resistor 36 is connected to the emitter of transistor 27 via resistor 38.

ここで、出力端子25aと25bに生じる出力信号は逆
極性のものであるから、抵抗器28,37.35によっ
て端子26からの入力信号とIH遅延線3の出力信号と
が加算39aにバースト信号および(B−Y)成分の搬
送色信号が得られ、また抵抗器28,38.36によっ
て、入力信号とIH遅延線3の出力信号とが減算され端
子39bにバースト信号および(R−Y)成分の搬送色
信号が得られ、これらが復調回路6Bおよび6Rに供給
される。
Here, since the output signals generated at the output terminals 25a and 25b are of opposite polarity, the input signal from the terminal 26 and the output signal of the IH delay line 3 are added by the resistors 28, 37.35 to the burst signal 39a. The input signal and the output signal of the IH delay line 3 are subtracted by the resistors 28, 38, 36, and the burst signal and (RY) component are obtained at the terminal 39b. Component carrier color signals are obtained and supplied to demodulation circuits 6B and 6R.

上述の本発明の一実施例の構成に依れば、バースト期間
では入力側変換器22には入力電圧が印加されないから
、バースト信号はIH遅延線3を介されることなく復調
回路6Bおよび6Rに係給される。
According to the configuration of the embodiment of the present invention described above, since no input voltage is applied to the input side converter 22 during the burst period, the burst signal is sent to the demodulation circuits 6B and 6R without being passed through the IH delay line 3. will be charged.

従って不要信号が復調されて白黒画像のときに画面上に
たての色縞が現れることを防止することができる。
Therefore, it is possible to prevent unnecessary signals from being demodulated and vertical color stripes from appearing on the screen when the image is black and white.

また、加算回路4あるいは減算回路5の出力にはバース
ト信号が存在しているから、このバースト信号に基いて
復調用の搬送波およびAC’C信号を形成できると共に
、色信号の極性判別を行なうことができる。
Furthermore, since a burst signal is present in the output of the adder circuit 4 or the subtracter circuit 5, it is possible to form a carrier wave for demodulation and an AC'C signal based on this burst signal, and also to determine the polarity of the color signal. I can do it.

また、上述の本発明の一実施例では、IH遅延線3に対
するバースト信号の供給を遮断するようにしたが、これ
・に限らず不要信号成分が復調されても色縞が検知でき
ない程度に減少させて、IH遅延線3に供給するように
しても良い。
In addition, in the embodiment of the present invention described above, the supply of the burst signal to the IH delay line 3 is cut off. Alternatively, the signal may be supplied to the IH delay line 3.

具体的には例えば第4図に示すように上述の一実施例の
構成における抵抗器290両端とダイオード32aおよ
び32bとの間に夫々抵抗器40aおよび40bを挿入
すれば良い。
Specifically, for example, as shown in FIG. 4, resistors 40a and 40b may be inserted between both ends of resistor 290 and diodes 32a and 32b, respectively, in the configuration of the above-described embodiment.

なお、本発明はPAL方式の色信号復調回路に限らず、
NTSC方式のカラーテレビ信号の輝度信号および搬送
色信号をIH遅延線からなるくし形フィルタで分離する
場合などにも適用して同様の利益がある。
Note that the present invention is not limited to a PAL color signal demodulation circuit;
Similar benefits can be obtained when applied to cases where the luminance signal and carrier color signal of an NTSC color television signal are separated using a comb filter consisting of an IH delay line.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明を適用しうる色信号処理回路の一例の系
統図、第2図は本発明の要部系統図、第3図は本発明の
一実施例の接続図、第4図は本発明の他の実施例の゛要
部接続図である。 1は搬送色信号およびバースト信号の供給される端子、
3はIH遅延線、6B、6Rは復調回路、20はゲート
パルス供給端子である。
Fig. 1 is a system diagram of an example of a color signal processing circuit to which the present invention can be applied, Fig. 2 is a system diagram of main parts of the invention, Fig. 3 is a connection diagram of an embodiment of the invention, and Fig. 4 is a system diagram of an example of a color signal processing circuit to which the present invention can be applied. FIG. 6 is a connection diagram of main parts of another embodiment of the present invention. 1 is a terminal to which a carrier color signal and a burst signal are supplied;
3 is an IH delay line, 6B and 6R are demodulation circuits, and 20 is a gate pulse supply terminal.

Claims (1)

【特許請求の範囲】[Claims] 1 搬送色信号及びバースト信号が供給されると共に、
上記バースト信号を除去あるいは減少させるゲート回路
と、該ゲート回路からの出力が供給され遅延時間が1水
平期間に等しい遅延線と、上記ゲート回路の入力側の信
号と上記遅延線の出力側の信号が供給される加算回路及
び減算回路とを有し、上記加算回路と上記減算回路より
出力搬送色信号及び出力バースト信号を得、上記出力搬
送色信号を復調回路に供給し、上記出力バースト信号を
利用回路に供給するようにしたことを特徴とする色信号
処理回路。
1 A carrier color signal and a burst signal are supplied, and
a gate circuit that removes or reduces the burst signal; a delay line to which the output from the gate circuit is supplied and whose delay time is equal to one horizontal period; a signal on the input side of the gate circuit and a signal on the output side of the delay line; the output carrier color signal and the output burst signal are obtained from the addition circuit and the subtraction circuit, the output carrier color signal is supplied to a demodulation circuit, and the output burst signal is A color signal processing circuit characterized in that the color signal is supplied to a circuit to be used.
JP50128701A 1975-10-24 1975-10-24 Irosingou Shiyori Cairo Expired JPS5823995B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP50128701A JPS5823995B2 (en) 1975-10-24 1975-10-24 Irosingou Shiyori Cairo
GB4354476A GB1558395A (en) 1975-10-24 1976-10-20 Colour video signal processing circuits
DE19762647905 DE2647905B2 (en) 1975-10-24 1976-10-22 Color television receiver circuit
NL7611813A NL189383C (en) 1975-10-24 1976-10-25 COLOR TV RECEIVER.
AU19139/76A AU508242B2 (en) 1975-10-24 1976-10-29 Colour video signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50128701A JPS5823995B2 (en) 1975-10-24 1975-10-24 Irosingou Shiyori Cairo

Publications (2)

Publication Number Publication Date
JPS5252327A JPS5252327A (en) 1977-04-27
JPS5823995B2 true JPS5823995B2 (en) 1983-05-18

Family

ID=14991276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50128701A Expired JPS5823995B2 (en) 1975-10-24 1975-10-24 Irosingou Shiyori Cairo

Country Status (5)

Country Link
JP (1) JPS5823995B2 (en)
AU (1) AU508242B2 (en)
DE (1) DE2647905B2 (en)
GB (1) GB1558395A (en)
NL (1) NL189383C (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58116378U (en) * 1982-02-02 1983-08-09 シャープ株式会社 Color television receiver circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1537225A1 (en) * 1967-12-08 1970-03-05 Loewe Opta Gmbh Circuit arrangement for automatically switching off or switching on the color channel in a color television receiver operating according to the PAL system
DE1762930C3 (en) * 1968-09-25 1979-03-15 Graetz Gmbh & Co Ohg, 5990 Altena Circuit arrangement for the automatic blocking of the color channel by means of a flip-flop if the color sync signal is missing or too small in hi color television receivers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SORTING OUT THE COLOUR SIGNAL=1967GS *

Also Published As

Publication number Publication date
NL189383C (en) 1993-03-16
AU508242B2 (en) 1980-03-13
DE2647905C3 (en) 1987-07-09
JPS5252327A (en) 1977-04-27
DE2647905A1 (en) 1977-04-28
NL7611813A (en) 1977-04-26
GB1558395A (en) 1980-01-03
DE2647905B2 (en) 1980-12-11
AU1913976A (en) 1978-05-04

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