JPH0336147Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a multi-system color television receiver capable of receiving at least PAL and NTSC color television signals.

[Prior art]

Traditionally, color television broadcasting systems have been broadly divided into
There are three types: PAL, SECAM, and NTSC, and the broadcasting system adopted differs depending on the country.

By the way, in Europe, the Middle East, etc., depending on the region, it is possible to receive not only the broadcasts of one's own country but also the broadcasts of neighboring countries, but there may be cases where the broadcast format of the home country's broadcasts and the broadcasts of other countries are different.

Also, for example, some PAL video tape recorders can play back NTSC tapes on which NTSC color television signals have been recorded; in this case, the color subcarrier frequency of the played back NTSC color television signals is 4.43MHz. becomes normal
Different from NTSC color subcarrier frequency 3.58MHz.

As mentioned above, the color television signals of various broadcasting systems and the color subcarrier frequency are 4.43M.
To receive a special NTSC color television signal of Hz, depending on the format of the color television signal to be received, the filter bands of the video intermediate frequency amplification circuit and the audio intermediate frequency amplification circuit must be switched, the deflection circuit must be switched, It is necessary to use a multi-system color television receiver that switches the demodulation method of the color signal processing section.

By the way, PAL and color subcarrier are 3.58MHz,
A color signal processing section of a multi-system color television receiver capable of receiving a 4.43 MHz NTSC color television signal is configured as shown in FIG. 1, for example.

The color television signal amplified and detected by the video intermediate frequency amplification section is input to a first bandpass filter/amplifier (hereinafter referred to as BPA) 2 via the input terminal 1. , only the composite chroma signal including the burst signal is extracted from the color television signal.

Furthermore, the composite chroma signal of BPA2 is
The BPA 3 extracts only the chroma signal from the composite chroma signal, and outputs the chroma signal from the BPA 3 to the delay separation section 5 via the terminal 4.

Note that a color control volume 6 is connected to the second BPA 3, and the so-called color gain is adjusted by the volume 6.

Further, the second BPA 3 extracts a burst signal from the composite chroma signal based on the internally generated burst gate pulse, and outputs the burst signal to an automatic saturation control circuit (hereinafter referred to as ACC circuit) 7.
The burst signal is detected by the ACC circuit 7, and the first BPA2 is detected by the detected signal of the ACC circuit 7.
The gain of is feedback controlled.

Furthermore, the delay separation unit 5 has a 1H delay circuit that delays one horizontal scanning period (hereinafter referred to as H) and a transformer that separates and forms B-Y and R-Y color difference signals, and has a When the chroma signal is input to the separation unit 5, terminals 8 and 9 are connected to R-Y,
The B-Y color difference signals are separately output. Note that R represents a red primary color signal, B represents a blue primary color signal, and Y represents a luminance signal.

The RY color difference signal at the terminal 8 is input to the RY demodulation circuit 10, and the BY color difference signal at the terminal 9 is input to the BY demodulation circuit 11.

On the other hand, the burst signal of the second BPA 3 is generated by an identification circuit (hereinafter referred to as IDENT circuit) 12 and a phase detection circuit (hereinafter referred to as APC) used only in the case of PAL.
(referred to as a circuit) 13.

The APC circuit 13 then detects the burst signal using the output signal of the voltage controlled oscillator (hereinafter referred to as VCO) 14, and generates a control signal for controlling the oscillation frequency of the VCO 14 to the frequency of the burst signal.
Output to VCO14.

Furthermore, the VCO 14 generates a pair of signals whose phases are shifted by π/4 at the oscillation frequency, that is, whose phases are shifted by π/4.
A pair of shifted color subcarrier signals are output to the demodulation circuit 11 and the pulse switch circuit 16, respectively.
Note that the VCO 14 is attached with one or more crystal oscillators 15, and the VCO 14 is connected to the crystal oscillator 1.
In addition to free-running oscillation at a vibration frequency of 5, the oscillation frequency is 3.58MHz based on the receiving method.
It can be alternatively switched to 4.43MHz.

Also, between the IDENT circuit 12 and the ground,
An NTSC switch 17 and a capacitor 18 are provided in parallel, and in the case of NTSC, the switch 17 is turned on, and in the case of PAL, the switch 17 is turned off.

Furthermore, the IDENT circuit 12 and the switch circuit 16
A flip-flop circuit (hereinafter referred to as an FF circuit) 19 is provided between the FF circuit and the FF circuit, and the FF circuit 19 is inverted every 1H by a horizontal flyback pulse.

And when switch 17 is turned off, PAL,
The detected signal obtained by detecting the burst signal using the output signal of the FF circuit 19 is sent from the IDENT circuit 12 to the FF circuit 1.
9, and based on the detected signal, the FF circuit 1
The inversion operation of No. 9 is controlled in synchronization with the inversion of the burst signal.

Note that when the switch 17 is turned on during NTSC, the detection signal from the IDENT circuit 12 to the FF circuit 19 becomes 0, and at this time the FF circuit 19 stops its inversion operation.

Further, the switch circuit 16 performs an inverting operation in synchronization with the inverting operation of the FF circuit 19, and the switch circuit 16
By the inversion operation, the phase of the color subcarrier signal output to the demodulation circuit 10 via the switch circuit 16 is inverted in synchronization with the inversion of the burst signal.

Therefore, in the case of PAL in which the phase of the R-Y color difference signal is inverted every 1H, the color subcarrier signal whose phase is inverted every 1H is input to the demodulation circuit 10 by the inversion operation of the switch circuit 16. , R-Y color difference signals do not change in phase, the switch circuit 16 stops inverting, and the demodulation circuit 1
0, a color subcarrier signal with a constant phase is input.

Based on the input color subcarrier signal, the demodulation circuits 10 and 11 demodulate the R-Y and B-Y color difference signals, respectively, when receiving PAL and NTSC, and send the signals from the demodulation circuits 10 and 11 to the matrix circuit 20. The demodulated R-Y, B-Y color difference signals are output, and R-Y, G-
Y and B-Y color difference signals are output, respectively.

By the way, the delay separator 5 is configured to be applied to both PAL and NTSC, but if it is applied only to PAL, for example, the delay separator 5 configured as shown in FIG. 2 may be used.

The PAL chroma signal input to terminal 4 is input to the 1H delay circuit DL via the coupling capacitor C1, the impedance matching resistor R1, and the coil L1, and the chroma signal is delayed by the 1H delay of the circuit DL. The signal is converted into a chroma signal and input to the primary winding of the transformer T.

Further, the PAL chroma signal input to the terminal 4 is input to the intermediate tap of the secondary winding of the transformer T via the variable resistor VR1 and the coupling capacitor C2.

Since the secondary winding of the transformer T is bifilar-wound, the intermediate tap chroma signal, that is, the undelayed direct chroma signal and the delayed chroma signal, are added and subtracted, and R is applied to both ends of the secondary winding. -Y and B-Y color difference signals are generated, respectively.
The R-Y and B-Y color difference signals are separated.

In addition, R2 and R3 in Fig. 2 are impedance matching resistors provided in series between terminals 8 and 9, and C3 is a filter resistor provided between the connection point of resistors R2 and R3 and the ground. It is a capacitor.

Next, in the case of application to both PAL and NTSC, that is, in the case of the delay separator 5, the configuration is as shown in FIG. 3 based on the configuration of FIG. 2.

When PAL is received, terminal a becomes high level, terminal b becomes low level, and terminal a becomes high level, so the bias that is obtained by dividing the level of terminal a by bias resistors R4 and R5 is used as the base. The supplied first transistor Q1 of the NPN type is turned on, and the first diode D1 whose anode is supplied with the high level of the terminal a via the pull-up resistor R6 is turned on.

Note that the collector of transistor Q1 is connected to the 12 volt power supply terminal (+B), and the emitter of transistor Q1 is connected to a variable resistor for bias.
It is grounded via VR2, and is also connected to the power terminal (+
A bias set by bias resistors R7 and R8 provided in series between B) and ground is supplied to the cathode of the diode D1.

On the other hand, since terminal b becomes low level, terminal b
The second NPN transistor Q2 whose base is supplied with a bias whose level is divided by the bias resistors R9 and R10 is turned off, and the anode is connected to the emitter of the transistor Q2 via the supply resistor R11. The second diode D2 is also turned off.

Note that the collector of transistor Q2 is connected to the power supply terminal (+B), and the collector of transistor Q2 is connected to the power supply terminal (+B).
The emitter No. 2 is grounded via a bias resistor R12.

Therefore, the PAL chroma signal input to the terminal 4 is input to the delay circuit DL via the coupling capacitor C4, the transistor Q1, the coupling capacitor C5, the impedance matching resistor R13, and the coil L2. , a delayed chroma signal is input from the circuit DL to the primary winding of the transformer T.

In addition, the chroma signal of the emitter of transistor Q1 is transmitted not only to capacitor C5 but also to variable resistor VR2.
The chroma signal of the variable resistor VR2 is supplied to the intermediate tap of the secondary winding of the transformer T via the coupling capacitor C6, the diode D1, and the coupling diode C7.

Therefore, the transformer T is 1 as in the case of Fig. 2.
A delayed chroma signal that is the chroma signal at terminal 4 delayed by 1H is input to the secondary winding, and a direct chroma signal that does not delay the chroma signal at terminal 4 is input to the intermediate tap of the secondary winding. By adding and subtracting , R-Y, B-
Y color difference signals are generated, R-Y and B-Y color difference signals are separated, and the separated R-Y and B-Y
The color difference signals are input to demodulation circuits 10 and 11, respectively.

In addition, R14 in FIG. 3 is a bias resistor provided between the terminal 4 and the ground, and R15, R16.
is a resistor for impedance matching provided in series between terminals 8 and 9, R17 is a resistor R15,
A bias resistor is provided between the connection point of R16 and terminal a, and C8 is a filter capacitor provided between the connection point of resistors R15 and R16 and the ground.

Next, when receiving NTSC, terminal a becomes low level, terminal b becomes high level, and terminal a becomes low level, so transistor Q1,
Diode D1 is turned off and terminal b becomes high level, so transistor Q2 and diode D2 are turned on.

Therefore, the NTSC chroma signal input to terminal 4 is supplied to the intermediate tap of the secondary winding of transformer T via coupling capacitor C9, transistor Q2, resistor R11 and diode D2.
R-Y and B-Y color difference signals are generated at both ends of the next winding, and the R-Y and B-Y color difference signals are separated and input to demodulation circuits 10 and 11, respectively.

In other words, since the phase of the R-Y component of the PAL chroma signal is inverted every 1H, the capacitor C
5. To the transformer T via the resistor R13, the PAL delay dedicated signal path of the coil L2, and the delay circuit DL,
In addition to supplying a delayed chroma signal that is 1H delayed from the chroma signal at terminal 4, variable resistor VR2, capacitor C6, diode D1, and capacitor C7 are
to the transformer T via the PAL non-delay dedicated signal path,
A direct chroma signal consisting of a chroma signal from terminal 4 is supplied, and R-Y and B-Y color difference signals are separated.

Also, since the NTSC chroma signal does not invert the phase of the R-Y component, the resistor R11 and diode D2
A direct chroma signal consisting of the chroma signal at terminal 4 is supplied to the transformer T via the NTSC dedicated signal path, and RY and BY color difference signals are separated.

In addition, R- generated at both ends of the transformer T
In the case of PAL, the level of the Y and B-Y color difference signals is twice the level of the chroma signal input to the transformer T, and in the case of NTSC, it is the level of the chroma signal input to the transformer T. variable resistance
By adjusting VR2, R-Y, which occurs at both ends of the transformer T, in the case of PAL and in the case of NTSC, respectively.
The levels of the B-Y color difference signals are set to be the same.

Moreover, in the case of Figure 1, it is necessary to provide two types of signal paths through which PAL chroma signals pass, namely, a PAL delay-only signal path and a PAL non-delay-only signal path, and an NTSC-dedicated signal path through which NTSC chroma signals pass. , which makes the configuration complicated.

Also, the signal path through which the PAL chroma signal passes
If the signal path that the NTSC chroma signal passes through is different,
Since the difference in the amount of phase fluctuation during transmission between the PAL chroma signal and the NTSC chroma signal becomes large, in the case of Fig. 1, a phase correction capacitor C10 is connected between the anode of the diode D2 and the ground, and a coil L3 is connected.
It is necessary to provide a phase correction circuit consisting of series circuits, which further complicates the configuration.

In addition, JP-A No. 56-25885 also describes the signal path through which the PAL chroma signal passes, as in Figure 3.
It is disclosed that a signal path through which an NTSC chroma signal passes is provided separately, and in this case, the same drawbacks as in FIG. 3 occur.

[Purpose of invention]

This invention was made with the above points in mind, and it converts the filtered chroma signal from the television signal into a PAL undelayed chroma signal.
It uses an NTSC chroma signal and has an extremely simple configuration without degrading the frequency characteristics during NTSC reception.
The purpose is to separate and form color difference signals when receiving PAL and NTSC.

[Structure of the idea]

This invention is the fourth in a multi-system color television receiver capable of receiving at least PAL and NTSC color television signals.
As shown in FIG. 5, a delay separation section 5'' processes the chroma signal separated by the filter from the color television signal to separate and form two types of color difference signals;
5, a transistor Q3 to which the chroma signal is input to the base, the applied bias increases when receiving PAL and decreases when receiving NTSC, and between the emitter of the transistor Q3 and one 1H delay circuit DL. a diode D3 for opening and closing the signal path, which is provided in the PAL delay dedicated signal path and turns on when the bias applied to the transistor Q3 increases and turns off when the bias applied to the transistor Q3 decreases; The chroma signal is input to the next winding, and the chroma signal is input to the transistor Q3.
It is input to the intermediate tap of the secondary winding via the emitter and PAL, NTSC common signal path, and the PAL
and one transformer T that separates and outputs the two color difference signals to the secondary winding during NTSC reception, and a variable resistor VR3 for level setting provided between the emitter of the transistor Q3 and the ground.
, and is provided between the end of the emitter side of the variable resistor VR3 and the sliding piece, and is turned on only when receiving PAL to reduce the impedance between the emitter of the transistor Q3 and the ground, thereby preventing reception of PAL. This multi-system color television receiver is provided with a level adjustment diode D4 that equalizes the level of the two color difference signals at the time of NTSC reception and the level of the two color difference signals at the time of NTSC reception.

[Effect of idea]

Therefore, according to the multi-system color television receiver of this invention, when receiving PAL, the chroma signal separated by the filter from the television signal is transmitted from the emitter of transistor Q3 to PAL,
is input to the intermediate tap of the secondary winding of transformer T via the NTSC common signal path, and at the same time, diode D is input by increasing the applied bias of transistor Q3.
3 is turned on, the chroma signal at the emitter of transistor Q3 passes through the PAL delay dedicated signal path to 1H.
The chroma signal is also supplied to the delay circuit DL, and the chroma signal delayed by this delay circuit DL is input to the primary winding of the transformer T.
Separate color difference signals are formed.

In addition, during NTSC reception, diode D3 is turned off due to a decrease in the bias applied to transistor Q3, so the chroma signal separated by the filter from the television signal is passed through the PAL and NTSC common signal path to the secondary winding of transformer T. Two types of color difference signals are separated and formed using only the filtered chroma signal inputted only to the intermediate tap of the chroma signal.

Moreover, diode D4 is turned on only when PAL is received, the impedance between the emitter of transistor Q3 and ground is reduced, the signal level at the emitter is lowered, and the levels of both color difference signals when PAL and NTSC are received become equal.

Then, the chroma signal at the emitter of transistor Q3 is converted into a chroma signal that is not delayed when receiving PAL.
Chroma signal when receiving NTSC, PAL,
Since the signal is supplied to the intermediate tap of the secondary winding of the transformer T via the NTSC common signal path, the number of signal paths for the chroma signal is reduced, and the PAL delay dedicated signal path is turned on and off by switching the diode D3. Since level adjustment during PAL reception and NTSC reception is performed by switching the diode D4, the configuration is extremely simplified.

Furthermore, when receiving NTSC, both color difference signals are formed from chroma signals separated by a filter from the television signal, and the delayed output signal of the delay circuit DL is not used, so the frequency characteristics do not deteriorate.

Therefore, it is possible to separate and form color difference signals during PAL and NTSC reception with an extremely simple configuration without deteriorating the frequency characteristics during NTSC reception.

〔Example〕

Next, this invention will be described in the fourth section showing its practical example.
This will be explained in detail with reference to the drawings below.

First, FIG. 4 showing one embodiment will be explained.

FIG. 4 shows a delay separator 5'' when receiving PAL and NTSC color television signals, that is, a delay separator provided in place of the delay separator 5 in FIGS. 1 and 3. In the first
The same symbols as those in the figures and FIG. 3 indicate the same or equivalent parts.

When PAL is received, terminal a becomes high level, and the base bias of transistor Q3, whose base is connected to terminal a via bias resistor R17, is connected in series between the power supply terminal (+B) and ground. bias resistors R18 and R1
The base bias is increased from the base bias set by 9.

By the way, the collector of transistor Q3 is connected to the power supply terminal (+B), and a bias resistor R20 and a variable resistor VR3 for level setting are provided in series between the emitter of transistor Q3 and the ground. As the base bias of Q3 increases, the emitter potential of transistor Q3 increases.

Further, a third diode D3 forming a diode for opening and closing the signal path is connected to the emitter of the transistor Q3.
The anode of D is connected, and the diode D
Bias resistors R21 and R2 are placed on the cathode of 3.
A bias voltage obtained by dividing the voltage of the power supply terminal (+B) by 2 is applied.

Then, when the terminal a becomes high level and the emitter potential of the transistor Q3 rises, the diode D3 is turned on.

Further, the anode of a fourth diode D4 forming a level adjustment diode is connected to the connection point between the resistor R20 and the variable resistor VR3, and the cathode of the diode D4 is connected to the bias resistor R2.
Since terminal b becomes low level when PAL is received, diode D4
turns on.

Then, the transistor Q3 is turned on and the diode D3 is turned on, so that the chroma signal at the terminal 4 is transferred to the coupling capacitor C11, the emitter of the transistor Q3, and the diode D3.
3. 1H delay circuit DL via a PAL delay dedicated signal path consisting of a coupling capacitor C12, an impedance matching resistor R24, and a coil L3.
A delayed chroma signal obtained by delaying the chroma signal at terminal 4 by 1H is input from the circuit DL to the primary winding of the matching transformer T.

Also, the chroma signal at the emitter of transistor Q3 is connected to resistor 20 and coupling capacitor C13.
It is input to the intermediate tap of the secondary winding of transformer T via the PAL and NTSC common signal path.

That is, when receiving PAL, diode D3,
Capacitor C12, resistor R24, coil L3
A delayed chroma signal obtained by delaying the chroma signal at terminal 4 by 1H is input to the transformer T via the PAL delay dedicated signal path, and is input to the transformer T via the PAL and NTSC common signal path of resistor R20 and capacitor C13. A direct chroma signal consisting of 4 chroma signals is input.

Since the transformer T adds and subtracts the delayed chroma signal and the direct chroma signal, the transformer T
The R-Y and B-Y color difference signals are generated at both ends of the secondary winding, and the R-Y and B-Y color difference signals are separated. The color difference signals are input to demodulation circuits 10 and 11 via terminals 8 and 9, respectively.

In addition, the cathode of diode D4 and the variable resistor
Capacitor C1 for coupling between VR3 sliding piece
4 is provided, and when receiving PAL, the variable resistance for the chroma signal is turned on by turning on the diode D4.
The resistance value of VR3 is the resistance value between the sliding piece and the ground.

In addition, R25 in FIG. 4 is a bias resistor provided between the terminal 4 and the ground, R26, R27
is a resistor for impedance matching provided in series between terminals 8 and 9, C15 is a resistor R26,
This is a filter capacitor provided between the connection point of R27 and ground.

Next, when receiving NTSC, terminal a becomes low level and terminal b becomes high level.

When the terminal a becomes low level, the base bias of the transistor Q3 decreases, the emitter potential of the transistor Q3 decreases, and the diode D3 turns off.

Furthermore, since the terminal b becomes high level, the diode D4 is also turned off.

Therefore, the chroma signal at terminal 4 is connected to capacitor C11, the emitter of transistor Q3, and
Resistor R20, capacitor C13 PAL, NTSC
It is input to the intermediate tap of the secondary winding of the transformer T via a common signal path.

That is, when receiving NTSC, the chroma signal is only input directly to the transformer T via the PAL and NTSC common signal path, and as in the case of Fig. 3, R- is connected to both ends of the secondary winding of the transformer T. Y and B-Y color difference signals are generated respectively, and the R-Y and B-Y color difference signals are separated, and the separated R-Y and B-Y color difference signals are The signals are input to demodulation circuits 10 and 11 via terminals 8 and 9, respectively.

By the way, when receiving NTSC, diode D4 is turned off, so variable resistance VR for chroma signals is
The resistance value of Q3 is the total resistance value between both ends, which is higher than when receiving PAL, and the level of the chroma signal at the emitter of transistor Q3 is higher than when receiving PAL.

Then, by adjusting the variable resistor VR3, the level of the chroma signal at the emitter of transistor Q3 is
When receiving NTSC, the level of the R-Y and B-Y color difference signals input to demodulation circuits 10 and 11 is set to be approximately twice that of PAL reception, and the level of the R-Y and B-Y color difference signals input to demodulation circuits 10 and 11 is set to be approximately twice that of PAL reception. become equal in time.

Therefore, according to the embodiment, when receiving PAL, the chroma signal at the emitter of transistor Q3 is transmitted to the PAL delay dedicated signal path and PAL, NTSC.
They each pass through a common signal path, and during NTSC reception, the chroma signal at the emitter of transistor Q3 is
Because PAL and NTSC pass through the common signal path, PAL,
NTSC common signal path when receiving PAL and NTSC
In this case, for example, there is no need to provide a dedicated NTSC signal path as shown in FIG. 3, and the configuration is simplified.

In addition, since the PAL chroma signal and the NTSC chroma signal pass through the same signal path, the difference in phase fluctuation during transmission between the PAL chroma signal and the NTSC chroma signal is small.For example, the phase correction circuit shown in Figure 3 There is no need to use the above, and the configuration is further simplified.

Furthermore, variable resistor VR3 and diode D4
By providing this, R-Y when receiving PAL,
The level of the B-Y color difference signal can be made equal to the level of the R-Y and B-Y color difference signals when receiving NTSC, and in addition, when receiving NTSC, it is possible to make the level of the color difference signal of B-Y equal to the level of the color difference signal of R-Y and B-Y when receiving NTSC. Since both color difference signals are formed by the chroma signal and the delayed output signal of the delay circuit DL is not used, the frequency characteristics do not deteriorate.

Next, FIG. 5 showing another embodiment will be explained.

Figure 5 shows the delay separator 5 when receiving not only PAL and NTSC color television signals but also SECAM color television signals, and the same symbols as in Figure 4 indicate the same or equivalent parts. , the difference is as follows.

That is, instead of terminal a in Fig. 4, PAL
becomes high level when receiving NTSC,
A terminal a' that becomes low level when receiving SECAM is provided, and a terminal b' that becomes low level when receiving PAL and high level when receiving NTSC and SECAM is provided in place of terminal b in Fig. 4, and ,
The resistor R21 in FIG. 4 is omitted, a bias resistor 28 is provided in place of the resistor R22, and further,
A fifth diode D5 is connected to the cathode of the diode D3.
through the cathode, anode and terminal 26 of
In addition to connecting the SECAM limiter amplifier 27, a coupling capacitor C16 and a terminal 28 are connected to the non-ground terminal of the primary winding of the transformer T.
This is the point where the SECAM switch circuit 29 is connected.

When receiving PAL and NTSC, the operation is similar to that shown in Fig. 4, and when receiving SECAM, the SECAM chroma signal is sent to the limiter amplifier 27.
At this time, similarly to when receiving NTSC, diode D3 is turned off and diode D4 is turned on, so the chroma signal at terminal 26 is input to terminal 26 via diode D5, capacitor C12, and resistor R2.
4. Input to delay circuit DL via coil L1,
A delayed chroma signal obtained by delaying the chroma signal at the terminal 26 by 1H is input from the delay circuit DL to the primary winding of the transformer T.

By the way, in the SECAM color television signal, the color difference signal is formed as a sequential signal every 1H, so the transformer T is generated only by the delayed chroma signal.
R-Y and B-Y color difference signals are generated at both ends of the secondary winding, respectively, and the R-Y and B-Y color difference signals are separated.

Therefore, in the case of Fig. 5, the same effect as in the case of Fig. 4 can be obtained, and the PAL delay dedicated signal path of diode D3, capacitor C12, resistor R24, and coil L3 is connected to the SECAM chroma signal signal. Can be shared on the road.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the color signal processing unit of a multi-system color television receiver capable of receiving PAL and NTSC color television signals, Figure 2 is a wiring diagram of the separation delay unit used only for PAL, and Figure 3 The figure shows a connection diagram of a conventional separation delay unit used in both PAL and NTSC. Figure 4 and the following figures show an embodiment of the multi-system color television receiver of this invention. Figure 4 shows the main points of one embodiment. Fig. 5 is a wiring diagram of main parts of another embodiment. 5'', 5...delay separation section, C12, C13,
C14... Capacitor, D3, D4... Third and fourth diodes, DL... 1H delay circuit, Q3... Third transistor, R20... Resistor, VR3... Variable resistor.

Claims (1)

[Claims for Utility Model Registration] In a multi-system color television receiver capable of receiving at least PAL and NTSC color television signals, a chroma signal separated by a filter from the color television signal is processed to produce two types of color difference signals. A transistor Q3 to which the chroma signal is inputted to the base of the delay separation unit 5'', 5, whose applied bias increases when receiving PAL and decreases when receiving NTSC, and an emitter of the transistor Q3. A signal path opening/closing circuit provided in a signal path dedicated to PAL delay between one horizontal scanning period delay circuit DL, and turned on by an increase in the bias applied to the transistor Q3 and turned off by a decrease in the bias applied to the transistor Q3. The output signal of the diode D3 and the delay circuit DL is input to the primary winding, and the chroma signal is input to the transistor Q3.
It is input to the intermediate tap of the secondary winding via the emitter and PAL, NTSC common signal path, and the PAL
and one transformer T that separates and outputs the two color difference signals to the secondary winding during NTSC reception, and a variable resistor VR3 for level setting provided between the emitter of the transistor Q3 and the ground.
, and is provided between the end of the emitter side of the variable resistor VR3 and the sliding piece, and is turned on only when receiving PAL to reduce the impedance between the emitter of the transistor Q3 and the ground, thereby preventing reception of PAL. A multi-system color television receiver comprising a level adjustment diode D4 that equalizes the level of the two color difference signals at the time of NTSC reception and the level of the two color difference signals at the time of NTSC reception.